Compact Modeling of Multi-Gate Transistors

Gajanan Dessai

A Dissertation Presented in Partial Fulﬁllment of the Requirements for the Degree Doctor of Philosophy

Approved November 2012 by the Graduate Supervisory Committee: Gennady Gildenblat, Chair Colin McAndrew Yu Cao Hugh Barnaby

ARIZONA STATE UNIVERSITY

December 2012 ABSTRACT

Scaling of the classical planar MOSFET below 20 nm gate length is facing not only technological diﬃculties but also limitations imposed by short channel effects, gate and junction leakage current due to quantum tunneling, high body doping induced threshold voltage variation, and carrier mobility degradation. Non-classical multiple-gate structures such as double-gate (DG) FinFETs and surrounding gate

ﬁeld-eﬀect-transistors (SGFETs) have good electrostatic integrity and are an alternative to planar MOSFETs for below 20 nm technology nodes. Circuit design with these devices need compact models for SPICE simulation.

In this work physics based compact models for the common-gate symmetric DG-FinFET, independent-gate asymmetric DG-FinFET, and SGFET are developed. Despite the complex device structure and boundary conditions for the

Poisson-Boltzmann equation, the core structure of the DG-FinFET and SGFET models, are maintained similar to the surface potential based compact models for planar MOSFETs such as SP and PSP.

TCAD simulations show diﬀerences between the transient behavior and the capacitance-voltage characteristics of bulk and SOI FinFETs if the gate-voltage swing includes the accumulation region. This eﬀect can be captured by a compact model of FinFETs only if it includes the contribution of both types of carriers in the

Poisson-Boltzmann equation. An accurate implicit input voltage equation valid in all regions of operation is proposed for common-gate symmetric DG-FinFETs with intrinsic or lightly doped bodies. A closed-form algorithm is developed for solving the new input voltage equation including ambipolar effects. The algorithm is verified for both the surface potential and its derivatives and includes a previously published analytical approximation for surface potential as a special case when ambipolar effects can be neglected. The symmetric linearization method for common-gate symmetric

DG-FinFETs is developed in a form free of the charge-sheet approximation present in

i its original formulation for bulk MOSFETs. The accuracy of the proposed technique is veriﬁed by comparison with exact results.

An alternative and computationally efficient description of the boundary between the trigonometric and hyperbolic solutions of the Poisson-Boltzmann equation for the independent-gate asymmetric DG-FinFET is developed in terms of the Lam- bert W function. Efficient numerical algorithm is proposed for solving the input voltage equation. Analytical expressions for terminal charges of an independent- gate asymmetric DG-FinFET are derived. The new charge model is C∞ continuous, valid for weak as well as for strong inversion condition of both the channels and does not involve the charge-sheet approximation. This is accomplished by developing the symmetric linearization method in a form that does not require identical boundary conditions at the two Si-SiO2 interfaces and allows for volume inversion in the DG-FinFET. Verification of the model is performed with both numerical computations and 2D TCAD simulations under a wide range of biasing conditions. The model is implemented in a standard circuit simulator through Verilog-A code. Sim- ulation examples for both digital and analog circuits verify good model convergence and demonstrate the capabilities of new circuit topologies that can be implemented using independent-gate asymmetric DG-FinFETs.

ii Dedicated to my parents and teachers

iii ACKNOWLEDGEMENTS

This dissertation would not have been possible without the assistance and support of many people. First of all I would like to express my sincere gratitude to my advisor Prof. Gennady Gildenblat for his guidance, encouragement, and support throughout my graduate years at Arizona State University (ASU). His attitude and professionalism towards work has been a source of inspiration for me. He always encouraged me to explore new ideas.

I would also like to thank members of my Ph.D. supervisory committee,

Dr. Colin McAndrew, Prof. Yu Cao, and Prof. Hugh Barnaby for taking their time to review my dissertation and for their valuable comments. I am highly indebted to

Dr. Colin McAndrew. His insightful comments and questions during our technical discussion and review of the manuscripts helped improve my dissertation research.

I would also like to thank Prof. Bertan Bakkaloglu for discussing circuit aspects of compact modeling.

I would like to thank Prof. A. B. Bhattacharyya for introducing me to the exciting ﬁeld of semiconductor devices and compact modeling. I came across various compact MOSFET models and modeling approaches during my association with his work on the book titled “Compact MOSFET Models for VLSI Design”.

As a part of PSP Compact Modeling Group I was fortunate to work with fel- low group mates Dr. Wei Yao (now with Xilinx), Dr. Zeqin Zu (now with Freescale),

Dr. Xin Li (now with GLOBALFOUNDRIES), and Dr. Weimin Wu (now with Texas

Instruments). I thank them for their friendship and having many illuminating dis- cussions on topic related to device physics and compact modeling. The support of the staﬀ from Electrical Engineering Department at ASU is also greatly appreciated.

My most rewarding experience was the summer I spent at GLOBALFOUNDRIES where I had an opportunity to work on practical aspects of CMOS technology and modeling.

iv My graduate life at ASU would not have been wonderful and fulﬁlling without many of my friends whom I met during my time at ASU. I thank them all.

Most importantly, I would like to thank my family for their immense support and encouragement, without whom none of this would have been possible. Especially,

I heartily thank my dear wife Prajakta for her lasting love, understanding, and encouragement.

v TABLE OF CONTENTS

Page

LISTOFFIGURES ...... viii

CHAPTER

1 INTRODUCTION ...... 1

1.1 Scaling Limits of Conventional Planar MOSFETs ...... 1

1.2 Multi-Gate MOSFET Structures and their Advantages ...... 3

1.3 CompactModeling ...... 7

1.4 Organization of the Dissertation ...... 8

1.5 Summary of the Original Results Obtained in this Work ...... 9

1.6 List of Publications Related to this Work ...... 10

2 ELECTROSTATICS of the COMMON-GATE SYMMETRIC DG-FinFET 12

2.1 Introduction...... 12

2.2 TCAD simulations of bulk and SOI FinFETs ...... 13

2.3 Poisson-Boltzmann Equation for DG-FinFET ...... 16

2.4 Common-Gate Symmetric DG-FinFET ...... 18

2.5 Exact IVE for Common-Gate Symmetric DG-FinFET ...... 20

2.6 Approximate Input Voltage Equation ...... 23

2.7 UnipolarIVE ...... 27

2.8 Closed Form Solution of the Ambipolar IVE ...... 29

3 ELECTROSTATICS of the INDEPENDENT-GATE ASYMMETRIC DG-

FinFET ...... 35

3.1 Introduction...... 35

3.2 Trigonometric Solution ...... 37

3.3 HyperbolicSolution ...... 39

3.4 SolutionSpace ...... 41

3.5 Analytical Expression for the Partition Lines ...... 46

3.6 A New Solution Technique for the IVEs ...... 47

vi Chapter Page 4 CURRENT and CHARGE MODELS for the COMMON-GATE SYMMET-

RICDG-FinFET...... 50

4.1 Introduction...... 50

4.2 Exact Drain Current ...... 51

4.3 Charge-Sheet Approximation ...... 52

4.4 Symmetric Linearization Method ...... 57

4.5 Terminal Charges ...... 59

4.6 Symmetric Linearization Method for SGFET ...... 66

5 CURRENT and CHARGE MODELS for the INDEPENDENT-GATE ASYM-

METRICDG-FinFET ...... 71

5.1 Drain Current Model ...... 71

5.2 Reformulation of Drain Current in PSP Form ...... 74

5.3 Eﬀective Gate Charge Density Concept ...... 77

5.4 Terminal Charge Model ...... 82

5.5 ResultsandDiscussion...... 85

5.6 Model Implementation and Simulation ...... 93

6 CONCLUSIONS ...... 96

REFERENCES...... 98

APPENDIX

A Derivationof(2.26)...... 108

B Equivalent form of Equation (2.26) ...... 110

C Asymptotes of ϕ0 for the Common-Gate Symmetric DG-FinFET . . . . . 112

D Derivation of q˜n and αl ...... 115 E Comparison of Symmetric Linearization Method for bulk MOSFETs and

DG-FinFETs ...... 118

F Derivation of (5.74)-(5.77) ...... 122

G Common-Gate Symmetric DG-FinFET as a Special Case of Independent-

GateAsymmetricDG-FinFET ...... 124

vii LIST OF FIGURES

Figure Page

1.1 Structure of (a) bulk FinFET and (b) SOI FinFET...... 4

1.2 Independent double-gate (a) FinFET on SOI and (b) ETSOI...... 6

1.3 Cross-section of various ﬂavors of multi-gate MOSFETs (a) π-gate , (b)

Ω-gate, (c) quad-gate and (d) surrounding-gate...... 7

2.1 Simulated device structures (a) bulk FinFET and (b) SOI FinFET. . . . 14

2.2 TCAD simulated normalized transcapacitances (a) Cgg, Cbg and (b) Cdg for bulk and SOI FinFETs with source, drain, and bulk connected. . . . 15

2.3 Cross-section of the common-gate symmetric DG-FinFET. φ is the work-

function of gate material...... 16

2.4 Energy band diagram (a) across the channel (Vd = Vs = 0) and (b) along the channel indicating the reference energy level for measuring electro-

static potential ψ. Solid lines corresponds to ψ = 0 whereas dashed lines

corresponds ψ > 0. Efm is the gate Fermi level...... 17

2.5 a(ϕ0) dependence; tsi = 20 nm, T = 300 K...... 24 2.6 Surface and center potential versus gate voltage. Circles represent ex-

act calculations based on (2.27) and the lines corresponds to the new

approximation (2.38); Vc = 0 V, tsi = 20 nm, tox = 2 nm, ∆φ = 0 V, T = 300 K...... 25

2 2 2.7 (a) dψs/dVgs and (b) d ψs/dVgs versus gate voltage. Circles represent exact calculation and the lines corresponds to the new approximation;

Vc = 0 V, tsi = 20 nm, tox = 2 nm, ∆φ = 0 V, T = 300 K...... 26 2.8 Surface and center potential obtained by solving IVE using closed form

algorithm is compared with that obtained by bisection method. Lines and

symbols corresponds to the results obtained from closed form algorithm

and numerical solution, respectively; tox = 2 nm, tsi = 20 nm, ∆φ = 0. . 31

viii Figure Page 2.9 Error in the surface potential obtained by new algorithm when compared

to that obtained by numerical solution of (2.50) for Vc = 0V. Device parameters are the same as in Fig. 2.8...... 32

2.10 (a) First and (b) second derivative of the surface potential with respect

to the gate voltage obtained by solving IVE using closed form algorithm

is compared with that obtained by numerical solution. Lines and sym-

bols corresponds to the results obtained from closed form algorithm and

numerical solution, respectively. Device parameters are same as in Fig. 2.8. 33

2.11 (a) Surface potential obtained by solving IVEs (2.50), (2.57), and (2.61)

for Vc = 0 V, (b) Surface potential near ﬂatband condition. Device parameters are same as in Fig. 2.8...... 34

3.1 Cross-section of the independent-gate asymmetric DG-FinFET. φ1 and

φ2 are the workfunctions of gate-1 and gate-2, respectively...... 37

3.2 Regions of operation on the V1-V2 plane for Vc = 0.5 V, tsi = 20 nm,

tox1 = 2 nm and tox2 = 40 nm...... 42

3.3 Partition lines on the V1-V2 plane with Vc as parameter obtained from

numerical solution (circles) and analytical solution (lines); tsi = 20 nm,

tox1 = tox2 = 2 nm...... 44

3.4 Partition lines on V1-V2 plane with Vc as parameter obtained from nu-

merical solution (circles) and analytical solution (lines); tsi = 20 nm,

tox1 = 2 nm , tox2 = 40 nm...... 44

3.5 Partition lines on V1-V2 plane with Vc as parameter obtained from nu-

merical solution (circles) and analytical solution (lines); tsi = 10 nm,

tox1 = 2 nm , tox2 = 40 nm...... 45 3.6 Regions of operation on the V V plane for V = 0.5 V, t = 10 nm, 1 − 2 c si tox1 = 2 nm and tox2 = 20 nm...... 48

4.1 Relative error for drain current Id using expression (4.11); tox = 1.5 nm,

T = 300 K, Vds = 1 V...... 53

ix Figure Page 4.2 g(θ) versus θ...... 55

4.3 Position dependence of surface potential in DG-FinFET; tox = 1.5 nm,

tsi = 20 nm, and Vds = 2 V...... 60 4.4 Normalized transcapacitances of (a) bulk FinFET and (b) SOI FinFET

versus gate voltage for Vds = 1V. Symbols represents TCAD simulations results and the lines corresponds to a compact model...... 63

4.5 Relative error for the terminal charges, using symmetric linearization

method for DG-FinFET; tsi = 20 nm, tox = 1.5 nm, T = 300 K, Vds = 1 V. 64 4.7 Cross-section of the SGFET...... 66

4.8 Relative error for the terminal charges, using symmetric linearization

method for SGFET; R = 8 nm, tox = 1.5 nm, T = 300 K, Vds = 1 V. . 69 5.1 Comparison of terminal charges (a) and transcapacitances (b) obtained

from the new model and numerical computations; tox1 = tox2 = 2 nm ,

Vg2 = 0.4 V and Vd = 1.5 V...... 87 5.2 Comparison of terminal charges (a) and transcapacitances (b) obtained

from the new model and numerical computations; tox1 = tox2 = 2 nm,

Vg2 = 1.0 V and Vd = 0.5 V...... 88 5.3 Comparison of terminal charges (a) and transcapacitances (b) obtained

from the new model and numerical computation; tox1 = tox2 = 2 nm,

Vg1 = 2.0 V and Vg2 = 0.6 V...... 89 5.4 Comparison of transcapacitances obtained from the new model and nu-

merical computations; tox1 = 2 nm, tox2 = 10 nm, Vg2 = 0.6 V and

Vd = 0.5 V...... 90 5.5 Comparison of transcapacitances obtained from the new model and nu-

merical computations; tox1 = 2 nm, tox2 = 10 nm, Vg2 = 1.5 V and

Vd = 2.0 V...... 90

x Figure Page 5.6 Comparison of transcapacitances obtained from the new model and nu-

merical computations; tox1 = 2 nm, tox2 = 10 nm, Vg1 = 2.0 V and

Vg2 = 0.6 V...... 91 5.7 Comparison of terminal charges (a) and transcapacitances (b) obtained

from the new model and numerical computation at Vds = 0.0 V; tox1 = 2

nm, tox2 = 10 nm, and Vg2 = 0.7 V...... 92 5.8 Double balanced mixer...... 94

5.9 Schmitttrigger...... 94

5.10 Harmonic balance simulation of double balance mixer shown in Fig. 5.8. 95

5.11 Transfer characteristics of independent-gate FinFET Schmitt trigger shown

inFig.5.9...... 95

xi Chapter 1

INTRODUCTION 1.1 Scaling Limits of Conventional Planar MOSFETs

Planar MOSFETs have been the basis of CMOS technologies since their inception in 1960 [1]. Continuous improvement as predicted by Moore’s law [2] has been achieved by scaling and material innovations keeping the classical planar structure unchanged. Scaling the channel length results in higher currents and hence faster switching speed. Scaling is accomplished by following certain rules called “scaling rules” to attain optimum device performance [3]. The aim is to have a transistor with high on-state current, zero off-state current, a sharp transition from off-state to on-state and the terminal currents apart from the drain to the source terminal must be zero i.e., zero parasitic effects. Classical scaling rules reduce device dimensions

(such as channel length, gate oxide thickness, junction depth) and increase doping concentration which helps in boosting on-current and keeps oﬀ-current under control.

Reducing device dimensions by scaling not only resulted in higher packing density

(i.e. more circuits functionality on given die area) but also higher speed, lower power, reduced manufacturing cost, and other performance improvements.

As the feature size approached the sub-100 nm range, the scaling of planar

MOSFETs was confronted with many technological limitations as well as problems related with the device characteristics. The problems with scaling of planar MOS-

FETs are severe short channel eﬀects (SCEs) including threshold voltage (Vth) roll- oﬀ, drain induced barrier lowering (DIBL), and subthreshold-slope (SS) degradation

[4]. This is because as the channel length is reduced the ﬁeld lines originating from the drain/source regions strongly inﬂuence the channel potential and reduce the barrier seen by the injecting electrons at the source which enhances the drain current

[5]. Ideally, the barrier is controlled by the applied gate ﬁeld. To increase the gate control of the channel the gate oxide must be made thinner and the channel doping must be increased as suggested by the classical scaling rules. Although this approach

1 has been followed over the decades, in recent years this has given rise to a series of undesirable eﬀects such as parasitic tunneling current, mobility degradation, and random dopant ﬂuctuation (RDF).

As the gate oxide thickness is reduced the gate current, due to the quantum tunneling, increases exponentially and therefore increases the standby power dissipation. In the current sub-100 nm planar CMOS technologies the gate oxide thickness has been reduced to the point where the power drain from gate leakage is comparable to the power used for circuit switching [6]. In highly doped MOSFETs the presence of a large number of dopant ions hinders carrier motion due to Coulomb scattering and reduces mobility [7]. Additionally, higher channel doping increases the surface electric field for a given inversion level which results in reduced carrier mobility due to surface scattering [8]. The high surface electric field confines the carriers in a narrow potential well resulting in quantum confinement effects [9]. Also a high gate oxide field depletes the poly-silicon gate with appreciable amount of potential drop thus reducing the effective gate bias [10]. Quantum confinement [4, 11] and poly-silicon depletion [12] leads to a threshold voltage shift and gate capacitance decreases. On the other hand, the RDF effect originate due to the discrete nature of dopant ions in the channel region which become prominent at small geometry because the total number of dopant ions is small; hence, their statistical fluctuation is large, which alters the transistor properties especially threshold voltage and drive current

[13]. High body doping increases the electric ﬁeld in the reverse biased source/drain to body junction which signiﬁcantly enhances the junction band-to-band tunneling

(BTBT) current [14].

Even with the above mentioned detrimental side eﬀects of scaling, the classical planar MOSFET has been scaled to 28 nm technology node with ultra-shallow junction, pocket implants [15], and super-steep retrograde channel doping [16]. Ma- terial innovations such as high-k dielectric, metal-gate, mechanically inducing strain in the channel and employing alternative channel materials such as SiGe, Ge semi-

2 conductors helped to push the planar CMOS technology under 100 nm node. With the high-k dielectric as gate insulator material the eﬀective insulator thickness is de- creased without decreasing the physical insulator thickness enabling the higher gate control on the channel and the metal-gate eliminates the poly-silicon depletion eﬀect

[17, 18]. Suppression of source/drain lateral electric ﬁeld can be achieved by locally raising the channel doping near source and drain junctions via pocket implants [19].

Process induced strain is used to achieve signiﬁcant mobility enhancement [20]. With such ingenious technological developments the planar MOSFET has been pushed to the limit. A paradigm shift in device structure was necessary for further scaling and performance improvement.

Multi-gate MOSFETs where the gates are present on more than one side of the channel are seen as an alternative for pushing the CMOS scaling forward under sub-20 nm gate length [21]. The primary advantage of the Multi-gate MOSFETs is the excellent control of SCEs [22, 23] without relying on channel doping, which makes it potentially scalable to the end of the SIA ITRS roadmap [24].

1.2 Multi-Gate MOSFET Structures and their Advantages

Having more than one gate around the channel improves the electrostatic integrity

which is the measure of electric ﬁeld lines from the source/drain inﬂuencing the

channel region. Higher electrostatic control by the gate results in reduced short

channel eﬀects. Various ﬂavors of alternative device structures having multiple gates

have been proposed to replace the classical planar MOSFET and extend the channel

length scalability into the sub-20 nm regime. Multi-gate MOSFETs shown in Fig. 1.1

have been proven to be strong candidates for the future CMOS technology [25] and

been in production in Intel at 22 nm technology node [26]. Such MOSFETs are

known as FinFETs [27, 28]. FinFETs oﬀer increased immunity to small-geometry

eﬀects, a near-ideal subthreshold slope, and certain other advantages like the in-

creased mobility associated with low or no doping. Lower doping results in less

eﬀective electric ﬁeld which reduces surface carrier scattering and gate tunneling.

3 The use of an undoped or lightly doped body provides immunity to threshold voltage and drive current variation due to statistical dopant ﬂuctuations in FinFETs.

Because of strong coupling between gates the whole potential across the silicon film moves along with the gate voltage and the carriers are not just induced at the in- terface but throughout the body which is called “volume inversion” [29]. This leads to a near-ideal subthreshold slope (60mV/decade) which improves device turn-off behavior and reduces off-state current. For planar MOSFETs the substrate doping not only served to control the SCEs but also enabled threshold voltage adjustment.

In FinFETs the freedom for threshold voltage adjustment is lost with the absence of doping. However, in FinFETs the required threshold voltage is usually set by gate work-function adjustment [30]. Moreover, the absence of doping increases the carrier mobility due to lack of Coulomb scattering and reduces the eﬀects of random dopant

ﬂuctuation. Thus FinFETs devices oﬀer the potential for maintaining the scalability of the CMOS technology as it approaches the “end of the road-map” phase of its development [25].

Gate Gate

SiO2 SiO2

Si body Si body

(a) (b) Figure 1.1: Structure of (a) bulk FinFET and (b) SOI FinFET.

4 Depending upon the substrate type, FinFETs can be classiﬁed broadly as a bulk (cf. Fig. 1.1a) or SOI type (cf. Fig. 1.1b). Both types of FinFETs have merits associated with their structure. Some of the advantages of bulk FinFETs are process compatibility with planar CMOS and reduced self-heating, whereas the

SOI FinFETs benefit from lower junction capacitances. Apart from these merits the choice of particular structure is decided by the fabrication cost and ease of integrating in the present technology setup. Typically, the body thickness is small compared to its height thus the two side gates have a prominent effect in controlling the channel inversion level as compared to the top gate. Also the top gate influence on the channel reduces when its gate oxide is thicker than the side gate oxide. Since the

FinFET is controlled by two side gates it is generally called a double-gate (DG)

FinFET. Nevertheless, when the body thickness and top gate oxide are comparable to its height and side gate oxide, respectively, the presence of the top gate cannot be neglected. Such a device is called a tri-gate (TG) FinFET [31].

It can be noted that when the top gate is removed the result is a FinFET with two independent-gate as shown in Fig. 1.2a. Both gates can be tied together to form a common-gate DG-FinFET or can be separated to form an independent-gate DG-

FinFET. Structurally, DG-FinFETs can be symmetric or asymmetric. DG-FinFETs with identical parameters (e.g., oxide thickness and gate work-function) for both gates are symmetric otherwise they are called asymmetric. A planar independent- gate asymmetric DG-FinFET is shown in Fig. 1.2b where a thin Si channel is locally isolated from the bulk-Si substrate by a thin buried dielectric layer. The structure resembles an SOI MOSFET with a extremely thin body [32] and relatively thin gate oxide and is called an extremely thin SOI (ETSOI) or ultra-thin body SOI

(UTB-SOI). This structure combines the best features of the classical MOSFET

(low parasitic source/drain contact resistance) with the best features of SOI technology (improved electrostatic integrity); however, it poses technological diﬃculty in aligning the bottom gate with the top gate.

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(c) (d) Figure 1.3: Cross-section of various ﬂavors of multi-gate MOSFETs (a) π-gate , (b) Ω-gate, (c) quad-gate and (d) surrounding-gate.

1.3 Compact Modeling

Circuit design with new devices requires the development of compact models. Com- pact models are a concise mathematical description of the transistor terminal characteristics in closed form. A compact model maintains a balance between the amount of physics captured for model accuracy and amount of approximation made for model simplicity [40, 41, 42]. Compact models provide a bridge between circuit designers and chip manufacturers. Traditionally, compact models of MOSFETs were threshold voltage based where carrier transport via “drift” and “diﬀusion” were modeled separately and then stitched together by smoothing functions to maintain continuity. Example of such models are BSIM3v3, BSIM4, and MM9. Although inversion charge-based models are powerful alternatives of threshold-based models they have

7 their own limitations such as modeling in the accumulation region where there is no inversion charge.

Recently, surface-potential-based compact models like PSP have attracted significant attention because of their better physical description of the device characteristics. Apart from accuracy, complexity, and physical framework (threshold voltage, inversion charge, or surface potential based) the typical compact model may differ by inclusion of second order effects and parasitics, physical (charge conservation, symmetry, reciprocity) and mathematical (continuity) consistency, simulation speed and memory usage, availability in EDA design tools, and documentation

[40, 43].

Due to the advantages oﬀered by multi-gate transistors there is presently considerable interest in developing compact models in order to assess the impact of multi-gate transistors on circuit performance. Guided by the development of compact models of the bulk [44, 45, 46, 47, 48, 49, 50, 51, 52] and SOI [53, 54, 55]

MOSFET one may expect that a compact model of multi-gate transistors will consist of an essentially physical core model of an ideal long-channel transistor to which small-geometry eﬀects [56, 57] and quantum corrections [58, 59] are added using suitably chosen approximations.

Various inversion charge- and surface-potential-based compact models of double-gate FinFETs have been developed. The compact model of FinFETs developed in this work is based on the same principles as the PSP models of conventional planar bulk and SOI MOSFETs. The structural similarity to PSP means that various small-geometry eﬀects can be introduced in a similar manner.

1.4 Organization of the Dissertation

This dissertation is organized as follows. In Chapter 2 we present TCAD simulations

illustrating the diﬀerences in C-V characteristics between bulk and SOI FinFETs.

The rigorous input voltage equation (IVE) in terms of the elliptic integrals is for-

8 mulated for the common-gate symmetric DG-FinFET and replaced by an accurate approximation suitable for compact modeling applications which takes into account both electron and hole contributions to the charge density. An accurate approximate solution for solving the IVE that does not require an iterative loop is developed.

The IVE for independent-gate asymmetric DG-FinFETs is developed in Chap- ter 3 with an explicit expression for the boundary between trigonometric and hyperbolic forms of the IVE. However, the IVE for this case is unipolar and valid from weak to strong inversion. An eﬃcient numerical technique for solving the unipolar

IVE is proposed.

In Chapter 4 a drain current expression for common-gate symmetric DG-

FinFETs in [60] is reformulated in the PSP form. A symmetric linearization method free from the charge-sheet approximation is developed for common-gate DG-FinFETs and SGFETs and is used to derive an accurate terminal charge model.

In Chapter 5 the symmetric linearization method is extended to independent- gate asymmetric DG-FinFETs by deﬁning the concept of eﬀective charge density.

The new model is implemented in Verilog-A following the style of the PSP model

[45] and circuit simulations are performed to verify its convergence robustness and demonstrate its capabilities to model novel FinFET circuits.

The summary and conclusions of this dissertation are presented in the last chapter.

1.5 Summary of the Original Results Obtained in this Work

In this work compact models for the common-gate symmetric DG-FinFET, SGFET, and independent-gate asymmetric DG-FinFET are developed. Original results obtained in this work are:

• Development of an ambipolar IVE for common-gate symmetric DG-FinFETs

which includes the contribution of both types of carriers (electrons and holes)

9 to charge density and is valid for all regions of operation (from accumulation

to inversion).

• An accurate closed-form algorithm for solving the ambipolar IVE of common-

gate symmetric DG-FinFETs and proof that the previously known unipolar

approximation of the IVE can be derived as a special case of the more general

ambipolar IVE.

• The symmetric linearization method is developed for common-gate symmetric

DG-FinFETs and SGFETs in a form free of the charge-sheet approximation

present in its original formulation for bulk MOSFETs.

• An alternative and computationally eﬃcient description of the boundary be-

tween the trigonometric and the hyperbolic solutions of the Poisson-Boltzmann

equation for the independent-gate asymmetric DG-FinFET is developed.

• Eﬃcient numerical solution of the independent-gate asymmetric DG-FinFET

IVE suitable for circuit simulator implementation is proposed.

• The symmetric linearization method is generalized and extended to the inde-

pendent gate asymmetric DG-FinFET and an accurate terminal charge model

for that device is derived.

• The core model structure for FinFETs is maintained similar to that of PSP for

planar MOSFETs.

• The compact models are implemented in commercial circuit simulators through

Verilog-A and simulations were performed to verify good model convergence.

1.6 List of Publications Related to this Work

The publications that resulted from this work are given below. The text of this dissertation, in part, is a reprint of the material as it appears in following list of publications. The dissertation author was the primary investigator and author of these publications.

10 (i) G. Dessai, and G. Gildenblat, “Approximate Closed-Form Solution of Ambipo-

lar Input Voltage Equation for the Common-Gate Symmetric FinFET,” Solid-

State Electron., vol. 75, no. 9, pp. 77–80, 2012.

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11 Chapter 2

ELECTROSTATICS of the COMMON-GATE SYMMETRIC DG-FinFET 2.1 Introduction

In surface potential based compact models such as PSP the drain current and the terminal charges are expressed as explicit functions of the surface potentials at the source and drain ends of the channel. The surface potential is obtained by solving an

IVE which is an implicit relation between the surface potential, the gate voltage and the imref splitting. Thus the IVE forms an essential part of any surface potential based compact MOSFET model. The IVE is derived from the integration of the one dimensional Poisson-Boltzmann equation. Generally, the resulting IVE is an implicit function of the surface potential and has to be solved iteratively. In PSP an eﬃcient explicit algorithm is proposed for solving the IVE [61]. Sometimes the

IVE is reformulated in terms of a variable on which the surface potential has explicit dependence [62].

In this chapter the Poisson-Boltzmann equation is formulated for the DG-

FinFET and the IVE is derived for the common-gate symmetric structure subject to appropriate boundary conditions. An explicit algorithm for solving the IVE of the common-gate symmetric DG-FinFET is formulated.

Most often compact models of FinFETs are developed by including the contribution of only one type of charge carrier to the charge density while integrating the Poisson-Boltzmann equation. This is the unipolar approximation. The inclusion of both type of carriers results in an IVE involving special functions which are undesirable for compact modeling as they are not available in Verilog-A and their implementation is computationally complex. Although the unipolar approximation is sufficient in many cases it is not universal and, for example, does not allow one to reproduce the difference in C-V curves between bulk and SOI FinFETs [63]. It also does not lead to a FinFET model valid in all regions of operation. Hence it is desirable to develop a compact FinFET model that includes ambipolar effects

12 (contribution of both holes and electrons to the charge density) based on a suitably modiﬁed IVE which does not involve special functions.

For the common-gate symmetric FinFET the IVE accounting for ambipolar eﬀects can be formulated in terms of elliptic integrals [64]. This formulation is physical and complete but is diﬃcult to use for compact modeling. Hence in [63] we have presented an approximate IVE which is well conditioned and numerically equivalent to that in [64] but does not include elliptic integrals or other quadratures.

The transcendental IVE in [63] was solved iteratively and implemented in a circuit simulator to demonstrate the validity of the approach for compact modeling.

Additionally, we developed and veriﬁed an accurate approximate solution that does not require an iterative loop [65]. Our approach is inﬂuenced by that in

[62] which in turn includes some ideas from the earlier work dealing with the surface potential equation for a traditional bulk MOSFET [61]. In particular, we will show that the results in [62] can be recovered as a special case of this work corresponding to the unipolar approximation.

2.2 TCAD simulations of bulk and SOI FinFETs

In this section we present TCAD simulations illustrating the diﬀerences in C-V

characteristics between bulk and SOI FinFETs. The simpliﬁed structures of bulk

and SOI FinFETs are shown in Figs. 2.1a and 2.1b, respectively. The gate contact is

metal with a mid-gap work function and the substrate of the bulk FinFET is p-type

with doping concentration of 5 1015 cm 3. The source and drain are heavily doped × − n-type and the body is intrinsic. The bulk contact is placed at the bottom of the

device.

Small signal a.c. simulations were performed around the d.c. bias point with

100 Hz signal frequency in order to investigate the low-frequency behavior. The

source, drain, and the bulk terminals are connected together as shown in the inset

of Fig. 2.2a. The gate voltage V is swept from 1.5 to 1.5 V. The simulated ca- gs −

13 y Drain Drain z x Gate Body Gate Body

Source Gate Source Gate

Oxide Doped silicon substrate substrate

(a) (b) Figure 2.1: Simulated device structures (a) bulk FinFET and (b) SOI FinFET.

pacitances Cgg, Cbg and Cdg for bulk and SOI FinFETs are shown in Fig. 2.2. In the inversion region, electrons are provided by the source and the drain contacts for

bulk and SOI FinFETs and similar capacitance characteristics are obtained for both

FinFET structures. However, in the accumulation region of the bulk FinFET, holes

are supplied by the substrate through the bulk contact, whereas such a supply of

holes is absent in the SOI FinFET. These holes need to be supplied from the thermal

generation process and through the source/drain contacts where their concentration

is extremely low. Even at a frequency as low as 100 Hz such processes fall short

of establishing the quasi-equilibrium concentration of holes resulting in negligible

capacitance Cgg and Cbg. Thus in agreement with TCAD simulations the accumulation capacitance for the SOI FinFET can be assumed to be negligible for all practical

purposes.

SPICE-like circuit simulators evaluate capacitances as derivatives of the ter-

minal charges with respect to the terminal biases. In surface-potential-based compact

models for bulk and SOI MOSFETs, the terminal charges are expressed as functions

Bulk C 1 SOI gg

0.8

0.6

0.4

0.2 C bg

Normalized transcapacitances 0

−1.5 −1 −0.5 0 0.5 1 1.5 V [V] gs (a)

dg Bulk 0.5 SOI 0.4 0.3 0.2 0.1 0

Normalized transcapacitance C −0.1 −1.5 −1 −0.5 0 0.5 1 1.5 V [V] gs (b)

Figure 2.2: TCAD simulated normalized transcapacitances (a) Cgg, Cbg and (b) Cdg for bulk and SOI FinFETs with source, drain, and bulk connected. of surface potentials at the source and the drain ends of the channel [45, 66]. The surface potential is obtained by solving the IVE derived from the Poisson-Boltzmann equation. A similar approach is followed in surface-potential-based compact models of the DG-FinFET [67, 68] which is valid from weak to strong inversion regions of

15 operation. To extend the validity of these models to the accumulation region, an accurate IVE derived by considering both electron and hole contributions to the charge density is needed. The TCAD result shown in Fig. 2.2 clearly illustrate the diﬀerence in C-V characteristics of the two FinFET structures and need to be reproduced by a compact model.

2.3 Poisson-Boltzmann Equation for DG-FinFET

Vg Gate φ

tox y

Vs Vd n+ x tsi n+ Source Drain L

tox φ Gate Vg

Figure 2.3: Cross-section of the common-gate symmetric DG-FinFET. φ is the work- function of gate material.

To understand the electrostatics of DG-FinFETs one needs to solve the

Poisson-Boltzmann equation within the device subject to the boundary conditions.

Fig. 2.3 shows the cross-section of a common-gate symmetric DG-FinFET. The grad- ual channel approximation (used universally for the development of compact models for MOSFETs) helps to write the Poisson-Boltzmann equation in one-dimension as

d2ψ ρ 2 = (2.1) dx −si where

ρ = q(p n) (2.2) − is the total charge density for an undoped body,

ψ V n = n exp − c (2.3) i φ t

16 Gate SiO2 Si body SiO2 Gate

Efm ψs ψ0 Ei qVg qVg

t 0 t t + t x − ox si si ox (a)

n+ source undoped Si body

Ef qψ

Ev y (b)

Figure 2.4: Energy band diagram (a) across the channel (Vd = Vs = 0) and (b) along the channel indicating the reference energy level for measuring electrostatic potential ψ. Solid lines corresponds to ψ = 0 whereas dashed lines corresponds ψ > 0. Efm is the gate Fermi level. is the electron concentration,

ψ p = pi exp (2.4) −φt

17 is the hole concentration, x is the direction across the channel, ψ is the electrostatic potential (cf. Fig. 2.4), V (F F )/q is the electron and hole imref splitting c ≡ n − p with value Vs at the source and value Vd at the drain, si is the permittivity of the

silicon, φt is the thermal voltage, ni is the intrinsic electron concentration and pi is

the intrinsic hole concentration. Note that pi = ni and the body is assumed to be undoped. The reference level for ψ is selected as in [69] to facilitate the recovery

of the theory in [69] as special case of the present work. In writing (2.4) which is

the hole contribution to the charge density, the holes are assumed to be in quasi-

equilibrium. This assumption is valid for FinFETs with n+ source/drain contacts

which act as sources and sinks only for electrons [64]. Substituting (2.2)-(2.4) in

(2.1) and using fact that ni = pi yields

2 d ψ q ψ Vc ψ 2 = ni exp − ni exp (2.5) dx si φt − −φt or equivalently, −Vc 2 d ψ φ e 2φt ψ V /2 = t · sinh − c (2.6) dx2 2 φ Ldi · t where the intrinsic Debye length [70] is

siφt Ldi = . (2.7) s 2qni

Normalizing ψ and x we have

d2ϕ = sinh (ϕ) (2.8) dξ2 where ψ V /2 ϕ = − c , (2.9) φt and Vc xe− 4φt ξ = . (2.10) Ldi 2.4 Common-Gate Symmetric DG-FinFET

From the mathematical point of view the essential diﬀerence between a common-gate

symmetric DG-FinFET and a bulk MOSFET is that in the latter case the boundary

18 conditions

lim ψ(x) = 0 (2.11) x →∞ and ∂ψ lim = 0 (2.12) x →∞ ∂x allow one to obtain an IVE directly from the ﬁrst integral of the Poisson-Boltzmann

equation. For common-gate symmetric DG-FinFETs (2.11) does not apply and even

though (2.12) takes an equally simple form of (cf. 2.3)

∂ψ = 0 (2.13) ∂x x=tsi/2

it is impossible to arrive at the IVE from the ﬁrst integral. In other words, in the DG-

FinFET there is no point where the values of ψ and ∂ψ/∂x are known a priori. This

necessitates the derivation of the IVE based on the second integral of the Poisson-

Boltzmann equation which, even in the case of undoped symmetric DG-FinFETs,

is formulated in terms of incomplete elliptic integrals and is not directly suitable

for the purpose of the compact modeling. Only if the unipolar approximation is

made can the IVE be rigorously reduced to the familiar form [69] almost universally

used in compact models of undoped DG-FinFETs. Our approach is to develop an

accurate simpliﬁed form for the IVE which does not involve elliptic integrals and can

be solved numerically within a compact model. This is accomplished in two steps. In

section 2.5 we reformulate the rigorous IVE using an approach developed earlier in

electrochemistry [71, 72] which is more suitable for our purpose than the equivalent

form recently rediscovered in [64] and which has also appeared earlier in the work on

electrocapillary slits [73]. The normalized form of the Poisson-Boltzmann equation

is the same in [71, 72, 64, 73]. Thus the developed rigorous IVE (including the

contributions of both electrons and holes) is simpliﬁed in the next section.

For further references we note that ﬂatband condition at a point y along

the channel corresponds to ψ = ψs = Vc/2 where ψs is the surface potential. This

implies that for Vd > Vs we may have ﬂat bands only for one but not for all planes

19 y = const. We note in passing that the ﬂatband condition can be included in the

model formulation only if both kinds of carriers are considered. For a ﬁxed y we

have a potential minimum at the center of the channel if ψ > Vc/2 and a potential

maximum if ψ < Vc/2. In terms of the gate bias the flatband condition corresponds to V =∆φ + V /2 since the oxide field (V ∆φ ψ )/t = 0 where at flatband gs c gs − − s ox ψs = Vc/2. Here Vgs is gate to source bias and ∆φ is the workfunction difference between gate material and body. At a given plane y = const. we have a potential

minimum for Vgs > ∆φ + Vc/2 and a maximum Vgs < ∆φ + Vc/2.

2.5 Exact IVE for Common-Gate Symmetric DG-FinFET

By integrating (2.8) and using the boundary condition ϕ = ϕ we have |x=tsi/2 0 dϕ 2 = 2 (cosh ϕ cosh ϕ0) (2.14) dξ · − where ψ0 Vc/2 ϕ0 = − (2.15) φt

and ψ0 is the electrostatic potential for x = tsi/2 (in the middle of the body). In terms of ϕ0, the ﬂatband condition for a plane y = const. corresponds to ϕ0 = 0, a potential minimum to ϕ0 > 0 and maximum to ϕ0 < 0. Thus denoting

Vc η = sgn(ϕ0)= sgn Vgs ∆φ (2.16) − − 2 we have dϕ sgn = η sgn(ξ ξ ), (2.17) dξ 0 · − where sgn() is the sign function and

t V ξ = si exp c (2.18) 0 2 L · −4φ · di t corresponds to ξ at x = tsi/2. From (2.14) and (2.17)

dϕ = η sgn(ξ ξ ) 2 cosh ϕ 2 cosh ϕ . (2.19) dξ · − 0 · − · 0 p

20 From the continuity of the x-component of the displacement vector at x = 0

Vc dϕ L e 4φt V = di V ∆φ c φ ϕ (2.20) dξ r t φ gs 2 t s ξ=0 − c si t − − −

where rc = Csi/Cox, Csi = si/tsi, Cox = ox/tox and

ψs Vc/2 ϕs = − . (2.21) φt

From (2.19) and (2.20)

Vc · ηL e 4 φt V di V ∆φ c φ ϕ cosh ϕ cosh ϕ = 0. (2.22) √ gs 2 t s s 0 2 rctsiφt − − − − − · p

To obtain an IVE we need another equation relating ϕ0 and ϕs. Integrating (2.19),

ϕ dϕ0 = η ξ ξ0 . (2.23) √2 cosh ϕ0 2 cosh ϕ0 · | − | ϕZ0 · − · The integral in (2.23) is an elliptic integral of the ﬁrst kind and can be written in

several equivalent forms [71, 73, 72, 64]. In what follows we use the complete

π/2 dθ K(k)= ; 0 k 1 (2.24) √1 k2 sin2 θ ≤ ≤ Z0 − and incomplete

t dθ F (t, k)= ; 0 k 1 and 0 t<π/2 (2.25) √1 k2 sin2 θ ≤ ≤ ≤ Z0 − elliptic integrals of the ﬁrst kind in Legendre’s form [74]. Then as shown in Ap- pendix A (2.23) is equivalent to

ηϕ0 − η(ϕ0 ϕ) 2 1 ηϕ0 ηϕ0 e ξ ξ0 F sin− e 2 , e− K e− = − | − |. (2.26) − 2 Setting ξ = 0 and ϕ = ϕs yields the desired form of the IVE including the contributions of both electrons and holes:

ηϕ0 Vc · − 2 4 φt η(ϕ0 ϕs) − 1 ηϕ0 ηϕ0 tsie F sin− e 2 , e− K e− = , (2.27) − − 4 Ldi ·

21 where ϕ0 as a function of ϕs is given by (2.22). In the Appendix B we show that this form of the IVE is mathematically equivalent to the formulation in [64]. The reason for choosing (2.27) as a starting point in this work is that from (2.27) Taur’s unipolar approximation [69] appears naturally. To see this set η = 1 and e ηϕ0 0 − ≈ for ϕ0 & 5 and note that by (2.24), (2.25) K(0) = π/2 and F (t, 0) = t. Then (2.27) becomes ϕ0 Vc 2 4·φ ϕ −ϕ − t 1 0 s π tsie sin− e 2 = (2.28) − 2 − 4 L · di Rearranging (2.28),

t ϕ V ϕ = ϕ + 2 ln sec si exp 0 c (2.29) s 0 · 4 L 2 − 4 φ · di · t or, equivalently,

t ψ V ψ = ψ + 2 φ ln sec si exp 0 − c , (2.30) s 0 · t 4 L 2 φ · di · t which is precisely the IVE in the form obtained in [69] by retaining the contribution of electrons and neglecting the contribution of holes to the space charge density.

Similarly, for ϕ . 5 (2.27) can be reduced to 0 − t ϕ V ϕ = ϕ 2 ln sec si exp 0 c (2.31) s 0 − · 4 L − 2 − 4 φ · di · t or, equivalently,

t ψ ψ = ψ 2 φ ln sec si exp 0 , (2.32) s 0 − · t 4 L −2 φ · di · t which is an approximation that can be also obtained directly from (2.5) by retaining the contribution of holes and neglecting the contribution of electrons to the space charge density. Note that in the presence of n+ source/drain contacts the hole imref is approximately constant throughout the device so the imref splitting Vc does not enter (2.32). In weak inversion or weak accumulation the diﬀerence between ψs or

ψ0 [i.e. the last term in (2.30) and (2.32)] is much less than φt which means that in the condition of validity of the unipolar approximation ψ0 can be replaced by ψs.

22 2.6 Approximate Input Voltage Equation

For ϕ close to ϕ0 (near the ﬂat-band) it is possible to obtain ϕs as a function of

ϕ0 in a closed form including contribution to the space charge of both electrons and holes. Using a second order Taylor expansion

1 cosh ϕ = cosh ϕ + (ϕ ϕ )sinh ϕ + (ϕ ϕ )2 cosh ϕ + (2.33) 0 − 0 0 2 − 0 0 · · ·

in (2.23) yields

ϕ dϕ0 1 = η ξ ξ cosh 2 ϕ . (2.34) 2 0 0 2 tanh ϕ0 (ϕ0 ϕ0) + (ϕ0 ϕ0) | − | ϕZ0 · · − − p Integrating and using the boundary condition ϕ = ϕs at ξ = 0 we ﬁnd

ϕ = ϕ + 2 tanh ϕ sinh2 a (2.35) s 0 · 0 ·

where −Vc · t e 4 φt √cosh ϕ a = si 0 . (2.36) 4 L · di At this point we have the unipolar approximation (2.29) for ϕ0 & 5, the unipolar approximation (2.31) for ϕ0 . 5 and bipolar approximation (2.35) near ﬂatband.

The next step is to develop a C∞ class approximation to the rigorous IVE (2.27) which has (2.29), (2.31) and (2.35) as proper limiting cases. This is done as follows.

First we note that

2 a6 sinh2 a = ln sec √2 a · + (2.37) · − 15 · · · h i The a(ϕ ) dependence near ﬂatband, for ϕ . 5, is shown in Fig. 2.5 for two values 0 | 0| 3 of Vc. While a can be of the order of 10− , the sixth order term in (2.37) is of the order 10 18 and is totally inconsequential. Hence for ϕ . 5 the relation between − | 0| ϕs and ϕ0 (2.35) is numerically indistinguishable from

ϕ = ϕ + 2 tanh ϕ ln sec √2 a (2.38) s 0 · 0 · · h i

23 in which we have approximated sinh2 a by the ﬁrst term in (2.37). From Fig. 2.5 it

can also be seen that for higher Vc the value of a is further reduced which increases the accuracy of approximation made in (2.38). The advantage of switching from

(2.35) to (2.38) is that (2.38) contains not only (2.35) but also (2.29) and (2.31) as

its proper limits. For example if ϕ0 > 5 and from (2.36)

−3 x 10 1.5

1 Vc = 0 V a

0.5

0.2 0 −5 0 5 ϕ0

Figure 2.5: a(ϕ0) dependence; tsi = 20 nm, T = 300 K.

t ϕ V √2 a si exp 0 c , (2.39) · ≈ 4 L 2 − 4 φ · di · t then (2.29) is recovered from (2.38) once we note that in this range tanh ϕ 1. 0 ≈ Similarly, for ϕ < 5 and from (2.36) 0 − t ϕ V √2 a si exp 0 c . (2.40) · ≈ 4 L − 2 − 4 φ · di · t Since this time tanh ϕ 1 we obtain (2.31). We stress that while (2.35) is a step 0 ≈− towards a uniﬁed bipolar approximation to the exact IVE (2.27), neither (2.35) nor

(2.29) or (2.31) are used in the model formulation. In what follows we work directly with (2.38) which covers all regions of operation and obviates the need for regional approximations.

24 It remains to check the accuracy of (2.38) in terms of the surface potential and its derivatives. The new IVE is solved numerically using the Newton-Raphson method. The results presented in Figs. 2.6, 2.7 (and several other extensive computations) show that (2.38) is an extremely accurate approximate form of (2.27) and contains the same information about the device physics. Hence there is no trade-oﬀ of any kind in switching from (2.27) to (2.38). Note also that in Figs. 2.6, 2.7 we show only the curves for Vc = 0 since this is the worst case for the accuracy of (2.38) as discussed above (cf. Fig. 2.5). Substituting for a from (2.36) in (2.38) yields

0.6 ψs

0.4 ψ0 0.2 [V] 0

ψ 0 , s

ψ −0.2

−0.4

−0.6 −1 −0.5 0 0.5 1 Vgs [V] Figure 2.6: Surface and center potential versus gate voltage. Circles represent exact calculations based on (2.27) and the lines corresponds to the new approximation (2.38); Vc = 0 V, tsi = 20 nm, tox = 2 nm, ∆φ = 0 V, T = 300 K.

ϕ (ϕ )= ϕ + 2 tanh(ϕ ) ln sec b 2 cosh ϕ , (2.41) s 0 0 · 0 · 1 · 0 h p i where t exp( x /4) b = si − n , (2.42) 1 4 L · di and Vc xn = . (2.43) φt

25 1

0.8 gs 0.6 /dV s

dψ 0.4

0.2

0 −1 −0.5 0 0.5 1 Vgs [V] (a) 4

2 [1/V] 2 gs 0 /dV s ψ 2 d −2

−4 −1 −0.5 0 0.5 1 Vgs [V] (b) 2 2 Figure 2.7: (a) dψs/dVgs and (b) d ψs/dVgs versus gate voltage. Circles represent exact calculation and the lines corresponds to the new approximation; Vc = 0 V, tsi = 20 nm, tox = 2 nm, ∆φ = 0 V, T = 300 K.

With this notation the IVE (2.22) [63] becomes

f(ϕ0) = 0 (2.44)

26 where

f(ϕ )= ϕ (ϕ ) x + b 2 cosh[ϕ (ϕ )] 2 cosh ϕ , (2.45) 0 s 0 − gn 2 · s 0 − · 0 q b = 4 ηr b , (2.46) 2 · c 1

η = sgn(xgn), (2.47) x x = x n , (2.48) gn g − 2 and Vgs ∆φ xg = − . (2.49) φt An equivalent form of (2.45) used in this work to develop a closed form solution

algorithm in Section 2.8 is

f(ϕ )= ϕ x + b 2 sinh(ϕ ) sinh[p(ϕ )] + 2 cosh(ϕ )[cosh p(ϕ ) 1] 1/2 0 s − gn 2 { 0 0 · 0 0 − } (2.50)

where

p(ϕ ) = 2 tanh(ϕ ) ln sec b 2 cosh ϕ . (2.51) 0 · 0 · 1 · 0 h p i The IVE (2.50) is better conditioned than (2.45) near flatband where ϕ ϕ x . 0 ≈ s ≈ gn For example, for x . 10 8 the square root term in (2.45) becomes zero if double | gn| − precision calculations are used. This creates difficulties for computing and coding the derivative df/dϕ0 near the flatband while solving the IVE . The IVE (2.50) does

not suﬀer from this problem except at a single ﬂatband point where we have ϕ0 = 0 and there is no need to solve the IVE. Once the IVE is solved the surface potential can be obtained from (2.41) and the gate charge density can be written as

q = 2 C (V ∆φ ψ ) (2.52) g · ox g − − s

where the factor of 2 is from the presence of two gates.

2.7 Unipolar IVE

We now investigate the special case of (2.45) corresponding to x & 5. This | gn| is useful not only for comparison with earlier work on the unipolar closed form

27 approximation [62] but as a ﬁrst step in the development of an explicit algorithm to compute ϕ0(Vgs, Vc) from new ambipolar IVE.

Physically, the condition x & 5 means that only one type of carrier con- | gn| tributes appreciably to the charge density within the active region of the device. To simplify (2.45) in this case we introduce

ϑ = b1 exp(ηϕ0/2). (2.53) and reformulate (2.41) as

ϑ2 ϕs = η ln 2 + 2 η ln [sec (ϑ)] , (2.54) b1 ! · where we have used the approximations

2 cosh(ϕ ) exp(ηϕ ) (2.55) · 0 ≈ 0 and

tanh(ϕ ) η (2.56) 0 ≈ for ϕ & 5. Substituting (2.54) in (2.45) and using the approximation 2 cosh(ϕ ) | 0| · s ≈ exp(ηϕs) we obtain the IVE in terms of ϑ

ln(ϑ sec ϑ) + 2 r ϑ tan ϑ F = 0 (2.57) · c − b where η x x /2 t F = gn − n + ln si . (2.58) b 2 4 L · di The unipolar IVE (2.57) corresponds to that in [62] when η = 1 and only the electron

contribution is included. In this case

ϑ θ b exp(ϕ /2), (2.59) ≈ ≡ 1 0 x x t F F g − n + ln si , (2.60) b ≈ ≡ 2 4 L · di and (2.57) becomes

ln(θ) + ln (sec θ) + 2 r θ tan θ F = 0 (2.61) · c −

28 which is the precisely the IVE given in [62]1.

When (2.57) is used the surface potential is related to ϑ by (2.54) and (2.21).

Physically, ϑ is proportional to √n where n is the electron (η = 1) or hole (η = 1) 0 0 − concentration in the middle of the body.

The inversion charge (electron) density is an important parameter in compact

modeling of MOSFETs and its absolute value per channel can be approximated in

the inversion region:

q = C (V ∆φ ψ ) . (2.62) n ox g − − s Note that unlike for planar bulk MOSFETs the inversion charge density for DG-

FinFETs is a linear function of surface potential due to the absence of doping. In

the accumulation region the inversion charge density can be neglected, however,

(2.62) can be used to estimate hole charge density per channel in the accumulation

region. To write qn in terms of θ we substitute the unipolar approximation (2.54) with η = 1 in (2.62) and using (2.61) yields

q = 4 C φ q (2.63) n · si t i

where

qi = θ tan θ (2.64) is the normalized inversion charge density.

2.8 Closed Form Solution of the Ambipolar IVE

The range of ϑ in (2.57) is between 0 and π/2 [62]. The asymptotic solutions for ϑ

corresponding to ϑ 0 and ϑ π/2 are developed in Appendix C and are used → → (0) to obtain asymptotic solutions for ϕ0 using (2.53). These are denoted as ϕ0 and (π/2) ϕ0 . The three step algorithm similar to that in [62] is developed in [65] to solve the IVE (2.50):

ϕ0 = ϕ00 +∆ϕ01 +∆ϕ02 (2.65)

1 In [62] the θ is denoted as β.

29 where 1 (0) (π/2) (0) (π/2) 2 ϕ00 = ϕ0 + ϕ0 + η ϕ0 ϕ0 + 0.001 . (2.66) 2 " r − # The correction term ∆ϕ01 is given by [62]

f f f 2 f 0f 000 ∆ϕ = 1+ f 00 + f 00 (2.67) 01 −f 2 f 2 f 2 − 3 0 · 0 0 2 2 3 3 where f and its derivatives f 0 = df/dϕ0, f 00 = d f/dϕ0, and f 000 = d f/dϕ0 are

calculated at ϕ0 = ϕ00. The correction term ∆ϕ02 is also given by (2.67) but with

f, f 0, f 00, and f 000 evaluated at ϕ0 = ϕ00 +∆ϕ01.

Once ϕ0 is found the surface and the center potentials can be obtained from (2.15), (2.21), and (2.41). In Fig. 2.8 the surface and the center potentials obtained

by closed form algorithm are compared with that obtained using numerical solution

for three diﬀerent values of Vc. It is seen that the new closed form algorithm accurately reproduces the exact results. The absolute error is found to be less than

0.01pV as shown in Fig. 2.9. Similar results are obtained for various device dimen-

sions and bias combinations. Fig. 2.10 shows the ﬁrst and second derivatives of ϕs

with respect to Vgs which (as is essential for compact modeling work) vary smoothly

as functions of Vgs. Fig. 2.11a shows the surface potential obtained by solving IVEs (2.50), (2.57), and (2.61). In the hole enhancement region (i.e. x 5 ) − gn − (2.61) does not apply and (2.57) must be used instead. Fig. 2.11b shows the surface

potential near the ﬂat band condition. As far as the accuracy is concerned the use

of the unipolar approximation (2.57) results in the error of less than 1nV which is

acceptable for compact modeling applications. However it results in a discontinuity

“cusp" (non existing derivative dϕs/dVg) at ﬂatband condition xgn = 0 (which corresponds to Vgs = 0 in Fig. 2.11 where Vc = 0). This is the motivation for using (2.50) rather than (2.57).

The new algorithm for solving the IVE has been implemented in Verilog-A as part of the compact FinFET model [67, 63] and further tested for accuracy and

1.5 ψs ψ0 1.0 1 0.5 [V]

0 0.5 , ψ

s Vc=0.0 V ψ 0

−0.5

−1 −0.5 0 0.5 1 1.5 2 Vgs [V] Figure 2.8: Surface and center potential obtained by solving IVE using closed form algorithm is compared with that obtained by bisection method. Lines and symbols corresponds to the results obtained from closed form algorithm and numerical solution, respectively; tox = 2 nm, tsi = 20 nm, ∆φ = 0. convergence. In agreement with Fig. 2.8 the results are indistinguishable from those obtained from iterative solution of the IVE.

31 5

0 Error in surface potential [fV] −5 −1 −0.5 0 0.5 1 1.5 2 Vg[V ] Figure 2.9: Error in the surface potential obtained by new algorithm when compared to that obtained by numerical solution of (2.50) for Vc = 0V. Device parameters are the same as in Fig. 2.8.

32 1

0.8

gs 0.6 /dV s

dψ 0.4 Vc=0.0 V 0.5 1.0

0.2

0 −1 −0.5 0 0.5 1 1.5 2 Vgs [V] (a)

2 [1/V] 2 gs 0 /dV s ψ 2

d −2

Vc=0.0 V 0.5 1.0 −4 −1 −0.5 0 0.5 1 1.5 2 Vgs [V] (b) Figure 2.10: (a) First and (b) second derivative of the surface potential with respect to the gate voltage obtained by solving IVE using closed form algorithm is compared with that obtained by numerical solution. Lines and symbols corresponds to the results obtained from closed form algorithm and numerical solution, respectively. Device parameters are same as in Fig. 2.8.

33 0.5

0 [V] s

ψ (2.50,2.57) 0.5 −

(2.61) 1 − 1 0.5 0 0.5 1 − − Vgs [V]

(a)

(2.50) 1 (2.57) 0 [nV] s

ψ 1 −

2 (2.61) −

3 − 2 1 0 1 2 − − Vgs [nV]

(b) Figure 2.11: (a) Surface potential obtained by solving IVEs (2.50), (2.57), and (2.61) for Vc = 0 V, (b) Surface potential near ﬂatband condition. Device parameters are same as in Fig. 2.8.

34 Chapter 3

ELECTROSTATICS of the INDEPENDENT-GATE ASYMMETRIC DG-FinFET 3.1 Introduction

In this chapter the Poisson-Boltzman equation for an independent-gate asymmetric

DG-FinFET is solved and the IVEs are derived. The presence of independent gates with diﬀerent bias conditions and gate oxide thicknesses destroys the symmetry of the device and results in diﬀerent boundary conditions at gate-1 and gate-2. Conse- quently, the boundary condition (2.13) does not apply for the independent gate asymmetric DG-FinFET. The solution of the Poisson-Boltzmann equation (2.5) with both electron and holes contribution to the charge density involves special functions [71].

However, neglecting holes for an n-channel device simplifies the integration and the solution of the Poisson-Boltzmann equation has a trigonometric or hyperbolic form depending upon the bias conditions and device parameters. As the IVEs take different functional forms (trigonometric and hyperbolic), the appropriate form to solve needs to be determined before solving the IVEs. This situation has no analog in compact modeling of other field effect transistors. We derive an explicit expression for the boundary between the trigonometric and the hyperbolic potential solutions.

An eﬃcient numerical algorithm is proposed for solving the IVEs to obtain surface potentials at gate-1 and gate-2.

Fig. 3.1 shows the cross-section of the independent-gate asymmetric DG-

FinFET where the origin of x-coordinate is placed at the center of the body to

be consistent with earlier work on the independent-gate asymmetric DG-FinFET

[75, 76, 77]. To simplify integration of the Poisson-Boltzmann equation we start

with (2.5) considering only electrons and neglect the hole contribution to the charge

density (i.e. we assume ψ(x) > 3 φ ): · t d2ψ qn ψ V = i exp − c (3.1) dx2 φ si t

35 Multiplying both sides by 2 dψ and integrating yields · dx 1/2 dψ φ 2 ψ V = σ t exp − c + c (3.2) dx L φ − " di t # where φ 2 ψ V c = E2 t exp x0 − c , (3.3) x0 L φ − di t

ψx0 and Ex0 are the electrostatic potential and electric ﬁeld, respectively, at some point x along the path of integration, and σ is the sign of dψ in the neighborhood 0 − dx of x0. Integrating (3.2) we obtain

φt 1 √c σ√cx0 σ√cx ψ(x)= V 2 φ ln sinh tanh− + (3.4) c − · t √cL σE − 2 φ 2 φ ( di " x0 ! · t · t #) 1 1 When c< 0 we can use identity tanh− (ix) = i tan− (x) and sinh(ix) = i sin(x) to avoid encountering complex numbers which yields

φt 1 √ c σ√ cx0 σ√ cx ψ(x)= Vc 2 φt ln sin tan− − − + − (3.5) − · (√ cLdi " σEx0 ! − 2 φt 2 φt #) − · · Thus depending on the sign of c the potential ψ(x) can have trigonometric or hyper-

bolic form. To select the sign of σ it can be noted that for hyperbolic case ψ(x) is

monotonic within the device as ψ(x) has sinh function. Physically, for this case ψ(x)

should be monotonically decreasing function of x for V1 > V2 and monotonically in- creasing function of x for V < V where V = V ∆φ , ∆φ is the work-function 1 2 j gj − j j diﬀerence between the body and the gate-j, and j = 1, 2. Thus σ can be selected as

σ = sgn(V V ) and x can be any point within the device. However, for trigono- 1 − 2 0 metric case as ψ(x) has sin function there exist a potential minimum (within or outside the device) and the sign of Ex0 depends on location of x0. As suggested in [77] if we set x = t /2 for V V and x = t /2 for V < V then one can 0 − si 1 ≥ 2 0 si 1 2 write σ = sgn(V V ). It may be mentioned that in the original work [75] only the 1 − 2 case V1 > V2 (i.e. σ = 1) was considered. In [78] we introduced σ to include the case

where V1 < V2.

36 Vg1

φ1 Gate 1

tox1 L Vs Vd n+ tsi n+ Source y Drain x

tox2 φ2 Gate 2 Vg2

Figure 3.1: Cross-section of the independent-gate asymmetric DG-FinFET. φ1 and φ2 are the workfunctions of gate-1 and gate-2, respectively.

3.2 Trigonometric Solution

To write the solution in a form given by Lu and Taur [75] in term of α and θ, we

deﬁne t √c θ = si (3.6) 4 φ · t and 1 √ c √ cx0 tan − − for σ = 1 − Ex0 2 φt α =  − · (3.7) 1 √ c √ cx0  π + tan − − for σ = 1  − Ex0 2 φt − · − then (3.5) becomes 

t 2 θx ψ(x)= V 2 φ ln si sin α + · . (3.8) c − · t 4 L θ t · di si From (3.8) the surface potential at both the interfaces can be expressed in terms of

α and θ by setting x = t /2 for ψ and x = t /2 for ψ which yields − si s1 si s2 t sin (α θ) ψ = V 2 φ ln si − (3.9) s1 c − · t 4 L θ · di and t sin (α + θ) ψ = V 2 φ ln si . (3.10) s2 c − · t 4 L θ · di

37 Diﬀerentiating (3.8) w.r.t x the electric ﬁeld distribution within the body is

dψ 4 φ θ 2 θx E(x)= = · t cot α + · . (3.11) − dx tsi tsi The electric ﬁeld inside the body at x = t /2 is − si

4 φtθ E1 = · cot (α θ) (3.12) tsi − and at x = tsi/2 is 4 φtθ E2 = · cot (α + θ) . (3.13) tsi The boundary condition that the normal component of the electric displacement vector is continuous at the gate-1 Si-SiO2 interfaces gives

C (V ψ )= E . (3.14) ox1 1 − s1 si 1

From (3.12) and (3.14) the surface potential there is then

ψ = V 4 φ r θ cot(α θ). (3.15) s1 1 − · t c1 −

Similarly, the boundary condition that the normal component of the electric displacement vector is continuous at gate-2 Si-SiO2 interfaces results in

C (V ψ )= E . (3.16) ox2 2 − s2 − si 2

From (3.13) and (3.16) the surface potential there is then

ψ = V + 4 φ r θ cot(α + θ) (3.17) s2 2 · t c2

Equating (3.9) and (3.15) we have

t V V = 2 φ ln si sin (α θ) + 4 φ r θ cot (α θ) . (3.18) 1 − c − · t 4 L θ − · t c1 − · di Similarly, equating (3.10) and (3.17) we obtain

t V V = 2 φ ln si sin (α + θ) 4 φ r θ cot (α + θ) (3.19) 2 − c − · t 4 L θ − · t c2 · di

38 where rc1 = Csi/Cox1 and rc2 = Csi/Cox2. Subtracting (3.18) from (3.19) yields

sin (α + θ) V V + 2 φ ln + 4 φ θ[r cot (α θ)+ r cot (α + θ)] = 0. (3.20) 2 − 1 · t sin (α θ) · t c1 − c2 − Any two of the above three equations form a set of coupled input voltage equations which needs to be solved for the unknown variables α and θ and hence the surface potentials ψs1 and ψs2. It may be noted that instead to two coupled IVEs it is possible to derive a single IVE in terms of ψs1 for V1 > V2 and ψs2 for V1 < V2 [77] (cf. Section 3.6). Nevertheless, the coupled IVEs derived in this section are used to derive the drain current and terminal charge model.

Applying Gauss’s law, the inversion (electron) charge density can be expressed as

Q = (E E )= 4 φ C θ [cot(α θ) cot(α + θ)] (3.21) n − si 1 − 2 − · t si − −

Note that the Qn is the total inversion charge density within the body. The variation of the electron concentration with x can be found from (2.3) and (3.8) as

4 C 2 2 θx n(x)= n · si θ2csc2 α + · (3.22) i C t f si which gives surface electron concentrations

4 C 2 n = n( t /2) = n · si θ2csc2 (α θ) (3.23) 1 si i C − f − and 2 4 Csi 2 2 n2 = n(tsi/2) = ni · θ csc (α + θ) . (3.24) Cf 3.3 Hyperbolic Solution

For this case deﬁning t √c θ = si (3.25) ∗ 4 φ · t and

1 √c σ√cx0 α = tanh− (3.26) ∗ σE − 2 φ x0 ! · t

39 (3.4) becomes

tsi 2 θ x ψ(x)= Vc 2 φt ln sinh α + σ · ∗ . (3.27) − · 4 Ldiθ ∗ tsi · ∗

Setting x = tsi/2 yields the surface potential at gate 1

tsi ψs1 = Vc 2 φt ln sinh (α σθ ) (3.28) − · 4 Ldiθ ∗ − ∗ · ∗ and setting x = t /2 yields the surface potential at gate 2 − si

tsi ψs2 = Vc 2 φt ln sinh (α + σθ ) . (3.29) − · 4 Ldiθ ∗ ∗ · ∗ Diﬀerentiating (3.27) w.r.t. x we get the electric ﬁeld distribution

dψ 4 φtθ 2θ x E(x)= = σ · ∗ coth α + σ ∗ . (3.30) − dx tsi ∗ tsi The electric ﬁeld inside the semiconductor at x = t /2 is − si

4 φtθ E1 = σ · ∗ coth (α σθ ) (3.31) tsi ∗ − ∗

and at x = tsi/2 is 4 φtθ E2 = σ · ∗ coth (α + σθ ) . (3.32) tsi ∗ ∗ From (3.31) and the boundary condition (3.14) the surface potential at the gate-1 is

ψs1 = V1 4 σφtrc1θ coth(α σθ ). (3.33) − · ∗ ∗ − ∗

Similarly, from (3.32) and the boundary condition (3.16) the surface potential at

gate-2 is

ψs2 = V2 + 4 σφtrc2θ coth(α + σθ ). (3.34) · ∗ ∗ ∗ Equating (3.28) and (3.33) we have

tsi V1 Vc = 2 φt ln sinh (α σθ ) + 4 σφtθ rc1 coth (α σθ ) (3.35) − − · 4 Ldiθ ∗ − ∗ · ∗ ∗ − ∗ · ∗ Similarly, equating (3.29) and (3.34) yields

tsi V2 Vc = 2 φt ln sinh (α + σθ ) 4 σφtθ rc2 coth (α + σθ ) (3.36) − − · 4 Ldiθ ∗ ∗ − · ∗ ∗ ∗ · ∗ 40 Subtracting (3.35) from (3.36) we have

sinh (α + σθ ) V V + 2 φ ln ∗ ∗ 2 − 1 · t sinh (α σθ ) ∗ − ∗ + 4 σφtθ [rc1 coth (α σθ )+ rc2 coth (α + σθ )] = 0 (3.37) · ∗ ∗ − ∗ ∗ ∗

Any two of (3.35), (3.36), and (3.37) together form a set of IVEs which needs to

be solved for unknown variables α and θ and hence surface potentials for the ∗ ∗ hyperbolic case. In this case the inversion charge density becomes

Qn = si (E1 E2)= 4 σφtCsiθ [coth(α σθ ) coth(α + σθ )] (3.38) − − − · ∗ ∗ − ∗ − ∗ ∗ and the variation of the electron concentration with x can be found from (2.3) and

(3.27) as 4 C 2 2 σθx n(x)= n · si θ2csc2 α + · (3.39) i C t f si which gives surface electron concentrations

2 4 Csi 2 2 n1 = n( tsi/2) = ni · θ csch (α σθ) (3.40) − Cf − and 4 C 2 n = n(t /2) = n · si θ2csch2 (α + σθ) . (3.41) 2 si i C f 3.4 Solution Space

The boundary between the hyperbolic and trigonometric solution is determined by a

transcendental equation derived in [75] which deﬁnes the critical value Vcr for given gate bias and device parameters where the two diﬀerent solutions merge. To obtain

an expression for the critical value Vcr one can introduce the variable s representing the limiting value [75] α α = ∗ (3.42) θ θ ∗ on the line Γ1 separating the trigonometric region from the hyperbolic region with σ = 1 shown in Fig. 3.2. This line corresponds to α, θ, α ,θ 0. This leads to ∗ ∗ → 4 L 4 φ r V = V 2 φ ln · di · t c1 (3.43) cr 1 − · t t (s 1) − s 1 si − − 41 2

Γ2 1.5

hyperbolic trigonometric σ = −1 [V] 1 2 V Γ1

0.5 hyperbolic σ = 1

0 0 0.5 1 1.5 2 V1 [V]

Figure 3.2: Regions of operation on the V1-V2 plane for Vc = 0.5 V, tsi = 20 nm, tox1 = 2 nm and tox2 = 40 nm. where s is determined numerically from the transcendental equation [75] V V s + 1 r r 2 − 1 + ln + 2 c1 + c2 = 0. (3.44) 2 φ s 1 · s 1 s + 1 · t − −

These equations determine the lower partition line Γ1 in Fig. 3.2 on which

V1 > V2. The equation of the upper partition line Γ2 on which V1 < V2 can be obtained by interchanging V V and r r . 1 ↔ 2 c1 ↔ c2 4 L 4 φ r V = V 2 φ ln · di · t c2 (3.45) cr 2 − · t t (s 1) − s 1 si − − where s can be found from the solution of equation V V s + 1 r r 1 − 2 + ln + 2 c1 + c2 = 0. (3.46) 2 φ s 1 · s + 1 s 1 · t − − For t = t the line Γ has a diﬀerent shape than the lower partition line Γ . ox1 6 ox2 2 1 Alternatively, equations (3.45) and (3.46) can be also obtained from (3.8), (3.27) and the usual boundary conditions at x = t /2 [75] by redeﬁning ± si π α α s = − = ∗ (3.47) θ θ ∗ 42 where the ratio is evaluated on the second partition line Γ2. As illustrated in Fig. 3.3 and Fig. 3.4, the boundary between the three regions shifts with the increase of the

imref splitting. Since the line V = V (i.e. V ∆φ = V ∆φ ) always falls 1 2 g1 − 1 g2 − 2 within trigonometric region (cf. Fig. 3.2) the trigonometric solution always applies

in this case even if t = t . This includes the case of the common-gate symmetric ox1 6 ox2 DG-FinFET [75]. Mathematically, this property of the partition line is represented

by the condition V = for V = V . cr ∞ 1 2

For a device with tox1 = tox2 and with independent gates the partition lines are also symmetric (cf. Fig. 3.3). This is required by the intrinsic symmetry of the

device and without any computations conﬁrms that there are three (trigonometric,

hyperbolic with σ = 1, and hyperbolic with σ = 1) rather than two regions on the − V1-V2 plane.

In [75] the regions of operation are found by ﬁrst solving (3.44) numerically

for s and then substituting s in (3.43) to get V . For V V equation (3.44) cr 1 ≈ 2 and (3.46) are poorly conditioned and are diﬃcult to solve numerically. Since it is

desirable that compact models of independent-gate asymmetric DG-FinFETs should

include the common-gate symmetric DG-FinFET as a special case, this represents a

potential problem for model development and convergence of circuit simulations.

43 2

1.5 1.0

[V] 1 0.5 2 V

0.5 Vc = 0 V

0 0 0.5 1 1.5 2 V1 [V]

Figure 3.3: Partition lines on the V1-V2 plane with Vc as parameter obtained from numerical solution (circles) and analytical solution (lines); tsi = 20 nm, tox1 = tox2 = 2 nm.

1.5 1.0

[V] 1 2 V 0.5

0.5

Vc = 0 V

0 0 0.5 1 1.5 2 V1 [V]

Figure 3.4: Partition lines on V1-V2 plane with Vc as parameter obtained from numerical solution (circles) and analytical solution (lines); tsi = 20 nm, tox1 = 2 nm , tox2 = 40 nm.

44 2

1.5

1.0 1 [V] 2 V 0.5 0.5

0 Vc = 0 V

−0.5 0 0.5 1 1.5 2 V1 [V]

Figure 3.5: Partition lines on V1-V2 plane with Vc as parameter obtained from numerical solution (circles) and analytical solution (lines); tsi = 10 nm, tox1 = 2 nm , tox2 = 40 nm.

45 3.5 Analytical Expression for the Partition Lines

With the physical picture and the complete partition diagrams in place it remains

to simplify the computational procedure. In this study we switch from computing

the critical value Vcr of the imref splitting to computing the critical values V1cr and

V2cr of V1 and V2, respectively [78]. This leads to the expressions for V1cr and V2cr in terms of the Lambert W function [79] which are mathematically equivalent to (3.43),

(3.44) and (3.45), (3.46) but are much better conditioned and exhibit no singular

behavior. When V1 > V2 we ﬁnd the critical voltage V2cr at gate 2 for a given value of

Vc and V1. Comparison of V2 with V2cr establishes the region of operation. Similarly,

for V1 < V2 we ﬁnd the critical voltage V1cr at gate 1 for a given value of Vc and V2.

Now the region of operation is established by comparing V1 with V1cr. From (3.43)

u ue = v1; V1 > V2 (3.48)

where 2 r u = · c1 ; V > V (3.49) s 1 1 2 − and r t V V v = c1 si exp 1 − c ; V > V (3.50) 1 2 L 2 φ 1 2 · di · t Then u = W (v1), 2 rc1 s =1+ · ; V1 > V2 (3.51) W (v1) and from (3.44)

s + 1 r r V = V 2 φ ln 4 φ c1 + c2 ; V > V (3.52) 2cr 1 − · t s 1 − · t s 1 s + 1 1 2 − − Similarly, from (3.46)

s + 1 r r V = V 2 φ ln 4 φ c1 + c2 ; V < V (3.53) 1cr 2 − · t s 1 − · t s + 1 s 1 1 2 − − where 2 rc2 s =1+ · ; V1 < V2 (3.54) W (v2)

46 and r t V V v = c2 si exp 2 − c ; V < V (3.55) 2 2 L 2 φ 1 2 · di · t The advantage of using the Lambert W function is that its deﬁning transcendental

equation (3.48) is well-conditioned and eﬃcient procedures for numerical as well

as analytical evaluation are readily available [79, 80]. For example, the condition

limV1 V2 Vcr = established above from the physical consideration corresponds → ∞

to limV1 V2 s = . Since W (v) is analytic at v = 0 numerical evaluation of the → ∞ case V V represents no particular diﬃculty. Comparison of the two methods of 1 ≈ 2 evaluating the partition lines on the V1-V2 plane is shown in Fig. 3.3 for tox1 = tox2 and in Fig. 3.4 for t = t respectively. As expected a perfect agreement is ox1 6 ox2 obtained between the numerical solution of (3.43)-(3.46) and the explicit solution

given by (3.52) and (3.53). To show the dependence of the boundary lines on the

silicon ﬁlm thickness, we plot them in Fig. 3.5 for tsi = 10 nm with the same gate oxide thickness as in Fig. 3.4.

3.6 A New Solution Technique for the IVEs

Originally, for both the trigonometric and hyperbolic cases, the IVEs were formulated

as two coupled equations with two unknown variables as shown earlier [75]. A single

IVE that is solved with respect to only one of the surface potentials was derived in

[77]. Depending on the device parameters and gate voltages Vg1 and Vg2 this IVE can take four diﬀerent forms: (i) V > V , hyperbolic, (ii) V V , trigonometric, (iii) 1 2 1 ≥ 2 V1 < V2, trigonometric, and (iv) V1 < V2, hyperbolic. The appropriate functional form of the IVE can be selected analytically as shown in Fig. 3.6, where explicit

equations for the boundaries Γ1 and Γ2 are described in the previous section [78]

and Γ3 corresponds to V1 = V2. However, the resulting IVE in [77] was solved using computationally expensive numerical optimization techniques. A better conditioned

single IVE is obtained here by changing the variable in the IVE of [77] from ψs1 to

2 Cox1 (V1 ψs1) Vc ψs1 ξ1 = − exp − , (3.56) Cf φt φt

47 2 Γ2 Γ3 1.5 (iv) (iii)

[V] 1 (ii) 2 V Γ1 0.5 (i) 0 0 0.5 1 1.5 2 V1 [V] Figure 3.6: Regions of operation on the V V plane for V = 0.5 V, t = 10 nm, 1 − 2 c si tox1 = 2 nm and tox2 = 20 nm.

where Cf = si/Ldi. For region (i) in Fig. 3.6 this gives an implicit ξ1(V1, V2, Vc) dependence [81]

ξ 1 sinh(ϕ ) (V V ) W b ξ 1+ r coth(ϕ ) 1 − + ln 1 + 2 − 1 = 0 (3.57) 1 1 1 √ " s ξ1 # ξ1 1 2 φt p − · where

ξ1 1 W b1√ξ1 1 ϕ1 = − + sinh− ξ1 1, (3.58) s ξ1 · rc1 − p C V V b = f exp 1 − c , (3.59) 1 2 C 2 φ · ox1 · t r = Cox1/Cox2, rcj = Csi/Coxj, and W is the Lambert-W function. The IVE for the trigonometric case of region (ii) in Fig. 3.6 becomes

1 ξ sin(ϕ ) V V W b ξ 1+ r cot(ϕ ) − 1 + ln 1 + 2 − 1 = 0, (3.60) 1 1 1 √ " s ξ1 # 1 ξ1 2 φt p − · where now

1 ξ1 W b1√ξ1 1 ϕ1 = − + sin− 1 ξ1. (3.61) s ξ1 · rc1 − p IVEs for regions (iii) and (iv) have a similar form. For the hyperbolic case it can be seen that ξ 1 and for the trigonometric case 0 <ξ 1. While the IVEs 1 ≥ 1 ≤

48 (3.57) and (3.60) are mathematically equivalent to those in [77], the well-deﬁned range of ξ1 allows the Newton-Raphson method to be used directly for solution, without any need for preliminary numerical optimization.

However, during numerical iteration of the trigonometric IVE for some bias

conditions ξ1 can cause ϕ1 = π which creates a problem when evaluating cot ϕ1 in

(3.60). We overcome this problem by selecting the initial range of ξ1 to be between

ξπ and 1 where ξπ is found from (3.61) by setting ϕ1(ξπ) = π. This also avoids encountering closely located unphysical multiple roots of the IVE between 0 and ξπ produced by oscillations of cot ϕ1 in (3.60). Note that (3.57) is equivalent to (3.60) for ξ 1 i.e. at the boundary between the trigonometric and the hyperbolic IVE 1 → forms [78].

The surface potential ψs1 for region (i) is obtained from (3.56) as

ψ = V 2 φ W b ξ (3.62) s1 1 − · t 1 1 p and the surface potential ψs2 is given by [77]

sinh(ϕ ) ψ = ψ 2 φ ln 1 . (3.63) s2 s1 − · t √ξ 1 1 − Traditionally, independent-gate asymmetric DG-FinFET models are formulated in

terms of the integration constants α and θ [75, 78] which are also used in expressions

for the drain current and terminal charges. They are related to ξ1 for region (i) as follows 1 ξ1 1 θ = − W b1 ξ1 (3.64) 2 rc1 s ξ1 · · p and

1 α = θ + sinh− ξ 1. (3.65) 1 − p 1 1 For region (ii) we replace ξ 1 by 1 ξ and sinh− √ξ 1 by sin √1 ξ in 1 − − 1 1 − − − 1 (3.63)-(3.65).

49 Chapter 4

CURRENT and CHARGE MODELS for the COMMON-GATE SYMMETRIC

DG-FinFET 4.1 Introduction

An exact core model of undoped multi-gate MOSFETs has been developed in [60, 62,

75, 82] for the common-gate symmetric DG-FinFET and in [83, 84] for the SGFET.

In both cases one obtains closed-form equations for the drain current Id, but the situation with the terminal charges is diﬀerent. For the common-gate symmetric

DG-FinFET, the charges are obtained as quadratures that require numerical eval-

uation [75] while exact closed-form expressions for the charges in the SGFET case

[84] are somewhat more complex than is customary in compact models. The second

problem is that exact core SGFET and common-gate symmetric DG-FinFET mod-

els are signiﬁcantly diﬀerent, which is disadvantageous for the purpose of realistic

compact model development that may require simultaneous inclusion of both models

to describe complex geometries and corner eﬀects [85]. The ﬁnal problem is that the

complexity of the exact multi-gate MOSFET core models is not conducive to the

inclusion of small-geometry eﬀects (e.g. velocity saturation) and does not allow one

to directly use the experience (and code) gained in the development of advanced

bulk and SOI MOSFET models.

Signiﬁcant progress towards the resolution of the three problems outlined

above has been made in [56, 57] and [82]. In [56, 57] the current equation of the

exact core model of [60, 75] has been reformulated and then simpliﬁed so that the

resulting expressions for the drain current and charges take a form identical to that

used in PSP [45]. This allowed incorporation of small-geometry eﬀects leading to

a relatively complete model of symmetric undoped DG-FinFETs that was found

to be in good agreement with both TCAD simulations and experimental data. The

price for the simplicity and the convenience of this approach is a signiﬁcant diﬀerence

(about 20% for current and 4% for transcapacitances) between the simpliﬁed [56, 57]

50 and the exact core models [60, 75]. This difference was absorbed by the parameters included in the model. A different approach to simplifying the exact core model has been introduced in [82]. Starting with the simplified input voltage equation simple analytical expressions were obtained for the drain current and terminal charges. One important accomplishment of the approximate theory developed in [82] is that with a proper mapping, the same equations describe symmetric undoped common-gate symmetric DG-FinFETs and SGFETs. The accuracy of the approximations made in

[82] is exactly the same as in [56, 57].

Another approximate core model of symmetric DG-FinFETs has been developed in [86]. Similarly to [82] this was accomplished by simplifying the input voltage equation and as in [57] the result was brought in a form compatible with one of the advanced bulk MOSFET models (EKV) simplifying the inclusion of small-geometry eﬀects [87].

In this work we continue the effort to make the DG-FinFET model as similar as possible to the PSP bulk MOSFET model [45]. For this purpose we first show that despite the different starting points and seemingly different formulation in [57] and [82] both approximations are identical. The origin of error in the charge-sheet approximation is discussed. We then significantly improve the accuracy of this approach while still keeping the equations of the approximate core model in a form nearly identical to that of the PSP model as suggested in [57]. This is accomplished by extending the symmetric linearization technique to not assume the charge-sheet approximation that is used in the bulk MOSFET case [88, 89].

4.2 Exact Drain Current

We start with the drift and diﬀusion formulation of the drain current:

tsi ∂ψ ∂n I = qµh n φ dx. (4.1) d f ∂y − t ∂y Z0

51 where µ is the electron mobility and hf is the ﬁn height. Using identity

∂ψ ∂n ∂V n φ = n c (4.2) ∂y − t ∂y ∂y and the fact that in a device with the geometry shown in Fig. 2.3a, Vc = Vc(y) (4.1) becomes dV I = 2 µh q c (4.3) d · f n dy where tsi/2

qn = q n(x,y) dx (4.4) Z0 is the absolute value of electron charge density per unit area per channel expressed in terms of ψs and θ in (2.62) and (2.63), respectively. Integrating (4.4) from source to drain yields L h I = 2 µ f q dV . (4.5) d · L n c Z0

Changing the variable of integration in (4.5) from Vc to θ gives [60]

θd h dV I = 2 µ f q c dθ (4.6) d · L n dθ θZs where θs and θd are the values of θ at source and drain end, respectively. From (2.61)

dVc 1 2 rcθ = 2 φt + (1 + 2 rc) tan θ + · 2 . (4.7) dθ − · θ · cos θ Substituting (2.63) and (4.7) in (4.6) the drain current becomes [60]

2 θs hf 2 2 θ Id = 16 µ Csiφt rqi + qi (4.8) · L − 2 ! θd

where qi = θ tan θ is the normalized inversion charge density. The values of θs and θd

are determined from (2.65) and (2.59) by setting Vc = Vs and Vc = Vd, respectively.

4.3 Charge-Sheet Approximation

Applying Brews charge-sheet approximation [90] to the DG-FinFET [67, 57] we get

dψ dq I = 2 µh q s φ n . (4.9) d f n dy t dy · − 52 Substituting for qn from (2.62) in (4.9) yields

dψ I = 2 µh C [(V ∆φ ψ )+ φ ] s . (4.10) d · f ox gs − − s t dy

Integrating (4.10) from the source end to drain end of the channel the drain current becomes h I = 2 µ f C [(V ∆φ ψ )+ φ ]∆ψ (4.11) d · L ox gs − − sm t where

∆ψ = ψ ψ (4.12) sd − ss is the total variation of surface potential along the channel,

1 ψ = (ψ + ψ ) (4.13) sm 2 ss sd

is the surface potential midpoint and ψss and ψsd are the surface potential at the source end and the drain end of the channel, respectively. Fig. 4.1 shows the per-

centage error introduced by the charge sheet charge sheet approximation (4.11) when

compared to the exact equation (4.8). In [82] an equivalent form of (4.11) is derived

d −5

−10

−15

t =10 nm Si

Relative error (%) for I −20 20 nm 30 nm −25 0 0.5 1 1.5 2 V −∆φ [V] g

Figure 4.1: Relative error for drain current Id using expression (4.11); tox = 1.5 nm, T = 300 K, Vds = 1 V.

53 by approximating the IVE as

ln q V ∆φ V 4 L i + 2 r q g − − c ln · di (4.14) 2 · c i ≈ 2 φ − t · t si to give h q qis I = 16 µ f C φ2 i + r q2 (4.15) d · L si t 2 c i qid

Using (2.62) and (2.63) in (4.15) it can be shown that although (4.11) and (4.15) originate from seemingly diﬀerent approximations, they are equal [67]. These approximation were used in [82] and [57] to derive closed form expression for terminal charges which had error of 4% compared to exact results. In Section 4.5 we propose a more accurate terminal charge model based on the symmetric linearization method.

To gain further insight into the origin of the signiﬁcant error for Id associated with expressions (4.11) or (4.15) we reformulate the exact expression for the drain

current [60]. This reformulation is later used in extending the symmetric linearization

method. Following [57] (4.1) can be written as

dψ dq I = 2 µh q˜ s φ n (4.16) d f n dy t dy · − where tsi/2 ∂ψ q n ∂y dx q˜ = 0 (4.17) n R dψs dy

As shown in Appendix D q˜n can be written as [57, 67]

g q˜ = 1+ q (4.18) n 4 r n · c where sin(2 θ) 2 θ cos(2 θ) g = · − · · (4.19) θ tan θ[2 θ + sin(2 θ)] · · Physically, the difference between qn and qñ accounts for the fact that, generally speaking, current flow in DG-FinFETs is not confined to a narrow surface channel and approximation (4.9) is not always accurate. In Fig 4.2 we plot g as a function of θ where θ varies from 0 (weak inversion) to π/2 (strong inversion). It can be seen that

54 0.7

0.6

0.5

0.4 ) θ

g( 0.3

0.2

0.1

0.0 0.0 0.2 0.4 0.6 0.8 1.0 2 ·θ/π Figure 4.2: g(θ) versus θ. in strong inversion g approaches zero and the second term in parentheses in (4.18) can be neglected which results in high accuracy of the charge sheet approximation.

In the weak inversion even with the highest value of g neglecting it does not result in significant error in drain current as the diffusion term in (4.9) is dominant. However, in the moderate inversion g has a significant value and since both drift and diffusion terms in (4.9) contribute to current, neglecting g introduces significant error in drain current [57]. Integrating (4.16) from the source end to the drain end of the channel yields ψsd h I = 2 µ f q˜ dψ + φ (q q ) . (4.20) d · L  n s t ns − nd  ψZ  ss    Reformulating (4.20)

ψsd h I = 2 µ f k q dψ + φ (q q ) (4.21) d · L  n s t ns − nd  ψZ  ss   

55 where ψsd q˜ndψs ψss k = R (4.22) ψsd qndψs ψss R or g k =1+ 0 (4.23) 4 r · c and ψsd gqndψs ψss g0 = R (4.24) ψsd qndψs ψss R is a bias-dependent but position-independent variable. From (2.62) we have dqn/dψs = C and (4.21) becomes − ox h q qis I = 16 µ f C φ2 kr q2 + i (4.25) d · L si t c i 2 qid

The value of k can be obtained by direct integration in (4.22) or more conveniently

by comparison with the exact result (4.8). Comparison of (4.8) with (4.25) yields

θs qis 2 2 qi 2 θ krcqi + = rcqi + qi (4.26) 2 qid − 2 θd

or 2 θ2 θ2 g = 1 s − d (4.27) 0 q + q − q q is id is − id ! With g0 given by (4.27) and k by (4.23) expression (4.25) is exact and is just one of many possible reformulations of (4.8). Clearly the approximations made in [57] and

[82] are equivalent to setting k = 1 i.e. g0 = 0 instead of using the exact expression (4.23). For further reference we note that (4.25) can be also written as

h I = 2 µ f C (kq + φ )∆ψ (4.28) d · L ox nm t or in PSP form h I = 2 µC f [q + φ + φ (1 g )]∆ψ, (4.29) d · ox L nm t t − 1

56 where θ2 θ2 g = s − d , (4.30) 1 q q is − id and

qnm = qn (4.31) |ψs=ψsm denotes the voltage drop across gate oxide (in the inversion condition) at the surface

potential midpoint. The term φ (1 g ) in (4.29) may be called a non-charge- t − 1 sheet term and if neglected it results in the drain current under the charge-sheet

approximation.

4.4 Symmetric Linearization Method

Introduction of a position-independent k is suﬃcient to compute Id but not the position dependence of the surface potential required to compute the terminal charges.

The latter involves evaluation of the derivative dy/dψs using (4.16) which can be written as [57] dψ I = 2 µ h (˜q + C φ ) s (4.32) d · f n ox t dy where we used (2.62). In order to obtain compact closed form expressions for ψs(y) and terminal charges some approximation is required. The simplest possible approximation is q˜n = qn [57] which leads to the approximate expressions for QG, QS, and

QD developed in [57, 82]. A more accurate approximation is

q˜ = C (ν α u) (4.33) n ox − l where

u = ψ ψ (4.34) s − sm and variables ν and αl are position independent (they, of course, are functions of the terminal voltages). This approximation represents linearization of q˜n as a function of surface potential. The value of the coeﬃcients ν and αl can be selected in more than one way. A natural choice is

q˜ ν = nm (4.35) Cox

57 and 1 d˜q α = n (4.36) l −C dψ ox s ψs=ψsm

where qñm denotes the value of qñ at the point where ψs = ψsm. Since, however, a simple expression for qñm is unavailable, we consider a different choice. From (4.32) and (4.33) we find du I = 2 µ h C (ν + φ α u) (4.37) d · f ox t − l dy and after integration along the channel

h I = 2 µ f C (ν + φ )∆ψ. (4.38) d · L ox t

By comparison with (4.28) it follows that by selecting

ν = k qnm (4.39) we assure that expression (4.38) is exact. The diﬀerence between two choices of

ν is further discussed in Appendix E where we compare the commonality and dif- ferences for the symmetric linearization method as applied to bulk MOSFETs and

DG-FinFETs.

From (4.36) the expression for linearization coeﬃcient αl becomes

1 d g α = q 1+ (4.40) l −C dψ n 4r ox s c ψs=ψsm

which is approximated as [67, 63]

3 (3 + 2q ) α 1+ · im (4.41) l ≈ 8 r (2 + q )3 · c im where 1 qim = qi = (qis + qid) (4.42) |ψs=ψsm 2 The derivation of (4.41) is presented in Appendix D.

58 4.5 Terminal Charges

With ν and αl established, the terminal charges are obtained as follows. From (4.37) and (4.38) dy L(H u) = − (4.43) du H∆ψ where ν + φ kq + φ H = t = nm t (4.44) αl αl After integration of (4.43)

Lu u y = y + 1 (4.45) m ∆ψ − 2 H · where L ∆ψ y = 1+ (4.46) m 2 4 H · gives the position of the “surface potential midpoint”, i.e. the point where ψs = ψsm.

An explicit form of the ψs(y) dependence follows (4.45):

2 ∆ψ ψs(y)= ψsm + H 1 1 · (y ym) (4.47) " − s − HL − # Expressions (4.43)-(4.46) are exactly the same as for bulk MOSFETs [44, 45, 88, 89]

except for the diﬀerent value of H. The high accuracy of the explicit expression (4.47)

for the position dependence of the surface potential is illustrated in Fig. 4.3 where

it is compared with the exact result for ψs(y) that can be presented in parametric form [60]

ψ (θ)= V ∆φ 4 r φ θ tan θ (4.48) s g − − · c t and y(θ) F (θ ) F (θ) = s − (4.49) L F (θ ) F (θ ) s − d where θ2 F (θ)= θ tan θ + r θ2 tan2 θ. (4.50) − 2 c

59 3 Exact Symmetric linearization 3 2.5

2 2 [V] s ψ 1.5

V =1 V 1 gs

0.5 0 0.2 0.4 0.6 0.8 1 y/L (from source to drain)

Figure 4.3: Position dependence of surface potential in DG-FinFET; tox = 1.5 nm, tsi = 20 nm, and Vds = 2 V.

Now the gate charge for bulk DG-FinFETs becomes

L ∆ψ/2 dy Q = h q dy = 2 h C (V u) du (4.51) G f g · f ox oxm − du Z0 ∆Zψ/2 − which with reference to (4.43) leads to a closed form expression

∆ψ2 Q = 2 C h L V + (4.52) G · ox f oxm 12 H · ! where

V = (V ∆φ ψ ) (4.53) oxm g − − sm is the potential across gate oxide at surface potential midpoint. The total drain charge using the Ward-Dutton partition scheme [91] is given by

L ∆ψ/2 y y dy Q = 2 h q dy = 2 C h (q u) du. (4.54) D − · f n L − · ox f nm − L du Z0 ∆Zψ/2 − Substituting (4.43), (4.45) in (4.54) and integrating yields

q ∆ψ ∆ψ ∆ψ2 Q = 2 C h L nm 1 . (4.55) D − · ox f 2 − 12 − 2 H − 20 H2 " · · !# 60 Similarly, the total source charge is

q ∆ψ ∆ψ ∆ψ2 Q = 2 C h L nm + 1+ . (4.56) S − · ox f 2 12 2 H − 20 H2 " · · !# The bulk FinFET body charge follows from the neutrality condition Q = (Q + B − G QD+QS). For SOI FinFETs expressions for QS and QD remain the same but in (4.52) we change Voxm to qnm to assure the QG (and hence Cgg, Cbg) becomes negligible in accumulation (ψss < 5φt). A subtle point here which is not needed to be included in the compact model formulation of SOI FinFETs is that in the steady state, QG can become appreciable due to the leakage of minority carriers from the n+ contacts provided that the device is not switched for prolonged periods of time. But this build-up of QG is extremely slow and hence has no consequences for small-signal behavior even at low frequency [cf. TCAD simulations in Fig. 2.2a].

Three dimensional (3D) TCAD simulations are performed for both bulk and

SOI DG-FinFETs. Both the electron and hole continuity equations are included in the simulations. The device channel length is kept suﬃciently large to reduce small geometry and fringe capacitances eﬀects. The simulated device structure parameters are L = 1 µm, hf = 0.2 µm, tox = 2 nm, tsi = 10 nm and ∆φ = 0 V. The carrier mobility is kept constant and equal to the mobility in intrinsic silicon.

While the implementation of modern compact transistor models in SPICE- like circuit simulators is charge-based, in order to preserve the charge conservation

[92], it is often convenient to perform model veriﬁcation in terms of capacitances.

∂Qm Cnm = (2 δnm 1) (4.57) · − ∂Vn where m,n label the terminals of the device and δnm is Kronecker’s delta. Indeed, any error in the expressions for the terminal charges Qm is ampliﬁed while evaluating the derivatives ∂Qm/∂Vn. For this reason we present a comparison of the charge model with numerically computed results both in terms of charges and transcapacitances.

61 Figs. 4.4a and 4.4b compare the capacitances obtained from the 3D TCAD simulations and the compact model for bulk and SOI FinFETs, respectively. The model accurately reproduces the transcapacitance behavior in all regions of operation including accumulation.

Expressions (4.38), (4.52), (4.55) and (4.56) represent a form of the symmetric linearization method applied to common-gate symmetric DG-FinFETs. Unlike the simpler formulation in [57], the result is exact for the drain current and as shown in Fig. 4.5 significantly reduces the error for the terminal charges. Similarly, it provides a better accuracy for the transcapacitances (cf. Fig. 4.6a and 4.6b). An important feature of the new approximations for QG and QD is that they are extremely simple, have the same form as in SP [44] and PSP [45] and differ only by using different expression for H. This means that incorporation of small geometry effects can proceed in the same manner as in [56, 57] which already had been shown sufficiently accurate in terms of both TCAD simulations and experimental data. The expressions for QG and QD given in [57, 82] can be obtained from (4.52) and (4.55) by setting qñ = qn. Indeed, this implies k = 1, ν = Voxm and αl = 1. Then by (4.44)

H = Voxm + φt and (4.52) and (4.55) revert to the charge sheet version of terminal charge expressions found in [57, 82].

62 C 0.8 gg

0.6 Csg 0.4

0.2 Cdg C

Normalized transcapacitances bg 0 −1 −0.5 0 0.5 1 1.5 2 Vgs [V] (a)

C 0.8 gg

0.6

Csg 0.4

0.2 Cdg C

Normalized transcapacitances bg 0 −1 −0.5 0 0.5 1 1.5 2 Vgs [V] (b) Figure 4.4: Normalized transcapacitances of (a) bulk FinFET and (b) SOI FinFET versus gate voltage for Vds = 1V. Symbols represents TCAD simulations results and the lines corresponds to a compact model.

63 1.5 Q G Q 1 D Q S 0.5

−0.5

−1 Relative error (%) for charges

−1.5 0 0.5 1 1.5 2 V −∆φ [V] g Figure 4.5: Relative error for the terminal charges, using symmetric linearization method for DG-FinFET; tsi = 20 nm, tox = 1.5 nm, T = 300 K, Vds = 1 V.

64 1 Circles: exact Lines: symmetric linearization method 0.8 C gg 0.6

C sg 0.4 C dg 0.2 Normalized transcapacitances

0 0 0.5 1 1.5 2 V −∆φ [V] g

(a)

1.5 C gg C 1 dg C sg 0.5

−0.5

−1

−1.5 Relative error (%) for transcapacitances 0 0.5 1 1.5 2 V −∆φ [V] g (b) Figure 4.6: Plots of (a) transcapacitance and (b) relative error for the transcapacitances, using symmetric linearization method for DG-FinFET; tsi = 20 nm, tox = 1.5 nm, T = 300 K, Vds = 1 V.

65 4.6 Symmetric Linearization Method for SGFET

With reference to Fig. 4.7 the drain current for SGFET

Id = JdA (4.58) Z where the integral is taken across the area in the direction perpendicular to the current ﬂow (i.e. dA = 2 πρdρ). The current density ·

Vg Gate φ

tox ρ

Vs Vd n+ 2R n+ Source y Drain L

tox

Gate Vg

Figure 4.7: Cross-section of the SGFET.

∂ψ ∂n J = qµ n φt (4.59) ∂y − ∂y Hence dψs dqn Id = µ q˜n φt (4.60) dy − dy where

qn = q ndA (4.61) Z is the absolute value of the inversion charge per unit channel length and

q ∂ψ q˜n = n dA. (4.62) dψs ∂y dy Z

Just as for the DG-FinFET the diﬀerence between q˜n and qn accounts for the fact that, generally speaking, current density is not concentrated near the Si-SiO2 inter- face.

66 Integrating along the y direction yields

ψsd µ I = k q dψ + φ (q q ) (4.63) d L  n s t gs − gd  ψZ  ss    where formally k is given by the same expression (4.23) as for DG-FinFET.

For SGFETs (cf. Fig. 4.7)

dqn = 2 πRCox (4.64) dψs − · where C = ox . (4.65) ox tox R ln 1+ R It follows that 2 qns µ kqn Id = + φtqn . (4.66) L 4 πRCox ! · qnd

For SGFETs it is convenient to deﬁne the variable θ as [84]

R 2 ψ V θ = 1 exp 0 − c (4.67) − 4 L φ · di t

where ψ0 denotes the potential at the center of the device. Then

q = 8 πφ q (4.68) n · t si i

where the normalized gate charge per unit length is

1 θ q = − . (4.69) i θ

From (4.66) 2 q 8 πµsiφt 2 is Id = · ksqi + qi (4.70) L qid where 2 t s = si ln 1+ ox . (4.71) R ox Comparing this with exact result [83, 84]

8 πµ φ2 s 2 (1 s) θs I = · si t + · − + ln θ (4.72) d L θ2 θ θd

67 we ﬁnd 1 1 θs θ θ + ln θ k =1+ s − d d . (4.73) 1 1 2 2 s 2 2 + θs θ θd θs − d − With this selection of k, (4.70) represents a reformulation of (4.72) conducive to the

development of the symmetric linearization method. The approximate expression

in [82] follows from (4.70) by setting k = 1, i.e. q˜n = qn just as in the case of DG-FinFET considered in Section 4.3.

To introduce symmetric linearization and account for q˜ = q we note that n 6 n dq dψ n = 2 πRC s (4.74) dy − · ox dy and set dψ I = µ (˜q + 2 πRC φ ) s . (4.75) d n · ox t dy

Linearization of q˜n as a function of ψs yields

q˜ = 2 πRC (ν α u). (4.76) n · ox − l where u is deﬁned as in (4.34) and the variables ν, αl are yet to be determined. From (4.75) and (4.76) du I = 2 πµRC (ν + φ α u) . (4.77) d · ox t − l dy In particular, 2 πR I = µ · C (ν + φ )∆ψ. (4.78) d L ox t According to (4.72) in order for this expression to be exact

s 2 (1 s) θs 2 (ν + φ )∆ψ = 4 sφ2 + · − + ln θ . (4.79) · t · t θ2 θ θd

This yields ν. The coeﬃcient αl is selected as

q˜is q˜id αl = − k (4.80) Cox∆ψ ≈ where the approximation is based on q˜ kq and q˜ kq . The ﬁnal justiﬁcation is ≈ is id ≈ id of the selected approximations for ν and αl for both DG-FinFET and SGFET is by comparison with the exact expressions for terminal charges and transcapacitances.

68 From (4.77), (4.78)

dy 2 πRC α (H u) = · ox l − (4.81) du Id

and 2 πR I = · µC α H∆ψ (4.82) d L ox l where ν + φ H = t . (4.83) αl This yields (4.45) and after integration one concludes that (4.52), (4.54), and (4.55)

apply also to SGFET, after changing hf into πR. The only diﬀerence with DG- FinFET or bulk MOSFET is in the expressions for ν and H. Comparison with the exact results for SGFETs is shown in Fig. 4.8 for charges and in Fig. 4.9 for transcapacitances. In all cases the accuracy is better than 2% while expression

(4.78) for the drain current is exact.

Q G 2 Q D Q S 1

Relative error (%) for charges −1

0.5 1 1.5 2 V − ∆φ [V] gs Figure 4.8: Relative error for the terminal charges, using symmetric linearization method for SGFET; R = 8 nm, tox = 1.5 nm, T = 300 K, Vds = 1 V.

69 1 Circles: exact Lines: symmetric linearization method 0.8 C gg

0.6

C sg 0.4

C 0.2 dg Normalized transcapacitances

0 0.5 1 1.5 2 V − ∆φ [V] gs

(a)

C gg 2 C dg C sg 1

−1

Relative error (%) for transcapacitances 0.5 1 1.5 2 V − ∆φ [V] gs (b) Figure 4.9: Plots of (a) transcapacitances and (b) relative error for the transcapacitances, using symmetric linearization method for SGFET; R = 8 nm, tox = 1.5 nm, T = 300 K, Vds = 1 V.

70 Chapter 5

CURRENT and CHARGE MODELS for the INDEPENDENT-GATE

ASYMMETRIC DG-FinFET 5.1 Drain Current Model

In this section the drain current expression for the independent-gate asymmetric DG-

FinFET is derived following the approach of [76] and extended to include biasing for which V1 < V2. The drain current expression (4.5) for common-gate symmetric DG-FinFETs can be used for independent-gate asymmetric DG-FinFETs:

Vd h I = µ f Q dV . (5.1) d − L n c VZs

Note that in (4.5) qn is the absolute value of inversion charge density per channel

whereas in (5.1) Qn is the total inversion charge density. The IVE and Qn for the independent-gate asymmetric DG-FinFET can have trigonometric or hyperbolic

form depending on the device parameters and applied bias as discussed in Section 3.1.

As Vc varies along the channel from Vs at the source to Vd at the drain the form

of IVE and Qn may or may not change along the channel. Depending on the form of IVE at the source end and the drain end of the channel there are three diﬀerent

cases:

Case I: In this case we have trigonometric form of IVE throughout the channel (i.e.

V V V ). s ≤ d ≤ cr

Case II: In this case we have hyperbolic form of IVE throughout the channel (i.e.

V V V ). cr ≤ s ≤ d

Case III: In this case we have trigonometric form of IVE at the source end and the

hyperbolic form of IVE at the drain end of the channel (i.e. V V V ). s ≤ cr ≤ d

Case I (V V V ): For this case we have the trigonometric solution for ψ(x) s ≤ d ≤ cr throughout the channel. Substituting for the inversion charge density from (3.21) in

71 (5.1) we have

hf 2 d Id = 8 µ Csiφt (J+ J ) s (5.2) · L − − | where 1 J = θ cot(α θ)dVc. (5.3) ± −2 φ ± · t Z and the limits of integration s and d correspond to values of (J+ J ) at the source − − and the drain end of the channel, respectively. From (3.18)

dV θ c = d ln 2 r d[θ cot (α θ)]. (5.4) 2 φ − sin (α θ) − · c1 − · t − Substituting (5.4) in (5.3) and integrating we have

2 2 2 θ J = θ cot(α θ)+ rc1θ cot (α θ) + θdα. (5.5) − − − − 2 Z

To evaluate J+ we use (3.19) which gives

dV θ c = d ln + 2 r d[θ cot (α + θ)]. (5.6) 2 φ − sin (α + θ) · c2 · t Substituting (5.6) in (5.3) and integrating yields

θ2 J = θ cot(α + θ) r θ2 cot2(α + θ)+ + θdα. (5.7) + − c2 2 Z From (5.2), (5.5), and (5.7) we have the expression for the drain current

h I = 8 µ f C φ2(f f ) (5.8) d · L si t d − s

where fd and fs are values of

f = θ2 1 r cot2(α θ) r cot2(α + θ) + θ [cot(α + θ) cot(α θ)] (5.9) − c1 − − c2 − − h i at the source and the drain end of the channel, respectively. It may be mentioned that since ψ(x) for a common-gate symmetric DG-FinFET has trigonometric form irrespective of Vc its drain current can be shown to be a special case of (5.8) (cf. Appendix G).

72 Case II ( V V V ): For this case we have a hyperbolic solution for ψ(x) through- cr ≤ s ≤ d out the channel. Substituting for the inversion charge density from (3.38) in (5.1) yields

hf 2 d Id = 8 µ Csiφt (J+∗ J ∗ ) s (5.10) · L − − where σ J ∗ = θ coth(α θ )dVc. (5.11) ± −2 φ ∗ ∗ ± ∗ · t Z and the limits of integration s and d correspond to values of (J+∗ J ∗ ) at the source − − and the drain end of the channel, respectively. From the IVE (3.35) we have

dVc θ = d ln ∗ 2 σrc1d[θ coth (α σθ )]. (5.12) 2 φt − sinh (α σθ ) − · ∗ ∗ − ∗ · ∗ − ∗ Substituting (5.12) in (5.11) and integrating yields

2 2 2 θ J ∗ = σθ coth(α σθ )+ rc1θ coth (α σθ )+ ∗ σ θ dα . (5.13) − ∗ ∗ − ∗ ∗ ∗ − ∗ 2 − ∗ ∗ Z

To evaluate J+∗ we use the IVE (3.36) which gives

dVc θ = d ln ∗ + 2 σrc2d[θ coth (α + σθ )]. (5.14) 2 φt − sinh (α + σθ ) · ∗ ∗ ∗ · ∗ ∗ Substituting (5.14) in (5.11) and integrating yields

2 2 2 θ J+∗ = σθ cosh(α + σθ ) rc2θ coth (α + σθ ) ∗ σ θ dα . (5.15) ∗ ∗ ∗ − ∗ ∗ ∗ − 2 − ∗ ∗ Z From (5.10), (5.13), and (5.15) we get drain current

hf 2 I = 8 µ C φ (f ∗ f ∗) (5.16) d · L si t d − s where fd∗ and fs∗ are values of

2 2 2 f ∗ = θ 1+ rc1 coth (α σθ )+ rc2 coth (α + σθ ) − ∗ ∗ − ∗ ∗ ∗ h i σθ [coth(α σθ ) coth(α + σθ )] (5.17) − ∗ ∗ − ∗ − ∗ ∗

at the source and the drain end of the channel, respectively.

Case III ( V V V ): The drain current for this case becomes s ≤ cr ≤ d

hf 2 I = 8 µ C φ [f ∗ f ∗ + f f ] (5.18) d · L si t d − cr cr − s

73 where fcr∗ and fcr are the respective values of f ∗ and f at the critical channel potential

Vc = Vcr within the channel. Since at Vc = Vcr, α = α = θ = θ = 0 when V1 > V2 ∗ ∗ and π α = α = θ = θ = 0 when V1 < V2 it can be seen that fcr∗ + fcr = 0 and − ∗ ∗ − (5.18) becomes

hf 2 I = 8 µ C φ [f ∗ f ] (5.19) d · L si t d − s 5.2 Reformulation of Drain Current in PSP Form

In this section we reformulate the drain current expressions given in Section 5.1 in

PSP form to facilitate the inclusion of small geometry eﬀects in a form similar to that of the PSP compact model [44, 45]. This reformulation also helps to independently model gate-1 and gate-2 ﬁeld dependent mobilities.

Case I (V V V ): s ≤ d ≤ cr Denoting θ2 f = θ cot(α θ) r θ2 cot2(α θ)+ (5.20) 1 − − − c1 − 2 and θ2 f = θ cot(α + θ) r θ2 cot2(α + θ)+ (5.21) 2 − c2 2 the drain current expression (5.8) becomes

Id = Id1 + Id2 (5.22) where h I = 8 µ f C φ2(f f ) (5.23) d1 · L si t 1d − 1s and h I = 8 µ f C φ2(f f ). (5.24) d2 · L si t 2d − 2s

The s and d in the subscript of f1 and f2 indicates their value at the source and the drain ends of the channel, respectively. Substituting for f1d and f1s and noting from (3.15)

4 φ r θ cot(α θ)= V ψ (5.25) · t c1 − 1 − s1

74 (5.23) becomes

h I = µ f C [V + φ + φ (1 g )] ∆ψ (5.26) d1 L ox1 ox1m t t − 1 1

where θ2 θ2 g = s − d , (5.27) 1 q q gn1s − gn1d q = θ cot(α θ ), (5.28) gn1s s s − s and

q = θ cot(α θ ). (5.29) gn1d d d − d

Physically qgn1s and qgn1d are the normalized gate-1 charge density at the source and

the drain end of the channel, respectively. Similarly, substituting for f2d and f2s and noting that from (3.17)

4 φ r θ cot(α + θ)= (V ψ ) (5.30) · t c2 − 2 − 2

(5.24) becomes

h I = µ f C [V + φ + φ (1 g )] ∆ψ (5.31) d2 L ox2 ox2m t t − 2 2

where θ2 θ2 g = s − d , (5.32) 2 q q gn2s − gn2d q = θ cot(α + θ ), (5.33) gn2s − s s s and

q = θ cot(α + θ ). (5.34) gn2d − d d d

The qgn2s and qgn2d are the normalized gate-2 charge density at the source and the drain end of the channel, respectively.

Case II (V V V ): cr ≤ s ≤ d For this case we denote

2 2 2 θ f1∗ = σθ coth(α σθ ) rc1θ coth (α σθ ) ∗ (5.35) − ∗ ∗ − ∗ − ∗ ∗ − ∗ − 2

75 and 2 2 2 θ f2∗ = σθ coth(α + σθ ) rc2θ coth (α + σθ ) ∗ (5.36) ∗ ∗ ∗ − ∗ ∗ ∗ − 2 then the drain current expression (5.16) becomes

Id = Id1∗ + Id2∗ (5.37)

where

hf 2 I∗ = 8 µ C φ (f ∗ f ∗ ) (5.38) d1 · L si t 1d − 1s and

hf 2 I∗ = 8 µ C φ (f ∗ f ∗ ). (5.39) d2 · L si t 2d − 2s

The s and d in the subscript of f1∗ and f2∗ indicates their value at the source and the drain ends of the channel, respectively. Substituting for f1d and f1s and noting that

4 σφ r θ coth(α σθ)= V ψ (5.40) · t c1 − 1 − s1 and σ2 = 1 (5.38) takes a form similar to (5.26) where now

2 2 θ s + θ d g = − ∗ (5.41) 1 q q ∗ gn1s − gn1d

qgn1s = σθ s cot(α s σθ s) (5.42) ∗ ∗ − ∗ and

qgn1d = σθ d cot(α d σθ d). (5.43) ∗ ∗ − ∗

Similarly, Id2∗ for this case is given by (5.31) with

2 2 θ s + θ d g = − ∗ , (5.44) 2 q q ∗ gn2s − gn2d

qgn2s = σθ s coth(α s + σθ s), (5.45) − ∗ ∗ ∗ and

qgn2d = σθ d coth(α d + σθ d). (5.46) − ∗ ∗ ∗

76 For Case III where we have trigonometric solution at source end of the channel and hyperbolic solution at drain end of the channel (5.26) and (5.31) still apply provided now g1 and g2 are given as

θ2 + θ2 g = s d (5.47) 1 q q∗ gn1s − gn1d and θ2 + θ2 g = s d . (5.48) 2 q q∗ gn2s − gn2d where qgn1s, qgn1d, qgn2s and qgn2d are given by (5.28), (5.43), (5.33), and (5.46) respectively.

Separation of the drain current into Id1 and Id2 components facilitates independent modeling of gate-1 and gate-2 ﬁeld dependent mobility by replacing µ in

Id1 and Id2 with µ1 and µ2, respectively, where µ1 is gate-1 ﬁeld dependent mobility

and µ2 is gate-2 ﬁeld dependent mobility.

5.3 Eﬀective Gate Charge Density Concept

The objective in this section is to present the drain current equation in a form

that looks as simple as the charge-sheet approximation but does not really use it.

This can be accomplished rigorously by introducing the concept of eﬀective charge

density. While the true charge density is a linear function of the surface potential,

the eﬀective charge density is not. However, this reformulation of the drift-diﬀusion

equation allows one to use the powerful symmetric linearization method developed

in [88, 89] that forms the theoretical foundation of the popular PSP model [45]. In

particular, symmetric linearization of the eﬀective charge density leads to closed-

form expressions for the terminal charges which are almost identical to those used in

PSP. This approach has been already successfully implemented for the special case

of common-gate symmetric DG-FinFETs [67].

An alternative view of what is done in this and the next section is that

we develop symmetric linearization of the diﬀerence between the actual channel

77 current and its charge sheet approximation. By doing so we are able to obtain simple analytical expressions for the terminal charges without relying on the charge-sheet approximation.

We start with the drain current expression including drift and diﬀusion components tsi/2 ∂ψ ∂n I = qµh n φ dx (5.49) d f ∂y t ∂y − tZsi/2 − For any choice of xd we have

Id = I1 + I2 (5.50) where xd ∂ψ ∂n dVc I1 = µhf q n φt dx + siEx(xd)  (5.51)  ∂y − ∂y dy   tZsi/2  − and   tsi/2 ∂ψ ∂n dV I = µh q n φ dx E (x ) c . (5.52) 2 f  ∂y − t ∂y − si x d dy   xZd 

For the trigonometric case, it is convenient to select xd at the point where the x-

component of electric ﬁeld, Ex, goes to zero (in this case the last term in (5.51) and

(5.52) is zero). This requires that xd = xd(y) be position-dependent. However, an explicit expression for xd does not enter the final expressions of the model developed below due to the fact that last term in the curly braces of (5.51) and (5.52) cancels with the values of integrals in (5.51) and (5.52) at the limit x = xd, respectively. For the hyperbolic case we set x = σ 1. This requires that the expressions for n and d ·∞ ψ as functions of x be extended from the physical range ( t /2,t /2) to the interval − si si ( t /2, ) for σ = 1 and to the interval ( ,t /2) for σ = 1, using (3.27). The − si ∞ −∞ si − last terms in (5.51) and (5.52) are included to facilitate subsequent derivation of the charge model. The currents I1 and I2 thus defined are position-dependent. However, they add up to produce constant current Id along the channel. 1 If one approaches the boundary between the trigonometric and the hyperbolic region on the V1-V2 plane [78] from inside the trigonometric region (cf. lines Γ1, Γ2 in Fig. 3.2) then xd approaches σ ·∞. This explains the selection of xd for the hyperbolic region. Naturally, this selection of xd is a matter of convenience and does not enter into the final model equation.

78 In both the trigonometric and the hyperbolic cases we deﬁne

qg1 = q ndx + siEx(xd) (5.53)

tZsi/2 −

tsi/2 q = q ndx E (x ) (5.54) g2 − si x d xZd

xd q ∂ψ dVc dEx(xd) q˜g1 = n dx + siEx(xd) + φtsi (5.55) dψs1 ∂y dψ dψ dy s1 s1 tZsi/2 − and tsi/2 q ∂ψ dVc dEx(xd) q˜g2 = dψ n dx siEx(xd) φtsi . (5.56) s2 ∂y − dψs2 − dψs2 dy xZd

Physically, qg1(y) and qg2(y) represent the charge densities at two gates at a distance y from the source. In particular, the total mobile charge density is q − g where

qg = qg1 + qg2. (5.57)

With the above deﬁnitions

dψ dq I = µh q˜ sj φ gj . (5.58) j f gj dy t dy − Substituting

q = C (V ψ ) (5.59) gj oxj j − sj in (5.58) we have dψ I = µW (˜q + φ C ) sj . (5.60) j gj t oxj dy

Using the identity ∂ψ ∂n ∂V n φ = n c (5.61) ∂y − t ∂y ∂y and the fact that in a device with the geometry shown in Fig. 3.1, Vc = Vc(y), expressions (5.51) and (5.52) can be reformulated as

dV I = µh q c . (5.62) j f gj dy

79 In particular, from (5.50) and (5.57)

dV I = µh q c . (5.63) d f g dy

Equating (5.60) and (5.62) we have

dψ dV (˜q + φ C ) sj = q c . (5.64) gj t oxj dy gj dy

Substituting dVc/dy from (5.63) yields

dψ I = µh qˆ sj (5.65) d f gj dy where qg qˆgj = (˜qgj + φtCoxj) . (5.66) qgj To interpret (5.65), consider the corresponding equation for a bulk MOSFET with

a single gate. Under the charge-sheet approximation

dψ I = µh qˆ s (5.67) d f dy where ψs denotes the surface potential and

qˆ = qi + φtCox (5.68)

where qi is the absolute value of the inversion charge density and the second term accounts for the diﬀusion current. Thus, the drain current in the double-gate device considered here rigorously without the charge-sheet approximation is given by the same expression as the current in a single gate device provided that instead of the charge density qˆ and the surface potential ψs we use the eﬀective charge density qˆgj

and the surface potential ψsj. In (5.66), the diﬀerence between q˜gj and qgj accounts for the fact that the charge-sheet approximation is not used in (5.65) and the factor

qg/qgj reﬂects the presence of the second gate. This interpretation is not necessary for the subsequent analysis but provides the motivation for symmetric linearization

of qˆgj in the next section. Indeed, such linearization of the charge qˆ for the single

80 gate bulk MOSFET leads to a remarkably simple and accurate terminal charge model

[88, 89, 45].

To complete the discussion, we present the following analytical expressions for qgj and q˜gj for j = 1, 2 derived in Appendix F.

In the trigonometric case

q = 4 φ C θ cot(α θ), (5.69) g1 · t si −

q = 4 φ C θ cot(α + θ), (5.70) g2 − · t si 2 2 q (α 1) q˜ = q φ C 1 − · gn1 0 − , (5.71) g1 g1 − t ox1 − 1 (n /q )(α 1) " − n1 gn1 0 − # and 2 + 2 qgn2(α0 + 1) q˜g2 = qg2 φtCox2 1 · (5.72) − " − 1 + (nn2/qgn2)(α0 + 1)# where

dα 2 (rc1nn1 rc2nn2) + 2 (rc1qgn1 rc2qgn2) + (qgn1 qgn2) α0 = = · − · − − , (5.73) dθ q + 2 (r n + r n ) gn · c1 n1 c2 n2 q and q is the respective gate charge density q and q normalized to 4 φ C , gn1 gn2 g1 g2 · t si qgn = qgn1 + qgn2, and nn1 and nn2 is the surface electron concentration normalized to n (4 C /C )2. i · si f In the hyperbolic case

qg1 = 4 σφtCsiθ coth(α σθ ), (5.74) · ∗ ∗ − ∗

qg2 = 4 σφtCsiθ coth(α + σθ ), (5.75) − · ∗ ∗ ∗ 2 2 q (σα 1) q˜ = q φ C 1 − · gn1 0 − . (5.76) g1 g1 − t ox1 − 1 (n /q )(σα 1) " − n1 gn1 0 − # and 2 + 2 qgn2(σα0 + 1) q˜g2 = qg2 φtCox2 1 · (5.77) − " − 1 + (nn2/qgn2)(σα0 + 1) #

where α0 is same as in (5.73).

81 5.4 Terminal Charge Model

The physical charge density qgj on gate j is a linear function of the surface potential

ψsj [cf. (5.59)] but the eﬀective charge density qˆgj is not [cf. (5.66)]. This is the price paid for the apparent simplicity of (5.65) for the drain current in terms of

qˆgj. The approximation made in the proposed charge model consists of symmetric

linearization of qˆgj. For this purpose we introduce the value qˆgjm of qˆgj at the point

y = yjm where the surface potential ψsj reaches its average value

ψ + ψ ψ = sjs sjd (5.78) sjm 2 where ψsjs and ψsjd are the values of ψsj at the source and drain ends of the channel, respectively. The simplest form of symmetric linearization consists of setting

dˆqgj qˆgj =q ˆgjm + uj (5.79) dψsj ! · ψsj=ψsjm where u = ψ ψ . This is a valid approximation closely resembling the one used j sj − sjm in the case of bulk MOSFETs [88, 89, 45]. However, in the context of a double-gate device it is somewhat diﬃcult to use, since evaluation of qˆgjm and (dˆqgj/dψsj)ψsj=ψsjm requires knowledge of Vc(yjm). Instead, we generalize (5.79) as

qˆ = C (ν α u ) (5.80) gj oxj j − j j where bias-dependent (but position-independent) coeﬃcients νj and αj are selected so as to assure model accuracy and simplicity.

Substituting (5.80) in (5.65)

dψ I = µh C (ν α u ) sj . (5.81) d f oxj j − j j dy

After integration h I = µ f C ν ∆ψ (5.82) d L oxj j sj where

∆ψ = ψ ψ . (5.83) sj sjd − sjs

82 We now select νj so that the expression for Id (available, for example, in [93, 94, 95, 76, 96]) remain unaﬀected by the symmetric linearization approximation (5.80):

LId νj = (5.84) µhf Coxj∆ψsj

In this way the new charge model can be used with any of the published drain current

models and the channel potential Vc at the point y = yjm is not needed. In this work

we use the exact analytical current model of [76]. For the linearization coeﬃcient αj we use the quotient approximation [66]

qˆgjd qˆgjs αj = − . (5.85) − Coxj∆ψsj

In the final analysis, this selection of νj and αj is justified by comparing the charge model with the results of numerical computations performed in Section 5.5. Never- theless, it is instructive to point out the difference between (5.79) and (5.80). Using

(5.79) provides an exact value for qˆgj at y = yjm but approximate expression for Id.

On the other hand, (5.80) provides approximate expression for qˆgjm but does not introduce any error for the drain current.

The advantage of the symmetrically linearized form (5.80) of the eﬀective charge densities is that it leads to simple expressions for the position dependence of the surface potential for the terminal charges. Equating (5.81) and (5.82) yields

dy L(H u ) = j − j (5.86) duj Hj∆ψsj where νj Hj = . (5.87) αj The total charge on gate j is

L ujd dy QGj = hf qgjdy = hf qgj duj (5.88) duj Z0 uZjs

83 where ujs and ujd are the values of uj at the source and drain ends of the channel, respectively. Substituting (5.86) in (5.88) we have

∆ψsj/2 L(Hj uj) QGj = hf qgj − duj (5.89) Hj∆ψsj ∆ψZsj/2 − where

q = C (V u ) (5.90) gj oxj oxjm − j and V = V ψ is the voltage across oxide t at point y = y . Hence oxjm j − sjm oxj jm ∆ψ2 Q = h LC V + sj (5.91) Gj f oxj oxjm 12 H · j ! The drain charge is found from Ward-Dutton partitioning [97]

L 2 y Q = h q dy (5.92) D − f gj L jX=1 Z0 or ∆ψ /2 2 sj hf dy QD = qgjy duj. (5.93) − L j=1 duj ∆ψZsj/2 X− To evaluate the integral we use the relations between the position y and the surface

potentials which are obtained by integrating (5.86):

L u2 y = y + u j (5.94) jm ∆ψ j − 2 H sj · j ! where L ∆ψ y = 1+ sj . (5.95) jm 2 4 H · j ! Then

2 2 Voxjm ∆ψsj ∆ψsj ∆ψsj QD = hf L Coxj 1 2 . (5.96) − " 2 − 12 − 2 Hj − 20 Hj !# jX=1 · ·

Finally, the integrated source charge is evaluated from the neutrality condition QS = (Q + Q + Q ). − G1 G2 D The concept of symmetric linearization of the eﬀective charge has been in-

vestigated for a common-gate symmetric DG-FinFET in the previous chapter [67].

84 The present model includes [67] as a special case (cf. Appendix G), thus eliminating the need for two separate models of symmetric and asymmetric DG-FinFETs which until now represented the state of the art in compact modeling of these devices.

5.5 Results and Discussion

To verify the accuracy of the proposed model we compare it with the results of numerical integration of (5.88) and (5.92) and also with two-dimensional TCAD simulations [98]. All transcapacitances are normalized to Cox1hf L. These capacitances are automatically evaluated in SPICE-like circuit simulators by diﬀerentiating terminal charges w.r.t. terminal voltages.

The terminal charges and transcapacitances are plotted for different biases assuming T = 300 K, tsi = 10 nm and ∆φ1 =∆φ2 = 0. The asymmetry is introduced with different gate oxide thicknesses. To concentrate on the core model the length and height of the channel are kept sufficiently long (L = hf = 1 µm) to suppress small geometry effects. These effects can be introduced as a correction to the core model as done for symmetric DG-FinFET [56].

Figs. 5.1a and 5.1b show the terminal charges and the transcapacitances as a functions of Vg1 for independent-gate symmetric DG-FinFET with Vg2 and Vd as parameters. In these plots the channel under gate 2 is in weak inversion. Figs. 5.2a

and 5.2b show similar plots for the same device with channel under gate 2 strongly

inverted. The terminal charges and the transcapacitances plots versus drain voltage

are shown in Figs. 5.3a and 5.3b, respectively, for ﬁxed values of Vg1 and Vg2.

The capacitances versus Vg1 plots for asymmetric DG-FinFET with Vg2 and

Vd as parameters are shown in Fig. 5.4 with the channel under the gate 2 weakly inverted, and in Fig. 5.5 with the channel under the gate 2 strongly inverted. Fig. 5.6

shows a plot of transcapacitances as functions of Vd. Finally, at Vds = 0 the re-

movable singularity in the expression for Hj does not appear since an expression

85 equivalent to, but more elaborate than (5.87) is used. The plots for charges and transcapacitances at Vds = 0 V are shown in Figs. 5.7a and 5.7b, respectively.

Good accuracy of the proposed model is observed in all cases. The small diﬀerences between the TCAD results and the new model present in Fig. 5.5 are inconsequential for practical compact modeling purposes and do not aﬀect the physical behavior of the device transcapacitances.

86 −14 x 10 2 1D Numerical Model 1.5 QG1

0.5

0 QG2 Terminal charges [C] −0.5 QD

−1 QS

0 0.5 1 1.5 2 Vg1 [V]

(a)

0.8 1D Numerical Cg1g1 0.7 Model 2D TCAD 0.6

0.5

0.4 Csg1

0.3 Cdg1 0.2 Cg2g1 Normalized transcapacitnaces 0.1

0 0 0.5 1 1.5 2 Vg1 [V]

(b)

Figure 5.1: Comparison of terminal charges (a) and transcapacitances (b) obtained from the new model and numerical computations; tox1 = tox2 = 2 nm , Vg2 = 0.4 V and Vd = 1.5 V.

87 −14 x 10 2.5 1D Numerical 2 Model QG1 1.5

QG2 0.5

Terminal charges [C] −0.5 QD −1 QS −1.5 0 0.5 1 1.5 2 Vg1 [V]

(a)

1 1D Numerical Model 0.8 2D TCAD Cg1g1

0.6

Csg1 0.4

Cdg1 0.2 Normalized transcapacitnaces Cg2g1

0 0 0.5 1 1.5 2 Vg1 [V]

(b)

Figure 5.2: Comparison of terminal charges (a) and transcapacitances (b) obtained from the new model and numerical computations; tox1 = tox2 = 2 nm, Vg2 = 1.0 V and Vd = 0.5 V.

88 −14 x 10 2.5 1D Numerical 2 QG1 Model

1.5

0.5

Q 2 0 G

Terminal charges [C] −0.5 QD

−1 QS

0 0.5 1 1.5 2 Vd [V]

(a)

0.6 Cdd 1D Numerical 0.5 Model

0.4 Cg1d 0.3

0.2 Cg2d

0.1

−0.1 Csd Normalized transcapacitnaces −0.2

−0.3 0 0.5 1 1.5 2 Vd [V]

(b)

Figure 5.3: Comparison of terminal charges (a) and transcapacitances (b) obtained from the new model and numerical computation; tox1 = tox2 = 2 nm, Vg1 = 2.0 V and Vg2 = 0.6 V.

89 1 1D Numerical Model C 1 1 0.8 2D TCAD g g

0.6

Csg1 0.4

0.2 Cdg1 Normalized transcapacitnaces Cg2g1

0 0 0.5 1 1.5 2 Vg1 [V]

Figure 5.4: Comparison of transcapacitances obtained from the new model and numerical computations; tox1 = 2 nm, tox2 = 10 nm, Vg2 = 0.6 V and Vd = 0.5 V.

1D Numerical C 1 1 0.7 Model g g 2D TCAD 0.6

0.5

0.4 Csg1

0.3 Cdg1

0.2

Normalized transcapacitnaces 0.1 Cg2g1

0 0 0.5 1 1.5 2 Vg1 [V]

Figure 5.5: Comparison of transcapacitances obtained from the new model and numerical computations; tox1 = 2 nm, tox2 = 10 nm, Vg2 = 1.5 V and Vd = 2.0 V.

90 0.5 Cdd 1D Numerical 0.4 Model Cg1d

0.3

0.2

C 2 0.1 g d

Normalized transcapacitnaces −0.1 Csd

−0.2 0 0.5 1 1.5 2 Vd [V]

Figure 5.6: Comparison of transcapacitances obtained from the new model and numerical computations; tox1 = 2 nm, tox2 = 10 nm, Vg1 = 2.0 V and Vg2 = 0.6 V.

91 −14 x 10 2.5 Model 2 2D TCAD QG1 1.5

0.5 QG2 0

Terminal charges [C] −0.5

−1 QS = QD

0 0.5 1 1.5 2 Vg1 [V]

(a)

1 Model 2D TCAD Cg1g1 0.8

0.6 Csg1 = Cdg1

0.4

0.2 Normalized transcapacitnaces Cg2g1 0 0 0.5 1 1.5 2 Vg1 [V]

(b)

Figure 5.7: Comparison of terminal charges (a) and transcapacitances (b) obtained from the new model and numerical computation at Vds = 0.0 V; tox1 = 2 nm, tox2 = 10 nm, and Vg2 = 0.7 V.

92 5.6 Model Implementation and Simulation

As Verilog-A has emerged as the de facto standard language for deﬁning compact

models [99] we have implemented our model in Verilog-A and used this, in a com-

mercial circuit simulator, to investigate circuit behavior. Two examples illustrate the

advantages of the gate-to-gate coupling feature of independent gate DG-FinFETs for

both analog and digital applications. A double balanced mixer [100, 34] and Schmitt

trigger [101] are shown in Figs. 5.8 and 5.9, respectively. In the mixer circuit RF+

and RF- are the RF signal ports, with input frequency fRF, and LO+/LO- is the

local oscillator signal of frequency fLO. The ‘+’ signal is antiphase with respect to

the ‘ ’ signal. A three tone (fRF1, fRF2, and fLO) harmonic balance simulation of − the mixer was done and Fig. 5.10 shows the output power of the ﬁrst, second, and third order inter-modulation products (at frequencies fRF1 fLO , fRF1 fRF2 , | − | | − | and 2fRF1 fRF2 fLO , respectively) as a function of the input power of the RF | − − | signals. The slopes of the inter-modulation product power in Fig. 5.10 are very close to their theoretical values. Two situations are shown, with symmetric gate oxides and with an asymmetry in the thickness of the two gate oxides of each DG-

FinFET. For the symmetric case the second order product of the mixer cancels out, as expected. However, the asymmetric case destroys the balance of the mixer, which results in the non-zero second order product seen in Fig. 5.10.

In the Schmitt trigger circuit of Fig. 5.9 the threshold voltages of M1 and

M2 are altered dynamically by positive feedback from output to gate 2 of both M1 and M2. This causes hysteresis in the transfer characteristic as shown in Fig. 5.11. The four transistor independent-gate FinFET Schmitt trigger has advantages of reduced area and reduced power consumption compared to a conventional six transistor common-gate FinFET Schmitt trigger [101].

93 VDD VDD

RL RL

+Vout−

M1 M2 M3 M4

RF+ LO+ RF- LO- RF+

Figure 5.8: Double balanced mixer.

VDD VDD

M2 M4

Vin Vout

CL M1 M3

Figure 5.9: Schmitt trigger.

94 0

Fundamental slope=1 −50

−100 nd 2 Harmonic slope=2 [dbmW] out P −150 rd 3 Harmonic slope=3 Balanced −200 Unbalanced

−50 −40 −30 −20 −10 P [dBmW] in Figure 5.10: Harmonic balance simulation of double balance mixer shown in Fig. 5.8.

1.5

1 [V]

out 0.5 V

−0.5 0 0.5 1 1.5

Vin [V] Figure 5.11: Transfer characteristics of independent-gate FinFET Schmitt trigger shown in Fig. 5.9.

95 Chapter 6

CONCLUSIONS

The transcapacitance characteristics of bulk and SOI DG-FinFETs are studied in all

regions of operation and it is found that the unipolar approximation is inaccurate

in describing the observed transcapacitances of bulk DG-FinFETs in the accumula-

tion region. An accurate approximate ambipolar IVE for common-gate symmetric

DG-FinFETs considering both electron and hole contributions to space charge is

proposed. The new IVE developed in this work is general and can be adopted in

any surface-potential-based compact model of DG-FinFETs with intrinsic or lightly-

doped bodies.

We have presented an accurate closed form algorithm for solving the am-

bipolar IVE of common-gate symmetric DG-FinFETs. The new algorithm can be

used with any surface-potential-based compact model of common-gate symmetric

DG-FinFETs. We also show that the earlier unipolar approximation of the IVE in

[62] emerges as an important special case of the more general ambipolar IVE.

Based on the new IVE a compact core model for drain current and terminal

charges valid in all regions of operation is developed for common-gate symmetric DG-

FinFET. Distinct C-V characteristics of bulk and SOI FinFETs can be reproduced

by the new model with good accuracy. The approximations developed in [56, 57] and

[82] from diﬀerent assumptions are shown to be equivalent and can be signiﬁcantly

improved by developing symmetric linearization forms that do not involve the charge-

sheet approximation. The new closed-form expressions for the drain current and

terminal charges are similar to those used in the bulk PSP model. The expression

for Id is exact while those for QG, QS, QB and QD are accurate within 1% for common-gate symmetric DG-FinFETs and 2% for SGFET.

The solution space for the Poisson-Boltzmann equation in independent-gate asymmetric DG-FinFETs has been partitioned including all possible cases. The

96 analytical expressions for the partition lines are given in terms of the Lambert W function. The results simplify the development of a core compact model of asymmetric DG-FinFETs. A surface-potential-based compact model of the independent-gate asymmetric DG-FinFET, valid for all inversion conditions (from weak to strong inversion) of both channels, is developed, veriﬁed, and implemented in a circuit simulator. Eﬃcient numerical IVE solution suitable for circuit simulator implementation is proposed.

We have developed analytical C continuous models for terminal charges of ∞ independent-gate asymmetric DG-FinFETs valid for all bias conditions. Terminal charges are obtained through the linearization of the eﬀective gate charge densities as functions of the surface potentials.

The equations of the new models are brought in a form similar to that used in the PSP model but with separate contributions from each of the two gates. The structural similarity to the PSP [45] and PSP-based symmetric DGFET models [57] means that various small-geometry eﬀects can be introduced in a similar manner. For the common-gate symmetric DGFET this approach has been already experimentally veriﬁed in [56].

Sample circuit simulations demonstrate the convergence properties and prac- ticality of the new compact model. This work provides a promising core model for the development of a practical compact DG-FinFET and SGFET model.

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107 APPENDIX A

Derivation of (2.26)

108 The integral in (2.23) can be written as

h dh I = 0 , (A.1) h0(h0 k) (h0 1/k) hZ0 − − p ϕ ϕ0 where h = e and k = e− . For η = 1 we have h> 1/k > k. Setting

1 h = ; 0 t π/2, (A.2) k sin2 t ≤ ≤ we find t π/2 dt dt I = 2 √k 0 0 , (A.3) − ·  √1 k2 sin2 t − √1 k2 sin2 t  Z0 0 Z0 0  − −  where   ϕ −ϕ 1 0 t = sin− e 2 (A.4) The first and second integrals are incomplete and complete elliptic integral of first

kind in Legendre’s form as deﬁned in (2.24) and (2.25). Thus,

ϕ0/2 ϕ0 ϕ0 I = 2 e− F t, e− K e− . (A.5) − · − Similarly, for η = 1 where h< 1/k < k setting − sin2(u) h = ; 0 u π/2 (A.6) k ≤ ≤ yields ϕ 0 ϕ ϕ I = 2 e 2 [F (u, e 0 ) K (e 0 )] , (A.7) · − where ϕ −ϕ 1 0 u = sin− e− 2 (A.8) Equation (A.5) and (A.7) can be combined together as

− − ηϕ0 η(ϕ0 ϕ) 1 ηϕ0 ηϕ0 I = 2 ηe 2 F sin− e 2 , e− K e− . (A.9) − · − Substituting (A.9) in (2.23) yields (2.26).

109 APPENDIX B

Equivalent form of Equation (2.26)

110 We show that (2.26) is equivalent to equation (7) of [64]. The integral in

(2.23) can be written as

ϕ 1 dϕ I = 0 . (B.1) 2 2 2 Z cosh (ϕ /2) cosh (ϕ0/2) ϕ0 0 − q ϕ ϕ0 Setting r = cosh 2 / cosh 2 yields

r dr I = η 0 (B.2) 2 2 2 Z1 (1 r ) 1 cosh (ϕ /2) r − 0 − 0 · 0 r h i or

r 1 dr0 dr0 I = η   .  2 2 2 − 2 2 2  Z0 (1 r0 ) 1 cosh (ϕ0/2) r0 Z0 (1 r0 ) 1 cosh (ϕ0/2) r0  r − − · r − − ·  h i h (B.3)i   The integrals in (B.3) are elliptic integrals in a form given in equation (5) of [64].

They can be easily transformed into Legendre’s form given in (2.24) and (2.25). As in [64] denote z dx Felliptic z, k = , (B.4) { } √1 x2√1 k2x2 Z0 − − then (B.3) becomes

I = η [F r, cosh(ϕ /2) F 1, cosh(ϕ /2) ] . (B.5) elliptic{ 0 }− elliptic{ 0 }

Substituting (B.5) in (2.23) and setting ξ = 0, ϕ = ϕs yields equation (7) of [64]. We note that while I is real, each of the two terms in (B.3) contains imaginary parts.

111 APPENDIX C

Asymptotes of ϕ0 for the Common-Gate Symmetric DG-FinFET

112 We start with the unipolar IVE (2.57). In the region where ϑ is small we retain the ﬁrst two terms in the Taylor series expansion

(1 + 4 r )ϑ2 (1 + 8 r ) ϑ4 ln(ϑ sec ϑ) + 2 r ϑ tan ϑ = ln(ϑ)+ · c + · c + (C.1) · c 2 12 · · · in (2.57) to yield (1 + 4 r )ϑ2 ln(ϑ)+ · c F = 0. (C.2) 2 − b Equation (C.2) can be solved for ϑ using the principal branch of the Lambert-W

function [79] W [(1 + 4 r )e2 Fb ] ϑ = · c · . (C.3) s 1 + 4 r · c From (2.53) and (C.3)

ηx t W [(1 + 4 r )e2 Fb ] ϕ(0) = n 2 η ln si + η ln · c · . (C.4) 0 2 − · 4 L 1 + 4 r · di ( · c ) The following approximation is valid in this region where the argument (1+4 r )e2 Fb · c · of W is small 1+ 123 z + 21 z2 W (z) ln(1 + z) 40 10 . (C.5) 143 713 2 ≈ · 1+ 40 z + 240 z Here the rational portion is the Pade approximation of W (z)/ ln(1+z) was obtained by using Mathematica [102].

In the region where ϑ is close to π/2 the Taylor series expansion of

πr ln(ϑ sec ϑ) + 2 r ϑ tan ϑ = c 2 r + · c π/2 ϑ − · c − π π 2 πr π ln ln ϑ + c ϑ . (C.6) 2 2 π 3 2 − − − − Retaining the ﬁrst four terms of the series expansion in (C.6) and substituting in

(2.57) yields πr π π c ln ϑ 2 r + ln F = 0. (C.7) π ϑ − 2 − − · c 2 − b 2 − Solving (C.7) for ϑ using the principal branch of the Lambert W function we obtain

π πr ϑ = c . (C.8) 2 − W [2 r exp (2 r + F )] · c · c b 113 From (2.53) and (C.8)

(π/2) ηxn tsi π πrc ϕ0 = 2 η ln + 2 η ln (C.9) 2 − · 4 L · 2 − W (2 r e2rc eFb ) · di · c In this region the argument 2 r e2 rc eFb of the Lambert W function in (C.9) is large · c · and we can use the approximation suggested in [103] for z e ln(z) ln[ln(z)] 2 + ln(z) W (z) { − } . (C.10) ≈ 1 + ln(z) ln[ln(z)] − Then from (C.9) and (C.10)

ηx t π πr [1 + G ln(G)] ϕ(π/2) = n 2η ln si + 2 η ln c − (C.11) 0 2 − 4 L · 2 − [G ln(G)]2 + G · di − where

G = F + 2 r + ln(2 r ). (C.12) b · c · c

For computational purpose we change G to Gm where

1 G = G + 6 r (G 6 r )2 + 1 . (C.13) m 2 · c − − · c q

114 APPENDIX D

Derivation of q˜n and αl

115 The potential ψ(x) in inversion condition (ϕ > 5) can be obtained from

(2.26) as x ψ V ψ(x)= ψ + 2 φ ln sec exp 0 − c . (D.1) 0 · t 2 L 2φ · di t Rearranging (D.1) using (2.59) yields

t 2 θx ψ(x)= V 2 φ ln si cos · . (D.2) c − · t 4 L θ t · di si Hence, ∂ψ ∂Vc 1 2 x 2 θx ∂θ = + 2 φt + · tan · . (D.3) ∂y ∂y · θ tsi tsi ∂y From (D.3) dVc 1 2 x 2 θx ∂ψ/∂y dθ + 2 φt θ + t· tan t· = · si si (D.4) h i ∂ψs/∂y dVc + 2 φ 1 + tan θ dθ · t θ thus 2 x 2 θx ∂ψ/∂y tan θ + t· tan t· =1+ si si . (D.5) ∂ψs/∂y 2 r tan θ + θ · cos2 θ where we have used (4.7). The electron concentration n can be obtained by substi-

tuting (D.2) in (2.3) to yield

2 θx n = n sec2 · (D.6) 0 t si where n0 denotes the electron concentration at x = 0. From (D.5), (D.6), and (4.17) we obtain θ u qn0tsi tan u θ tan u q˜n = qn + − 2 du (D.7) 4 r θ tan θ + θ 0 cos u · c cos2 θ Z where it is convenient to set qn0tsi/θ = qn cot θ. Using standard trigonometric identities (D.7) can be reduced to (4.18).

To evaluate αl note that by (4.36)

dg α = 1 φ 1 (D.8) l − t dψ s ψs=ψsm

where sin(2 θ) 2 θ cos(2 θ) g = q g = · − · · (D.9) 1 i · 2 θ + sin(2 θ) · · 116 then dg dg1 1 = dθ (D.10) dψ dψs s dθ where dg 8 θ2 sin(2 θ) 4 sin(2 θ) cos2 θ + 8 θ cos2 θ 1 = · · − · · · (D.11) dθ (2 θ + sin(2 θ))2 · · and dψs/dθ is found from (D.2) as

dψs dVc 1 = + 2 φt tan θ + . (D.12) dθ dθ · θ

Substituting dVc/dθ from (4.7) yields dψ s = 4 φ r (tan θ + θ sec2 θ) (D.13) dθ − · t c and from (D.8), (D.9) and (D.11) 1 [2 θ2 sin2(2 θ ) sin(θ ) cos2 θ + θ cos2 θ ] α =1+ · m · m − m m m m (D.14) l r · (2 θ + sin(2 θ ))2(tan θ + θ sec2 θ ) c · m · m m m m where

θm = θ . (D.15) |ψs=ψsm An equivalent form is θ2 q (2 q2 + 2 θ2 1) + q2 + θ2 α =1+ m im · im · m − im m . (D.16) l 2 r · (q2 + q + θ2 )3 · c im im m While for common-gate symmetric DG-FinFETs qim is given by (4.42), the corresponding approximation θ2 = θ2 (θ2 + θ2)/2 for θ2 is valid only in weak inversion m 0 ≡ s d m where q = θ tan θ θ2. Since in strong inversion, q θ2 an approximation [67] i ≈ im m θ2 q (2 q2 + 2 θ2 1) + q2 + θ2 α =1+ m im · im · 0 − im 0 (D.17) l 2 r · (q2 + q + θ2)3 · c im im 0 is quite accurate in all regions of DG-FinFET operation. However, approximating

2 2 θm by θ0 in (D.17) does not result in accurate expressions for QG and QD. Better accuracy is achieved by setting θ2 = 3 q /4 i.e. by using α in the form given by m · im l 3 q q (2 q2 + 2 θ2 1) + q2 + θ2 α 1+ · im im · im · 0 − im 0 . (D.18) l ≈ 8 r · (q2 + q + θ2)3 · c im im 0 This conclusion is invariant of device parameters such as tox and tsi. Without adding

2 much error further simpliﬁcation is made to (D.18) in [63] by setting θ0 in (D.18) to

qim which gives (4.41).

117 APPENDIX E

Comparison of Symmetric Linearization Method for bulk MOSFETs and

DG-FinFETs

118 For both DG-FinFETs and bulk MOSFETs symmetric linearization is introduced to obtain compact expressions for the terminal charges. The diﬀerence is that in the case of the bulk device symmetric linearization is required for the inversion charge while for undoped DG-FinFETs the inversion charge

Q = q = 2 C (V ∆φ ψ ) (E.1) i − n − · ox g − − s is already a linear function of ψs. However, the surface potential dependence of the

“effective charge” qñ is nonlinear necessitating the approximation given by (4.33). In other words, for DG-FinFETs the complexity of the model comes from the fact that, generally speaking, ∂ψ/∂y = dψ /dy and symmetric linearization approximation is 6 s introduced in order to account for this complication in a computationally efficient way.

The second diﬀerence is that the value of ν in this work selected so as to make the expression (4.25) for Id not just accurate but exact. This approach is also applicable to bulk MOSFETs. Indeed, the equations for the drain current in [90, 41] can be written in the form

W γ Id = µ Cox Vgb Vfb ψsm + φt 1+ L " − − √a + √b! (2 γ/3)(2 ψ 2 φ + √ab) · · m − · t ∆ψ (E.2) − √a + √b # where W is the width of the channel, Vfb denotes ﬂat-band voltage, γ is the body eﬀect factor, a = ψ φ and b = ψ φ . sd − t ss − t Using the version of the symmetric linearization method in the form

Q = C (ν α u) (E.3) i − ox − l and proceeding as in [88] yields

W I = µ C (ν + α φ )∆ψ. (E.4) d L ox l t

119 It is now possible to select ν so that (E.4) coincides with the exact result (E.2):

(2 γ/3)(2 ψm + 2 φt + √ab) ν = Vgb Vfb ψm · · · − − − √a + √b γ + φt 1+ αl (E.5) √a + √b − !

The linearization coeﬃcient αl can be selected as in [88, 89]

γ α =1+ (E.6) l 2 √ψ φ · sm − t or as γ αl =1+ . (E.7) √a + √b The essence of symmetric linearization, however, is to obtain simple but accurate

approximations for the terminal charges. Following [88] or Section 4.4 we obtain

(4.43)-(4.47) with ν H = + φt (E.8) αl the only diﬀerence being that ν and αl are now given by (E.5) and (E.6). The total gate charge, QG, is still given by (4.52) (without the coeﬃcient 2), while

ν α ∆ψ ∆ψ ∆ψ2 Q = WLC l 1 (E.9) D − ox 2 − 12 − 2 H − 20 H2 " · · !# As shown in Fig. E.1, for charges this approach produces results that are even more

accurate than the symmetric linearization version developed in [88]. However, this

requires using expression (E.5) which is more complex than the approximation ν =

(Q )/C used in [88]. In contrast, for undoped DG-FinFETs (4.39) results − i|ψ=ψsm ox in a model that is both simpler and more accurate than that based on (4.35). This

explains the diﬀerence in our implementation of the symmetric linearization method

in this work relative to [88, 89].

120

Original charge sheet model Original symmetric linearization method 1 New symmetric linearization method gg

0.8

0.6

0.4 Normalized capacitance C 0.2

−1 0 1 2 3 4 V − V [V] gb fb (a)

0.04

gg 0.02

−0.02

−0.04 Relative error (%) for C

Original symmetric linearization −0.06 New symmetric linearization method

−1 0 1 2 3 4 V − V [V] gb fb (b)

Figure E.1: (a) Normalized transcapacitance Cgg using original charge sheet model [89, 104], and two versions of symmetric linearization; (b) Relative error (%) for C for present technique and symmetric linearization of [88]; N = 3 1017 cm 3, gg A × − tox = 2.5 nm and Vds = 1 V, Vbs = 0 V.

121 APPENDIX F

Derivation of (5.74)-(5.77)

122 We present a derivation of expressions (5.74)-(5.77) for the hyperbolic case.

Expressions (5.69)-(5.73) for the trigonometric case are derived similarly. Substitu- tion of (3.39) in (5.53) and integration yields (5.74) once it is noted that from (3.30)

E(σ ) = 4 σφtθ /tsi. Similarly, (5.75) follows from (5.54) and (3.39). ·∞ · ∗ The derivation of (5.76) requires evaluation of the integral in (5.55). For this purpose, we diﬀerentiate (3.27) with respect to y to obtain

∂ψ dVc 2 φt ∂ 2 θ x = + · θ csch α + σ · ∗ (F.1) ∂y dy 2 θ∗x ∂y ∗ ∗ t θ csch α + σ · × si ∗ ∗ tsi h i where from (3.35)

dVc 2 φt d d = · [θcsch(α σθ )] 4 σφtrc1 [θ coth(α σθ )] dy −θ csch(α σθ ) dy ∗ − ∗ − · dy ∗ ∗ − ∗ ∗ ∗ − ∗ (F.2)

Setting x = t /2 in (F.1) yields − si

dψs1 d = 4 σφtrc1 [θ coth(α σθ )] (F.3) dy − · dy ∗ ∗ − ∗

Substitution of n(x), ∂ψ/∂y, and, dψs1/dy from (3.39), (F.2) and (F.3), respectively, in (5.55) and integration yields (5.76). The derivation of (5.77) follows the same lines, except that now it is convenient to obtain dVc/dy from (3.36) rather than (3.35):

dVc 2 φt d d = · [θ csch(α + σθ )] + 4 σφtrc2 [θ coth(α + σθ )] dy −θ csch(α + σθ ) dy ∗ ∗ ∗ · dy ∗ ∗ ∗ ∗ ∗ ∗ (F.4)

Finally, (5.73) is obtained by diﬀerentiating (3.37).

123 APPENDIX G

Common-Gate Symmetric DG-FinFET as a Special Case of Independent-Gate

Asymmetric DG-FinFET

124 It is worth noting that we can get the drain current and q˜g for a common- gate symmetric DG-FinFET deﬁned in [67] as a special case of (5.8) and (5.71), respectively. In common-gate symmetric DG-FinFETs we have V1 = V2, rc1 = rc2 = rc, α = π/2 and the ψ(x) has a trigonometric form [69]. Thus, considering the drain current expression for case I we have

h I = 8 µ f C φ2(f f ) (G.1) d · L si t d − s

where

2 2 2 f = rc1u + rc2u+ θ [u u+] (G.2) − − − − − h i and π u = θ cot(α θ)= θ cot θ = θ tan θ. (G.3) ± 2 ± ± ∓ Hence (G.2) becomes

f = 2 r θ2 tan2 θ θ2 2 θ tan θ. (G.4) − · c − − · h i Substituting (G.4) in (G.1) the expression for drain current becomes

2 θs W 2 2 2 θ Id = 16 µ Csiφt rcθ tan θ + θ tan θ . (G.5) · L − 2 ! θd

The equation (G.5) is the equation for the drain current of common symmetric DG-

FinFET [60].

Symmetry allows us to write

q q = q = g (G.6) g1 g2 2 and q˜ q˜ =q ˜ = g . (G.7) g1 g2 2 The constant α results in dα/dθ = 0 which is consistent with (5.73) for α = π/2.

Substituting α = π/2 and dα/dθ = 0 in (5.71)

sin(2 θ) 2 θ cos(2 θ) q˜ = q + C φ · − · · . (G.8) g1 g1 ox t 2θ + sin(2θ)

125 From (G.6)-(G.8),

sin(2 θ) 2 θ cos(2 θ) q˜ = q + 2 C φ · − · · (G.9) g g · ox t 2 θ + sin(2 θ) · · which is precisely the result given in [67] for common-gate symmetric DG-FinFETs.

126