How Far Can We Push Si CMOS? What Lies Beyond?

How far can we push Si CMOS? What lies beyond?

Prof. Krishna Saraswat

Department of Electrical Engineering Stanford University Stanford, CA 94305 [email protected]

araswat tanford University 1 Saraswat - EE311/Future Devices

Physical Limits in Scaling Si MOSFET

Gate stack • Tunneling current ⇒ ⇑ Ioff • Gate depletion ⇒ ⇑ EOT Source/Drain • Parasitic resistance • Doping level, abruptness Gate Power ⇑ • CV2f ⇑ Source Drain • S/D leakage current ⇑ • Gate leakage current ⇑ Substrat e Channel/Drain • Surface scattering - mobility ⇓ • High E-field - mobility ⇓

• DIBL ⇒ drain to source leakage ⇑ Ioff • Subthreshold slope ≥ kT/q ⇒ ⇑ Ioff • VG - VT decrease ⇒ ⇓ ION Net result: Bulk-Si CMOS device performance increase commensurate with size scaling is unlikely beyond the 65 nm node araswat tanford University 2 Saraswat - EE311/Future Devices

1 Bulk-Si Performance Trends

1010 e c

n Conventional Bulk CMOS a Predictions m r

o (Bulk) f ITRS r 1 e 1.0

P IEDM Benchmark

v Technologies i t

a Novel l

e Device R MOSFET in Bulk Si Structures 0.10.1 1985 1990 1995 2000 2005 2010 2015 1985 1990 1995 2000 2005 2010 2015 Technology Node 130nm 80nm 45nm 22nm Physical Gate Length 90nm 32nm 18nm 9nm  Maintaining historical CMOS performance trend requires new semiconductor material and structures by 2008-2010…

 Earlier if current bulk-Si data do not improve significantly araswat tanford University 3 Saraswat - EE311/Future Devices

Nanotechnology Eras 0.1 100 65 nm 45 nm Generation 32 nm LGATE 22 nm 16 nm 11 nm micron 0.01 8 nm 10 nm

Evolutionary Revolutionary CMOS CMOS Exotic

0.001 1 2000 2010 2020

Reasonably Nanotubes Really Familiar Nanowires Different araswat Source: Mark Bohr, Intel tanford University 4 Saraswat - EE311/Future Devices

2 Extending CMOS

• Novel transistor structures and materials integration can extend commensurate CMOS scaling beyond planar bulk-Si solutions: – Improved Electrostatics and Contacts • Double-gate or surround-gate • Schottky source/drain – Improved Materials Properties • High mobility materials (e.g. strained Si/SiGe/Ge, etc.) • Extended CMOS functionality via new Integration Technologies • 3-D Integration (Billions of transistors on a chip) • Exploration of new frontier devices – Alternatives compatible with silicon

araswat tanford University 5 Saraswat - EE311/Future Devices

New Structures and Materials for Nanoscale MOSFETs CURRENT BULK MOSFET 4 5 Problem 1: Poor Electrostatics ⇒ increased Ioff 3 4 Solution: Double Gate 2 - Retain gate control over channel - Minimize OFF-state drain-source leakage 1 Problem 2: Poor Channel Transport ⇒ decreased Ion Solution - High Mobility Channel - High mobility/injection velocity High ION - High drive current and low intrinsic delay Low IOFF Problem 3: S/D Parasitic resistance ⇒ decreased Ion Solution - Metal Schottky S/D FUTURE MOSFET - Reduced extrinsic resistance Top Gate Problem 4. Gate leakage increased Solution - High-K dielectrics Schottky Schottky - Reduced gate leakage Source Drain Problem 5. Gate depletion ⇒ increased EOT Bottom Gate Solution - Metal gate High µ High-K channel dielectric - High drive current

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3 Evolution of MOSFET Structures Bulk Partially Depleted SOI

G G S D S D

• Device design translates well between bulk and PD SOI • e.g. short channel effect control by doping/halo (same as bulk) • Reduced junction capacitances • Dynamic floating body effect - parasitic bipolar

Ref: Philip Wong, IEDM Short Course, 1999 araswat tanford University 7 Saraswat - EE311/Future Devices

Evolution of MOSFET Structures

Partially Depleted SOI Ultra-Thin Body Single Gate SOI

Gate Source SOI Drain Si

SiO2 TBOX

Silicon Substrate Advantages of Ultra-Thin Body SOI • Depleted channel ⇒ no conduction Ultra-Thin Body Double path is far from the gate Gate SOI • Short channel effects controlled by geometry Gate 1 Vg • Steeper subthreshold slope • Lower or no channel doping Source SOI Drain Si - Higher mobility - Reduced dopant fluctuation Tox Gate 2 araswat Ref: Philip Wong, IEDM Short Course, 1999 tanford University 8 Saraswat - EE311/Future Devices

4 Fully Depleted SOI FET

J. Chen et al., Symp. VLSI Tech., 1999.

araswat tanford University 9 Saraswat - EE311/Future Devices

Ultra-Thin Body Single vs. Double Gate SOI

• Can be used as a second gate • Not the ideal structure for double gate H.-S. P. Wong, et al., p. 407, IEDM 1998.

• In DG MOS better electrostatic control of the channel ⇒ Reduced short channel effects

Wong, et al. IEDM 1998 araswat tanford University 10 Saraswat - EE311/Future Devices

5 Double-Gate FET

• ~2X current drive for the same device width Depletion regions • Very thin (5 nm) undoped channel ⇒ better electrostatic control Steeper subthreshold slope - approaching 60 mV/dec G OFF Short-channel effect control feasible down to 20 nm S D May tolerate a thicker gate oxide for the same channel length G Channels at the surface • Gate workfunction tuning needed for Vt control (for undoped channel) • Steep lateral source/drain doping profile is required G • Parasitic source resistance S D ON Source/drain fan-out and contact - an integral part of the device structure G

Channel length (nm) araswat tanford University 11 Saraswat - EE311/Future Devices

Effect of Extrinsic Resistance on Double Gate FETs

R R s d

α Id = K⋅(Vg–Vth–IdRs)

• Ultrathin body ⇒ higher series resistance • More severe effect in Double-Gate FET

– Twice Id ﬂows through same Rs ⇒ higher series drop

• Degradation in ION • Need to reduce parasitic resistance

Shenoy and Saraswat, IEEE Trans. Nanotechnology, Dec. 2003 araswat tanford University 12 Saraswat - EE311/Future Devices

6 Effect of Extrinsic Resistance on Double Gate MOSFETs

SCE Series Resistance

1.E+21 GATE 1.E+20

1.E+19

1.E+18 (cm-3)

1.E+17 Doping Doping 1.E+16 gradient 5nm/dec Net 1.E+15 4nm/dec 3nm/dec 1.E+14 2nm/dec 1nm/dec 0.5nm/dec 1.E+13 40 45 50 55 60 65 x (nm)

• Extrinsic resistance reduces gate overdrive ⇒ performance limiter in ballistic FETs • Doping profile too gradual: ⇒ dopants spill into channel ⇒ worse SCE • Doping profile too abrupt: ⇒ large series resistance in extension tip • Extrinsic (S/D) resistance may limit performance in future ultrathin body DGFETs araswat Shenoy and Saraswat, IEEE Trans. Nanotechnology, Dec. 2003 tanford University 13 Saraswat - EE311/Future Devices

Non Planar MOSFETs

Vertical FET Double Gate FinFET Tri Gate FET Gate Channel

Source Drain

SiO2

Gate Drain Source

Stanford, AT&T UC Berkeley Intel araswat tanford University 14 Saraswat - EE311/Future Devices

7 Why Germanium MOS Transistors?

Electronic Properties: • More symmetric and higher carrier mobilities (low-field) ⇒ More efficient source injection Ge (due to lighter m*) ⇒ ↓ CMOS gate delay

• Smaller energy bandgap Si ⇒ Survives VDD scaling ⇒ ↓ R with ↓ barrier height • Lower temperature

processing (Sze, Phys. of Semicond. Devs. 2nd Ed., p.46, ⇒ 3-D compatible 1981) araswat tanford University 15 Saraswat - EE311/Future Devices

CMOS Performance Boost with Ge

Drive Current & Gate Delay: MOSFET Channel Energy Band: W ION = !Qinv !vinj 1 T L gate 1-T CLOADVDD Lgate !VDD = kBT/q I D (VDD "VT )!vinj

Ballistic Ratio Comparisons: S D (from Monte Carlo simulations) Si Ge Ge l <100> <100> <111> (Lundstrom et al., 2001, Purdue) n-MOS 0.68 0.78 0.76 p-MOS 0.48 0.70 0.56 araswat tanford University 16 Saraswat - EE311/Future Devices

8 Problems With Ge

Problems #1: Ge Surface Passivation . The native oxide passivation on Ge surface is not stable enough either during fabrication or in the end-product Solution: . High-κ dielectrics are deposited on Si, why not on Ge? Problem #2: Ge Wafers as a Substrate? . Ge substrate not easy to handle and not easily available . Si will continue to be the main substrate due to its overall excellent properties Solution: . Heterogeneous integration of Ge on Si.

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Heteroepitaxial Growth of Ge on Si Ge as deposited Ge after H2 anneal H2 Si

Rrms :2.5nm AFM Z = 50nm/div, X= 2µm/div

Rrms : 25 nm

° As Grown at 400°C No H2 Anneal 400°C Growth + 825 C H2 Anneal

Ge TEM Crystalline Ge Defects Si Si

With H2 anneal dislocations are confined to the Si/Ge

araswat interface leaving defect free top Ge layers. tanford University 18 Saraswat - EE311/Future Devices

9 High Mobility Ge FETs with High-k

Gate Leakage HR-XTEM ) Mobili ty 2 400 m c

/ 25 µm Ge hi-! pFET

/V-s) A 30 m Ge hi- pFET 2 µ ! (

V 300 100 µm Ge hi-! pFET 1 + B F V

HfO2 200 @

t Si Universal

GeOxNy n Mobility e r

r 100 Ge u C Si hi-! pFET 4 nm e t 0 a

Effective Mobility (cm 0.2 0.3 0.4 0.5 0.6 G Effective Field (MV/cm) Equivalent SiO2 Thickness (nm) Key Results

• Passivation of Ge with GeOxNy, ZrO2 and HfO2 • n and p dopant incorporation • 1st demo of Ge MOSFETs with metal gate and hi-κ • p-MOSFET with 3× mobility vs. Hi-k Si • n-MOSFET demonstrated but mobility low

Chui, Kim, McIntyre and Saraswat, IEDM 2003 araswat tanford University 19 Saraswat - EE311/Future Devices

Ge nanowires synthesized by low temperature CVD Au nano Cold-Wall NW Growth Reactor particle

nanowire

• Vapor-Liquid Solid (VLS) mechanism Substrate uses super saturated liquid eutectic to locally deposit Si. Nanowire Au • Growth mechanism: wires grow as GeH = Ge + 2H the catalytic end moves 4 2 SiH4 = Si + 2H2 • Size of the wire is decides by the size of the nano particle Nanowire • 10-20 nm single crystal Ge wires Au • CVD temperature: 275 - 400°C araswat tanford University 20 Saraswat - EE311/Future Devices

10 Ge Nanowire Growth

TEM SEM

. No control over the overall growth direction . Individual wires are single crystal and grow along <110> direction Courtesy: Hongjie Dai araswat tanford University 21 Saraswat - EE311/Future Devices

Ge Nanowire FET with High K gate dielectric

Ge NW MOSFET Top view SEM metal dielectric ~C2h0annmnel semiconductor

SiO2 Source ~10nm

drain Drain gate source

ALD HfO2 Coating of Ge NW

• 10-20 nm single crystal Ge wires • CVD temperature: 275 °C • Initial fabricated transistor shows

great promise µp ~ 500 • 3D integrable technology Key Challenge: Controlled growth

Ref: Wang, Wang, Javey, Tu, Dai, Kim, McIntyre, Krishnamohan, and Saraswat, Appl Phys. Lett, 22 Sept. 2003 araswat tanford University 22 Saraswat - EE311/Future Devices

11 Center Channel Double/Surround Gate FET Conventional DG Depletion-Mode DG Schred: 1-D Poisson-Schrodinger simulations Depletion regions G G E-field S D OFF S D Zero E-field G G

Channels at the surface Channel in the center

G G Charge density S D ON S D G G Transport: Electrostatics: • Zero E-field by symmetry of DG • Excellent control of short channel effects due to DG structure structure • Excellent sub-threshold slope • Reduced scattering due to perpendicular • Very low DIBL and V roll-off E-field th High performance devices: • Natural fan-out (lower Rparasitic ) Technology integration: • High mobility channels leading to very high drive currents • Easier integration with high-k materials • Very high switching speeds • Fully utilizes excellent transport • Very high cut-off frequencies properties of materials like Ge, SiGe, strained Si etc. • Lower power dissipation araswat Krishnamohan and Saraswat, IEDM 2003 tanford University 23 Saraswat - EE311/Future Devices

Epitaxial Growth of Vertical Nanowires

(111) surface Ge <111> oriented Si NWs on (111) Si SiC coonntatianiinging vaVpaopror

Au Nanoparticle

[111] Si Ge nanNoawniorweire

Yiying Wu et al., Chem. Eur. J., 2002, 8, 1261

Si nanowires grow epitaxially on a (111) Si plane

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12 o i t a rMobility Enhancements in Strained-Si MOSFETs

t n Strained Si channel n+ poly e LTO with high mobility spacer m gate oxide e Strained Si c n+ n+ n NMOS Relaxed Si1-xGex ar 2.0 o t V = 10 mV hc DS Si Ge Graded layer

a 1-x x n 1.8 300 K F

et n

e 1.6 Si Substrate ym e

tc n 1.4 PMOS a

i Measured, J. Welser, et al., r h o n l IEDM 1994. t 2.6 Calculation by c E 1.2 i a

y Oberhuber et al. t i F

bl 2.4

Calculated for strained Si t Rim, et al. ob 1.0 n o MOS inversion layer 2.2 M e Currie and

M S. Takagi, et al., J. Appl. Phys. 80, 1996. 0.80 m Leitz, et al.

e 2.0 0.0 0.10 0.20 0.30 0.40 c

Substrate Ge fraction, x n 1.8 a h

n 1.6 E

For substrate Gefraction x < 30%

y 1.4 t i

NMOS I enhanced ~ 1.5X and l • dsat i

b 1.2 • PMOS Idsat enhanced only ~ 1.15X o Mobility

M 1.0 0 10 20 30 40 50 Substrate Ge Content (%) araswat Gibbons Group, Stanford Enhancement tanford University 25 Saraswat - EE311/Future Devices Factor

Enhanced Hole mobility for Uniaxial Strained-Si

(Si3N4)

Simpliﬁed hole valance band structure for longitudinal Hole mobility for uniaxial strained-Si in-plane direction. (a) Unstrained and (b) strained-Si. introduced by Si1-xGex in the source/drain.

araswat S. Thompson, et al. IEEE EDL, April 2004 tanford University 26 Saraswat - EE311/Future Devices

13 Center Channel Double Gate Heterostructure FET Krishnamohan and Saraswat

PMOS Elwomis: Full-Band Monte-Carlo Simulations

Depletion-Mode DG

Depletion regions

G OFF S D G Hole ψ

Channel in the center NMOS Electron G ψ

ON S D G

Higher drive current Higher cut-off frequency

• Carriers in the center of an un-doped strained-Si or SixGe1-x channel araswat • high mobility also due to zero E field, strain, low surface scattering tanford University 27 Saraswat - EE311/Future Devices

Two kinds of transistors Junction S/D MOSFET Schottky S/D MOSFET

Possible advantages of Schottky S/D MOSFET • Better utilization of the metal/semiconductor interface Possible option to overcome the higher parasitic resistance • Modulation of the source barrier by the gate High Vg ⇒ barrier thin ⇒ tunneling current ⇑ ⇒ ION ⇑ Low Vg ⇒ barrier thick ⇒ tunneling current ⇓ ⇒ IOFF ⇓ • Better immunity from short channel effects Possible Disadvantage • ION reduction due to the Schottky barrier araswat tanford University 28 Saraswat - EE311/Future Devices

14 PN Junction vs. Schottky S/D Si DGFET Simulations

PN Junction S/D ION vs. IOFF

Schottky S/D

Low barrier height metal/semiconductor contacts required to achieve high ION and low IOFF

R. Shenoy, PhD Thesis, 2004 araswat tanford University 29 Saraswat - EE311/Future Devices

Schottky Barrier MOSFET

Band diagrams (Schottky barrier FET) Bias 0.5 source Off-state 0 Vds=1.5V Vgs=0V -0.5

-1

Silicide Si -1.5 drain BOX Energy (eV) -2 On-state -2.5 Vds=1.5V Vgs=1.5V -3 0 0.005 0.01 0.015 0.02 0.025 0.03 x (microns) Possible advantages • Better utilization of the metal/semiconductor interface Possible option to overcome the higher parasitic resistance • Modulation of the source barrier by the gate High Vg ⇒ barrier thin ⇒ tunneling current ⇑ ⇒ ION ⇑ Low Vg ⇒ barrier thick ⇒ tunneling current ⇓ ⇒ IOFF ⇓ • Better immunity from short channel effects •Disadvantage • Tradeoff between short channel effect vs. ION reduction due to the Schottky barrier araswat tanford University 30 Saraswat - EE311/Future Devices

15 Optimal φB Schottky Barrier MOSFET

Lg~20 nm FETs with Complementary Schottky Barrier Silicides PtSi PMOS, ErSi NMOS

Source ErSi Silicide Si 2 BOX Tilted Lg + Spacers =27nm

Gate + N poly, ErSi2 W=25nm

PtSi PMOS ErSi NMOS Lg 20 nm 15 nm Tox 4 nm 4 nm Vg-Vt 1.2 V 1.2 V Ion 270 uA/um 190 uA/um 1E-3 |Vsd| f rom 0.2V to 1.4V Swing 100 mV/dec 150 mV/dec 1E-4 in steps of 0.4V

Ion/Ioff 5E5 1E4 1E-5 )

Vt -0.7 V -0.1 V m

µ 1E-6 / A (

d 1E-7 I | PMOS NMOS • Metal S/D reduce extrinsic resistance 1E-8 T = 4nm T = 4nm ox ox • Need ultrathin channel, double gate L = 20nm L = 15nm 1E-9 g g • Need low barrier technology to ensure high I on 1E-10 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 V (V) J. Boker et al.- UCB g araswat tanford University 31 Saraswat - EE311/Future Devices

Variation of the Schottky barrier S factor

1 S = 2 1+ 0.1("# $1)

ε∞

Yeo, King, and Hu, J. Appl. Phys., 15 Dec. 2002 Ref: Robertson, MRS March 2005

. High K’s are less ‘Schottky-like’ than SiO2. Barrier heights change less than metal workfunction. . Strong pinning for semiconductors

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16 Combining New Device Structures with New Materials

We will be here with these innovations

We are here today

•With better injection and transport we may be able to reach closer to the ballistic Ion •With better electrostatics we may be able to minimize Ioff araswat tanford University 33 Saraswat - EE311/Future Devices

Seemingly Useful Devices

Limited Current Drive Limited Fan-Out Cryogenic operation Critical dimension control Challenging fabrication and process integration

+ = ~ 2 nm

Spintronics Carbon Need high spin injection Nanotubes and long spin coherence time Limited thermal stability Controlled growth New architectures needed araswat tanford University 34 Saraswat - EE311/Future Devices

17 Motivation for Organic FETs 25 µm Low-Cost, Flexible Electronics

Philips

Plastic Logic

Penn State / Sarnoff 30 µm Siemens

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Organic Semiconductors

LSI Applications (864 Transistors) • identification tags • low-end data storage B. Crone, A. Dodabalapur et al. Nature 403, 521 (2000) • smart cards • emissive displays All-Printed • electronic paper Polymer Circuit • distributed computing Z. Bao / Bell Labs • toys, clothes, ...

low-cost, lightweight, rugged, flexible electronics

No competition to Si, Going where Si can‘t follow !!

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18 Next Step : ‘Molecular Electronics

Nanotube Devices / Circuits Molecular Switches (Stanford, IBM, ...) (HP, Cal Tech, Stanford ...)

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Nano-Patterning Self-Assembly

Molecular Materials

Molecular Electronics

Molecular-Scale Three-Terminal Devices ? araswat tanford University 38 Saraswat - EE311/Future Devices

19 Organic Insulator / Semiconductor Monolayer (σ − π SAM)

J. Collet et al., APL 76, 1339 (2000). araswat tanford University 39 Saraswat - EE311/Future Devices

Self-Assembled Monolayer Molecular FET

Molecular FETs Molecular Relays

•Molecular Length Defines Channel

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20 Molecular Electronics Interfaced with Silicon Technology Demultiplexers Molecular Switch Order (n) wires (large pitch) To gain element or logic circuit MS

multiplexer

Crosspoint molecular electronic memory: 2n bits (20 – 30 nm pitch)

• Molecular mechanical complexes as solid-state switch elements • Non-traditional patterning techniques to achieve a memory bit (cross-point) density of >1011/cm2. • Non-linear, voltage response of molecular switches to latch (amplify) and clock signals by coupling a large molecular circuit with very few CMOS-type amplifiers.

araswat Source: Nicholas Melosh and J. Heath tanford University 41 Saraswat - EE311/Future Devices

Graphene band structure

“left-handed” “right-handed” E conduction

K1 K2 EF valence

k Two cones in unit cell || k! Symmetry K1 = -K2 araswat tanford University 42 Saraswat - EE311/Future Devices

21 Diversity of SWNTs

(10,10) Arm-chair (18,0) Zig-zag Metal Small gap Quasi-metal

Chiral angle: M, S, or Quasi-M

Diameter: band gap ~ 1/d (7,12) (0.6 eV for d=1.4 nm) Chiral Semiconductor (0.84 eV for d=1 nm)

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Nanotube Band Structure E E 0 0 Egap

Eg ≈ 0.8/d (nm) eV) k|| k||

k! k! semiconducting metal small bandgap large bandgap semiconducting semiconducting 0.15 ) ) 1.0 h h 0.15 ) / / h 2 2 / e e 2 ( (

(

G G G 0 0 0 -10 0 10 -4 0 4 -10 0 10 V (V) Vgate (V) Vgate (V) gate Due to curvature, strain, etc. araswat McEuen et al., IEEE Trans. Nanotech., 1 , 78, 2002. tanford University 44 Saraswat - EE311/Future Devices

22 Band Gap vs. Diameter

(3) (3) m-n ≠ 3 · integer semiconductor

Eg ~ 1/R

araswat C. Kane, G. Mele, Phys. Rev. Lett. 78 1932 (1997) tanford University 45 Saraswat - EE311/Future Devices

Ballistic Nanotube Transistors Growth MOS Transistor Nanotube

Gate

HfO2 D S

10 nm SiO2

CnHm C H p++ Si Fe n m

Catalyst Support 0.2 V 10-5 -5 -0.1 V -6 A)

) 10 ) µ A -10-(

A µ Dai (Stanford) (A) -7 L ~ 50 nm µ ( 10 -0.4 V DS ( I McIntyre (Stanford) S DS S D -I -15- I -8 D

Gordon (Harvard) I 10 -0.7 V Lundstrom (Purdue) L ~ 50 nm VDS = -0.1,-0.2,-0.3 V -20 10-9 -1.0 V -1.3 V -25 -1.5 -1.0 -0.5 0.0 0.5 -0.4 -0.3 -0.2 -0.1 0.0 VG (V) VDS (V) Key Challenge: Low thermal budget controlled growth araswat tanford University 46 Saraswat - EE311/Future Devices

23 High Performance CNT -6 V =0.5 V N-MOSFETs 10 ds S~80 (A) -8 mV/dec ds D 1I 0 S~70 mV/dec

-10 G 10 d~1.6 nm S CNT -1 0 1 K+ K+ G Vgs (V)

HfO2 n-FET Pd Pd 10 p-FET n+ i n+ Moderate 8 S/D doping

500 nm SiO2 A) µ

6 ( ds I p+ Si 4 2 Dai/Gordon/Guo Groups 0 araswat -0.4 -0.2 0.0 0.2 0.4 V (V) tanford University 47 ds Saraswat - EE311/Future Devices

Ambipolar Schottky S/D Nanotube FETs

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24 Conventional MOS Like Nanotube FETs

MOS

Dai group, Stanford araswat tanford University 49 Saraswat - EE311/Future Devices

Theoretical Limits to Scaling

 Thermodynamic limit:

Eb ≥ kB.T.ln2 Emin  Quantum mechanics Eb ∆x . ∆p ≥ h  xmin (Integration density) ∆E . ∆t ≥ h  (witiching speed) τ xmin

 Ultimate limit: 3 3 • xmin ~ 1.5 nm  5.10 transistors/cm

• Switching speed tmin ~ 0.04 ps  25 Tbits/sec

• Switching energy Ebit = 17 meV • Power = 55 nW/bit  For densely packed, 100% duty cycle devices nmax E bit • Total power density = 4.106 W/cm2 P =  With duty cycle ~1 %, Active transistors ~1 % tmin • Total power density = 370 W/cm2

Source: George Bourianoff, Intel araswat tanford University 50 ! Saraswat - EE311/Future Devices

25 Spin Based Switch Jim Harris et al. (Stanford) Charge Spin -2 -8 ΔEb(e-) ~1.7x10 eV ΔE(spin) ~8.6x10 eV B a E b + =

a Eb

w w

ΔE(spin) << ΔE(e-) Single spin state can be detected by After Mark Bohr, (Intel) measuring if there is any tunneling current. araswat tanford University 51 Saraswat - EE311/Future Devices

New materials

Ge SiGe Semiconductors

Ta2O5 HfO 2 High-k ZrO2 dielectrics

Air ZrSixOy PtSi2 Low-k RuO WSi HSQ dielectrics 2 Si N 2 Electrode 3 4 Polymer Pt materials CoSi2 Poly Si Silicides IrO Al TiN 2 Al TiSi2 Y1 SiO SiO MoSi TaN 2 2 2 Metals Cu PZT Ferroelectrics Si Si TaSi2 W BST

1950 1970 1980 1990 2000 2010

(S. Sze, Based on invited talk at Stanford Univ., Aug. 1999) Moore’s Law increasingly relies on material innovations araswat tanford University 52 Saraswat - EE311/Future Devices

26 Conclusion: Technology Progression (After P. Wong) Bulk CMOS Wafer bonding 3D ICs Crystallization Nanowires FD SOI CMOS Strained Si Cu interconnect Optical interconnect Si Low-k ILD (tensile) Si0.8Ge0.2

Si1-xGex Nanotechnology

Double-Gate CMOS Detectors, lasers, High k gate dielectric Gate modulators, waveguides

Metal gate Single e Source Drain transistor Ge/Si Heterostrcture Nanowire Nanotube Ge on Si hetroepitaxy Self- Molecular device Ge on Insulator assembly Interconnects B and contacts + = for nanodevices Spin device Feature Size (Time) 100 nm 2 nm araswat tanford University 53 Saraswat - EE311/Future Devices