sign in sign up
<<
Home , MOSFET

International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-9 Issue-6, April 2020 The Effect of on Different FET Structures: MOSFET, TFET and FinFET

Anjali Goel, Neelam Rup Prakash

Abstract: MOSFET have been scaled down over the past few The VTFET are alike to conventional TFET in respect of years in order to give rise to high circuit density and increase the flow of carriers but VTFET overcomes the shortcomings of speed of circuit. But scaling of MOSFET leads to issues such as conventional TFET. The VTFET has sharper subthreshold poor control gate over the current which depends on gate slope (SS) which is disadvantageous in conventional TFET. voltage. Many short channel effects (SCE) influence the circuit The sharper SS leads to decrease in OFF current and also performance and leads to the indeterminist response of drain current. These effects can be decreased by gate excitation or by enhances performance of low power electronic devices [7- using multiple gates and by offering better control gate the 8]. FinFET overcomes the drawback of SCEs by having device parameters. In Single gate MOSFET, gate higher dominance of gate over channel. Along with that decreases but multigate MOSFET or FinFET provides better when compared to TFET, it has improved ON/OFF control over drain current. In this paper, different FET property. FinFET also has reduced , minor structures such as MOSFET, TFET and FINFET are designed erraticism, and exceptional electrostatic command over at 22nm channel length and effect of doping had been evaluated channel and decreased power consumption. For high- and studied. To evaluate the performance donor concentration is performance application, FinFET is preferred over TFETs kept constant and acceptor concentration is varied. [9]. The rest of paper is organized as follows: Section II Keywords: Doping, FinFET , gate voltage, MOSFET, TFET andsummarizes the previously reported FET structure and their threshold voltage. shortcomings. Section III explains the FinFET and TFET devices structures and Section IV explains the Design I. INTRODUCTION: Considerations of TFET and FinFET fabrications. Section V In modern day integrated circuits, MOS have explains the device structure and simulation. Finally section gained popularity over conventional transistors because of VI highlights the summary of the paper. its properties like low power consumption, high speed and high input impedance. Moore’s Law led to extensive II. II PREVIOUSLY REPORTED FET research in downscaling of parameters. STRUCTURES Downscaling of transistors parameters had led to increase in The International Technology Roadmap for operating speed, low power consumption and reduction in (ITRS) is a manuscript that described the inventions in the die area of prevailing integrated circuits. To cope up with field of IC technology over the past 20 years. The main this law, the channel length of has been lowered objective was to assist the industry to endure productivity gradually in past few decades [1]. However, lowering of and evolution of Moore’s Law. ITRS reflects the headway channel length beyond a certain level leads to degraded generation of IC technology, offers the communal reference performance of MOS transistors. Performance degradation for the industry. The objectives achieved in occurs due to effects like Drain Induced Barrier Lowering the Roadmap were required to be authenticated but bellicose (DIBL), Gate Induced Drain Lowering (GIDL), at same time [10]. Figure 1 illustrates the downscaling of subthreshold leakage and enormous parameter variations. feature size of transistors with time. It can be seen that These effects are known as short channel effects (SCE) [2, reduction is exponential with time. Although, the present- 3]. Scaling of MOSFET leads to decrease in threshold day technology permits solid matter to be fashioned at voltage (Vth) thereby causing escalation of leakage current. various levels like molecular and atomic. Thereby, the These SCEs restrict the downscaling of MOS device beyond and usage of Nano-Scale devices had become a certain level without tolerable degradation in its realistic [11]. performance [4]. To elucidate these problems, various device structures and working mechanisms had been proposed, one of which, that gained much attention is TFET (Tunnel Field Effect Transistor). In TFET the carriers tunnel from source to channel via quantum mechanical tunneling whereas in MOSFET charge injection takes place through thermionic emission [5-6]. The conventional TFET concentrates only on dc transfer characteristics at device level particularly during the increase in the number of interconnect parasitics in the device as equated to gate parasitics.

Revised Manuscript Received on April 1, 2020. Anjali Goel, Student, Dept. of and Communication, Punjab Figure 1: Feature Size of Transistor as a function of time Engineering College, Chandigarh, Chandigarh (Deemed to be University) [11] Neelam Rup Prakash, Professor, Dept. of Electronics and Communication, Punjab Engineering College, Chandigarh, (Deemed to be University)

Published By: Retrieval Number: F4051049620/2020©BEIESP Blue Eyes Intelligence Engineering DOI: 10.35940/ijitee.F4051.049620 972 & Sciences Publication

The Effect of Doping on Different FET Structures: MOSFET, TFET and FinFET

These roadmaps were anticipated to increase innovations appellation. The width of the fin outlines the effective within the industries. The reduction in the size of MOSFET channel of the device. It can regulate the channel from all led to intensification of the operating speed, packaging the sides of the gate. Due to the ability to regulate the density and functionality of IC’s. The gradual reduction of channel from all the side of the gate it overcomes all the device size results in SCE’s, enlarged subthreshold leakage minuses of SCE’s. It has reduced leakage, exceptional current and threshold voltage reduction as an outcome of subthreshold ascent, rapid speed of exchange and lesser adjacent immediacy between source and drain. Along with power consumption [15]. Figure 3 demonstrates the this, the performance of device also lessens due to rise in improvement in SCE’s accomplishment of FinFET in power consumption. Static power and dynamic power are contrast to planar MOS structure. two modes of power consumption appears in IC’s [12]. As the size of the device further reduces, the temperature independent current mechanism is required which lacks in MOSFET. In MOS transistors, when there is change in gate voltage to change drain current while operating in subthreshold region, it is depicted by the following expression:

= 60mV/decade at T=300K……..(1)

To keep the overdrive voltage high at reduced channel length, it was essential to lower the value of Vdd and Vt. Therefore, to overcome the drawbacks of MOSFET, the TFET was exploited. TFETs can achieve the lower value of subthreshold swing than MOSFET [13]. The prime difference between them was their working mechanism. In MOSFET, charge carriers move from source to drain via thermionic emission whereas, in TFET, movement of Figure 3: Variations of SCE’s w.r.t channel length [16] carriers is based on the band to band tunneling (BTBT) The conventional MOSFETs when operating at reduced phenomena. Figure 2 shows the divergence in the transfer channel has various drawbacks in terms of its performance characteristics of MOSFET and TFET. It has been witnessed in low power applications, leakage currents, SCE such as that, TFET’s were not limited by thermal Boltzmann DIBL, GIDL and speed issues that had led to degradation of extremity of carriers because of its BTBT phenomena and MOSFET. In order to maintain the constant electric fields possess the capability of delivering subthreshold-swing while reducing the MOSFET dimensions channel length and below 60mV/decade at room temperature. It was also thickness had been scaled by 1/K and doping was inferred that in TFET the OFF current and operating voltage increased by factor K. This scaling of dimensions result in decreases because of drop in SS in the subthreshold region. scaling of applied voltage by 1/K factor. This type of scaling was termed as R. Dennard Scaling [17]. But R.Dennard scaling was not applicable for non-planar devices because gate overdrive changes due to variations in supply voltage and threshold voltage. Since threshold voltage is proportional to channel length. The shortcomings of conventional MOSFETs led to the development of TFETs. TFETs were proven to be useful for low power applications. /Ioff current ratio is high for TFET and they possess low subthreshold leakage current which led to less leakage per device. For scaled TFET device, gate overdrive increases leads to increase ON current. Prior experiments on TFET, demonstrates that for 50 nm , on current was of the order of 0.5-0.7 mA and off current of the order of 10 pA [18,19]. Additional improvement was required to optimize Figure 2: Divergence of Characteristics of MOSFET and the ON state current and prevent ambipolarity as transistor TFET[14] size was decreased. To overcome this FinFET structure was In 2013, ITRS had envisaged that TFET would remain a proposed by Hisomato et. al. in 1989[20]. has research issue till beginning of 2020s before they would be vertical channel known as FIN. The channel length in manufactured and utilized for low power applications [14]. FinFET is related to Fin height characterised as width TFET’s proven to be useful in the field of low power optimization. Therefore, on state current could be increased applications but it has certain disadvantages as well. It by varying Fin height and number of fins [21]. For channel experiences struggle in retaining sudden tunneling junctions length below 10 nm, FinFET power is 50% lower than because of diffusion of dopants [7]. It also has high ON/OFF TFETs. FinFETs were proven better for high performance property. The drawbacks of TFET were overpowered by and low power applications FinFETs because they possess lower ON/OFF property. [9]. FinFET is a tri-gate device whose conducting channel is enfolded by a thin film from which it has received its

Retrieval Number: F4051049620/2020©BEIESP Published By: DOI: 10.35940/ijitee.F4051.049620 Blue Eyes Intelligence Engineering 973 & Sciences Publication International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-9 Issue-6, April 2020

III. III TFET AND FINFET DEVICE because of tunneling effects and also has higher ON/OFF STRUCTURE current ratio [24].

3.1 TFET Device Structure 3.2 FinFET Device Structure:

The basic layout of TFET is analogous to the MOSFET FinFETs are evolving technology in the present scenario. excluding that source and drain terminal are incapacitated They has assorted design choices and improved regulation with reverse type and the most extricate characteristics of over the channel leading to reduced power structures and TFET is nobbling used for drain and source. A communal advanced noise lenience. The FinFET device design TFET device structure comprises of a p-type, intrinsic, n- includes of a silicon fin enclosed by shorted or independent type junction led to formation of p-i-n , inside which gate on any side of the fin usually on silicon insulated the electrostatic potential of the inherent region is regulated substrate. It has two gates which can operate either self- by a gate terminal and it operates in the reverse bias sufficiently or when coupled together. The voltage at one condition. Thermal injection is a process for the source of gate can be regulated by the voltage at another gate. Figure carrier inoculation used in MOSFET whereas TFET 6 illustrates the FinFET in various schemes. operates the BTBT process of . TFET basic structure comprises of three portions (source, drain ). Source terminal is utilized as a cause of majority carrier. Drain terminal is utilized to transmit the majority carrier and Gate terminal is utilized to regulate the majority carrier flowing from source to drain ramblingly regulating the drain current. Channel is molded in-between the p-type and n-type region. is utilized to cloister gate and to allow gate to regulate the electrostatic in the channel and oxide is cloister; gate oxide averts the current leakage from channel to gate. Figure 4 displays the representation of p-i-n TFET [22]. Figure 6: FinFET schemes (a) self –sufficient (independent) gates (b) united (shorted) gate [25]

These devices can be utilized to rise the performance by decreasing the leakage current and power dissipation as front and back gates both can be regulated self-sufficiently or when coupled together [25]. The movement of charge can be enhanced by aggregating the amount of fins on the device which provides improved gate regulation on the channel charge. The fin height is quantifiable factor to describe the stability of the device [20]. The profits of FinFET are that Figure 4: Representation of p-i-n TFET [22] they have less cost, reduced SCE, increased technological adulthood and have abilities of matching [26] These are also known as gated p-i-n . To enable the device, the diode is reverse biased and a voltage is supplied IV. DESIGN CONSIDERATIONS OF TFET AND to the gate. Reverse bias is essential for tunneling effect and FINFET along with that it had been observed that N-MOS functions 4.1 Design Consideration and Optimization of TFETs when positive voltage are given to gate and drain. Thus, n- region of TFET is denoted as its drain and p+ region as its Although, TFETs possess high ON/OFF current ratio but source for n-type device. The TFET’s operates on various key issues needs to be considered while designing of 4.5eV. Figure 5 illustrates the structure of the TFET. p-i-n TFET. 4.1.1 Single and Double gate TFET’s

Conventional TFETs possess low ON/OFF current ratio. In order to offer enhanced electrostatic control over the channel, number of gates in devices had been increased. TFET with double gate or multigate deliver high Ion. Second gate in TFET is created at the bottom of single gate TFETs [27]. Single gate and double gate TFETs are illustrated in figure 7: Figure 5: Structure of p-i-n TFET[23]

It has sharper switching nature, works on BTBT mechanism [23]. It has capability of having subthreshold swing lower than the 60mV/decades, overcomes the problems of SCE’s, minimizes the leakage currents, crosses the speed necessities

Published By: Retrieval Number: F4051049620/2020©BEIESP Blue Eyes Intelligence Engineering DOI: 10.35940/ijitee.F4051.049620 974 & Sciences Publication

The Effect of Doping on Different FET Structures: MOSFET, TFET and FinFET

Figure 7 (a) Single TFETs (b) Double gate TFETs

Double gate(DG) TFETs offers improved Figure 9: Gate on Drain overlap structure [30]. and lessened threshold voltage. By selecting appropriate gate , DG TFET’s can poses low threshold voltage 4.2 FinFET Design Challenges roll-off, high Ion and reduced Ioff as compared to conventional TFETs. The supply voltage of Ge based TFET Various parameters of device technology is influenced by was limited to 0.5 V for circuit level designs [28]. downscaling of device and modification in device architecture. Below are some of the key issues. 4.1.2 Asymmetric Gate Oxide 4.2.1 Fin Pattering Nagpal et al in 2012, observed the performance of asymmetric gate oxide DG TFET with a high-k dielectric at In order to achieve the matched or exceeded width of source region and low-k dielectric at drain of TFET. The FinFET device either their fins needs to be extremely tall or high gate grain of DG TFET is controlled by huge number of fins should be gathered per pitch. Normally, replacing SiO2 with air (k=1) at the drain side resulting in two fins per each base pitch provides a tolerable fin aspect higher cut off frequency. DG-TFET with asymmetric gate ratio that helps to achieve either matched or exceeded width oxide had been reported best for low power applications at as compared to planar device. Lithographic designing of circuit level [29]. Figure 8 shows the DG TFET with such fins has few drawbacks associated with it: asymmetric gate oxide Overlay error may appear between two fins pattern because of double patterning required for splitting the base pitch. This error could lead to undesired fin pitch variations that influences down-steam handling.

If selected fin width is smaller than twice the gate length, it may result in intolerable capabilities of optical lithography leading to poor fin width control [31].

4.2.2 Orientation of Fin

Figure 8: DG TFET with asymmetric gate oxide [29] Current in FinFET drifting along <110> sidewalls is because of alignment of fins in direction <110> on wafers <100>. 4.1.3 Gate on Drain Overlap Along <110> direction, hole mobility is usually higher on <100> wafers but as stress is employed difference between The movement of and hole in opposite direction darin current and hole current decreases. In non-planer can be suppressed with gate-drain overlap in TFET. In device such as FinFET mobility is higher along TFET, even at higher drain doping level (1x1019 cm-3) <110> surface than along <100> sidewalls. For uniform ambipolar conduction can be suppressed. Band bending of thickness if Fin either epitaxial layer can be used or device doesn’t get altered at higher drain doping levels diamond shape structures could be extended on <110> because of gate potential in overlapping regions [30]. Figure sidewalls [32]. 9 depicts the gate on drain overlap structure of DG TFET. 4.2.3 Fin measurement variability

Effective width of FinFET device is directly proportional to fin height. Out of the two parameters, fin height is more crucial. Any modification in fin height and shape is transferred to device width difference. FinFET devices suffer from device width variations whereas in MOS devices, design variations only affect the narrowest of transistors [33].

Retrieval Number: F4051049620/2020©BEIESP Published By: DOI: 10.35940/ijitee.F4051.049620 Blue Eyes Intelligence Engineering 975 & Sciences Publication International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-9 Issue-6, April 2020

4.2.4 FinFET parasitic capacitance properties of TFET. The TFET structure under study is demonstrated in Figure 11 and table 2 dictates the various Parasitic capacitance of FinFET device is usually higher regions of TFET with their meshing size. than planar devices such as MOSFETs. Gate to fin capacitance includes capacitance of gate above the fin and the top of fin. This capacitance reduces with increase in fin height and decrease in fin pitch per effective width of device. Junction capacitance of Bulk FinFET between source/drain area and well/substrate was reported several times lesser than MOS devices [34].

V. V Device Structure and Simulation 5.1 MOSFET Structure

For a given MOSFET structure the Vth can be related to SCE and DIBL by the following equation:

Vth = Vth∞–SCE–DIBL where Vth∞ is the threshold voltage of a long channel device, SCE is short channel effect and DIBL is drain induced barrier limiting. The reduction in threshold voltage along with decrease in gate length is a popular SCE called “threshold voltage roll-off”. The MOSFET realized has gate length equals to 22nm which is formed by diffusing the drain and source. Thickness of gate oxide layer, acts as Figure 11: TFET structure under study insulator is 2 nm and is made up of SiO2.Figure 10 illustrates the MOSFET structure realized at 22nm gate Table 2 Different regions of TFET length and table 1 dictates the different regions of MOSFET Region Material Mesh with their meshing size. Size Source/Drain Al 0.005

Gate NpolySi 0.003

Oxide SiO2 0.004 Substrate Al 0.004 Contact Substrate Silicon 0.005 Spacers Nitride 0.004

5.3 FINFET Structure Figure10: Structure of MOSFET having channel length 22 nm For two-gate FinFET, effective channel length (ECL) is given by Table 1 Different regions of MOSFET ECL= 2H +T Region Material Mesh Size fin fin

Substrate Silicon 0.005 Where Hfin is height of FinFET and Tfin is thickness of FinFET. Two-gate FinFET has both the gates aligned on Soucre/Drain Al 0.001 both faces of the fin fixed by Hfin and a gate increased above which is equal to Tfin. So, the gate length is 22nm and Hfinis Oxide SiO2 0.0005 2nm, so according to calculations Tfin i.e. width of gate is Spacers Nitride 0.001 18nm. The gate insulators are made up of high-k dielectric spacers (sp1,sp2,sp3,sp4). Both the gate Gate Al 0.002 (toxide/boxide) are made up of SiO2 and thickness of gate oxide is 2nm. The structure of FinFET is shown in Figure 12 5.2 TFET Structure

The TFET uses the MOS gate to achieve BTBT .The device is off when zero gate volatge is applied and BTBT is suppressed during that time. The gate length is 22nm and it is made using NPolySi and gate oxide thickness is 4nm. Gate material has significant effect over drain current where as source and drain material doesn’t affect the

Published By: Retrieval Number: F4051049620/2020©BEIESP Blue Eyes Intelligence Engineering DOI: 10.35940/ijitee.F4051.049620 976 & Sciences Publication

The Effect of Doping on Different FET Structures: MOSFET, TFET and FinFET

respectively. Output characteritics curve for finFET is shown in figure 15

Figure 12: FinFET device structure

Table 3 Different regions of FinFET

Region Material Mesh size Substrate Silicon 0.005 Figure15 Output Characteristics ( Id-Vd ) of FinFET Gates(Tgate/Bgate) Al 0.001 5.4.2 Impact of Doping

Oxide SiO2 0.0005 The effect of impurities of source/drain of revered type is Source/Drain Al 0.001 observed by simulating the structure at different doping concentrations. It has been observed that drain current increases as concentration of in channel decreases. Spacers Nitride 0.01 Figure 16 illustrates the MOSFET Id-Vd characteristics at different acceptor concentration while keeping the donor concentration constant at 7e20 cm-3. Drain current is 4.072 -3 Id-Vd characteristcs curve for MOSFET is shown in figure mA for lowest acceptor concentration i.e. 1e16 cm . -3 13. Id-Vd characteristcs curve is obtained at 1e20 cm -3 acceptor concenteration and 1e20 cm and Vg varies from 0.25 V to 1.25 V.

Figure16 MosFET at Different Acceptor Concentration

Id-Vd characteristics of TFET at different acceptor

Figure 13: Output Characteristics (Id-Vd) of MOSFET concentration and distinct donor concentration are demonstrated in Figure 17. It has been observed that drain The Id-Vd charcateristics of TFET is shown in figure 14. current is max at lower acceptor concentration i.e 1e16 cm- 3. The drain current is 4.05 mA at lower acceptor concentration

Figure 14: Output characteristics of TFET

To obtain the output characteristics curve for FinFET gate Figure 17: TFET at Different Acceptor Concentrations voltage is varied between 0.25 to 1.25 V and concentration of donor and acceptor ions is 7e20 cm-3 and 1e16cm-3

Retrieval Number: F4051049620/2020©BEIESP Published By: DOI: 10.35940/ijitee.F4051.049620 Blue Eyes Intelligence Engineering 977 & Sciences Publication International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-9 Issue-6, April 2020

Id-Vd characteristics of FinFET at different acceptor Semiconductors perspective," 6th Int. Conf. on Solid-State and concentration and distinct donor concentration are Technol. Proc., vol. 1, Shanghai, China, 2001, pp. 23-28. demonstrated in figure 18. It has been observed that drain 11. Bhuyan, M., “History and Evolution of CMOS Technology and its current is max at lower acceptor concentration i.e 1e16 cm- Application in ,” SEU J. of Sci. and Eng., vol. 3. 11,pp. 28-42. 12. Cogez, P., Kokshagina, O., Masson, P. and Weil, B., "Industry-wide technology roadmapping in double unknown — The case of the semiconductor industry," Int. Conf. on Eng., Technol. and Innovation (ICE) & IEEE Int. Technol. Manag.t Conf., 2013, pp. 1-13. 13. Kale, S., Kondekar, P.,“Design and investigation of double gate Schottky barrier MOSFET using gate engineering,” IET Micro Nano Lett., vol. 10 , 2015 , pp. 707–711. 14. Bhowmick, B. “Emerging device: FINFET, tunnel FET and their applications,” CSI Trans., vol. 7, 2019, pp. 221–225. 15. Kumar, A., Kaur, B. and Arora, M., “Evolution of Transistor Technology from BJT to FinFET – A study.” Int. J. of App. , 2016 16. Nowak, E.J., et. al.,“Turning silicon on its edge -double gate CMOS/FinFET technology,” IEEE Circuits and Devices Magazine, vol. 20, no. 1, 2004, pp. 20–31. 17. Dennard, R., Gaensslen, F., Yu, H. N., Rideout, V., Bassous, E. and LeBlanc, A., “Design of Ion-Implanted MOSFETs with Very Small Physical Dimensions,” IEEE J. Solid-State Circuits, vol. 9, no. 5, pp. 256-268, 1974. 18. Zhang, Q, “Low-Subthreshold-Swing Tunnel Transistors,” IEEE Figure 18: FinFET at different concentration Electron Device Letters, 2006. 19. Nirschl, T., “The tunneling field effect transistor (TFET) used in a VI. CONCLUSION single-event upset (SEU) insensitive 6 transistor SRAM cell in ultra- low voltage applications,” IEEE Conf. on , 2004. Various FET structures had been discussed and reviewed in 20. Pal,R, Sharma, S. and S. Dasgupta, S., "Recent trend of FinFET paper. The comparative study of conventional MOSFET devices and its challenges: A review," Conference on Emerging Devices and Smart Systems (ICEDSS), 2017, pp. 150-154. structure with TFET and FinFET has been done. In order to 21. B. Rainey, D.M. Fried, M. Leong, J. Kedzierski, E.J. Nowak get better knowledge of recent trends in FET structure, the “Demonstration of FinFET CMOS circuit,” Int. Conf. Digest Device circuit problems, fabrication and challenges had been Research Conf., pp. 47-48, June, 2002. discussed in the paper. In this, various FET structures has 22. Lu, H. and Seabaugh, A.,"Tunnel Field-Effect Transistors: State-of- the-Art," IEEE J. of the Electron Devices Society, vol. 2, no. 4, pp. been compared at different doping concentration at channel 44-49, July 2014. length of 22nm. It is observed that FinFET possesses higher 23. Jossy, M. & Vigneswaran, T.,“A perspective review of tunnel field Ion current and drain current is max at lower acceptor effect transistor with steeper switching behavior and low off current concentration. (IOFF) for ultra low power applications,” Int. J. of Eng. and Technol., vol. 6, pp. 2092-2104. 24. Turkane, S, & Kureshi, A.K., “Review of Tunnel Field Effect REFERENCES Transistor (TFET),” Int. J. of Appl. Eng. Research, vol. 11, 2016 ,pp 4922-4929. 1. Paras, N. and Chauhan, S.,“Insights into the DC, RF/Analog and 25. Kataria, S.and Beniwal, P., “FINFET Technology: A Review paper,” linearity performance of vertical tunneling based TFET for low-power Int. J. of Technical Research., vol.5, no. 2 , 2016, pp 35-36. applications,” Microelectronic Eng., vol. 216, 2019, 111043. 26. Prasad, M. and Mahadevaswamy, U. B., “Comparative Study of 2. Ionescu, A.M., Riel, H., “Tunnel field effect transistors as energy MOSFET, CMOS and FINFET: A Review,” Proc. of Int. Conf. on efficient electronic ,” Nature , vol.479, 2011, pp. 329–337. Current Trends in Eng., Science and Technology, ICCTEST, 2017. 3. Singh, D., Pandey, S., Nigam, K., Dheeraj, S., Yadav, D., Kondekar, 27. Sandow, C., Knoch, J., Urban, C., Zhao, Q. and Mandl S. “Impact of P., “A chargeplasma- based dielectric modulated junctionless TFET and doping concentration on the performance of silicon for label-free detection,”IEEE Transactions Electron Dev., tunnel field-effect transistors,” Solid-State Electronics, 2009. vol. 64, 2017, pp. 271–278. 28. Goel, A., Gupta, S. K.and Roy, K.,“Asymmetric drain spacer 4. Choi, W., Park, B., Lee, J, Liu, T., “Tunneling field-effect transistors extension (ADSE) FinFETs for low power and robust SRAMs,” IEEE (TFETs) with subthreshold swing (SS) less than 60 mV/dec,” IEEE ransactions Electron Dev., vol.58 , 2011, pp. 296–308. Electron Devt., vol. 28, no. 8, 2007, pp. 743–745. 29. Narang, R., Saxena, M., Gupta. R.S. and Gupta, M.,“Asymmetric 5. Zhang, Y. B., Sun, L., Xu. H., and Han, J. W., “Simulation and gate oxide tunnel field effect transistor for improved circuit per- comparative study of tunneling field effect transistors with dopant- formance,” Int. Conf. on Devices, Circuits and Sys., 2012. segregated Schottky source/drain,” Jap. J. of Appl. , vol. 55, 30. Abdi, D.B. and Jagadesh, K. M.,“Controlling ambipolar current in 2016. tunneling FETs using overlapping gate-on-drain,” Journal of the 6. Martino, J.A., Paula, W., Rooyackers, R., Simoen, E. and Claeys, C., Electron Devices Society, vol. 2 ,2014. “Comparison of Current Mirrors Designed with TFET or FinFET 31. Lawrence, B. & Rubia, J., “Review of Fin FET Technology and Devices for Different Dimensions and Temperatures,” ECS Trans., Circuit Design Challenges,” Int. J. of Eng. Research and App., vol. 5, vol. 66, 2015, pp. 303-308. 2015. 7. Yadav, S., Vemulapaty, M., Sharma, D., Gedam, A., and Sharma, N., 32. Colinge, J.P. et al., “ transistors without junctions,” Nat. "Design structure of tunnel FET by combining thermionic emission Nanotechnol., vol. 5, no. , pp. 225–229, Mar. 2010. with tunneling phenomenon," Micro & Nano Letters, vol. 14, no. 4, 33. Bhattacharya, D. and Jha, N. K. “FinFETs: From Devices to pp. 450-454, 2019. Architectures,” Advances in Electronics, vol. 2014, Article ID 8. ‘International Technology Roadmap for semiconductors (ITRS)’. 365689, 21 pages, 2014. 5689. Available at http://www.itrs2.net. 34. J.P Colinge, FinFETs and other Multigate Transistors, Springer, 2008. 9. Sharma, A., Goud, A., and Roy, K., "Sub-10 nm FinFETs and tunnel- FETs: From devices to systems," Design, Automation & Test in Europe Conf. & Exhibition (DATE), 2015, pp. 1443-1448. 10. Zeitzoff, P. M, "Circuit, MOSFET, and front end process integration trends and challenges for the 180 nm and below technology generations: an International Technology Roadmap for

Published By: Retrieval Number: F4051049620/2020©BEIESP Blue Eyes Intelligence Engineering DOI: 10.35940/ijitee.F4051.049620 978 & Sciences Publication

The Effect of Doping on Different FET Structures: MOSFET, TFET and FinFET

AUTHORS PROFILE

Anjali Goel received her B.E degree from Chandigarh College of Engineering and Technology, Chandigarh, in Electronics and Communication in 2018. Currently, she is pursuing her M.E in VLSI –Design from Punjab Engineering College (Deemed to be University), Chandigarh. Her current research includes designing of different FET structures at 22 nm channel length and comparing them by varying the doping concentration.

Neelam Rup Prakash hasa vast experience in both Industry and Academia for nearly 32 years. She has headed the Electronics & Communication Engineering Department at Punjab Engineering College (Deemed to Be University), Chandigarh. She started a new Postgraduate Program in VLSI Design in the Department during her tenure as HOD. Her area of research includes Digital Design, Low Power VLSI Circuit Design, Computer Aided Diagnostics and has a number of publications in journals of repute. She is the Co-coordinator of the Centre of Excellence in Industrial and Product Design. She has guided over 50 MTech and PhD students. She is a member of various forums like IEEE, IETE, etc. She has a number of patents to her credit.

Retrieval Number: F4051049620/2020©BEIESP Published By: DOI: 10.35940/ijitee.F4051.049620 Blue Eyes Intelligence Engineering 979 & Sciences Publication