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AN296216 APPLICATION INFORMATION MCO-0000998 P0079

ESTIMATING MAXIMUM MOSFET SWITCHING FREQUENCY

By Shingo Ehara, Alistair Wood, and Andrea Foletto Allegro MicroSystems, Edinburgh, UK and Milan, Italy

Introduction 1.6 This application note describes how to calculate the maxi- TJ=25°C 1.4 ID=40A mum power MOSFET switching frequency in BLDC motor gate drives. While this application note focuses on Allegro 1.2

three-phase bridge gate drivers with a standard voltage ) 1.0 Ω m regulator plus bootstrap architecture, such as the ( )

n 0.8

Allegro A4910, A4911, A4913, A4916, and A4918, the con- S( o D cept is generally applicable to other circuits. R 0.6

VBAT 0.4

0.2

0.0 5 10 15 20 VGS (V)

Figure 2: RDS(ON) versus VGS Allegro 3 - Phase Control Gate DSP BLDC Driver As can be seen in Figure 2, to achieve low R a V of or DS(ON), GS µC 10 V is typically required, though operation at lower -

Diagnostics ages can be supported with only limited increase of RDS(ON).

Current MOSFET Turn-On/Off Current Requirement Sense If a power MOSFET gate source voltage is quickly raised from near zero to a sufficient value for MOSFET turn-on, Figure 1: Typical Application the resultant current waveform is as shown in Figure 3 as “charge current”. The current into the MOSFET gate rises MOSFET Turn-On Voltage Requirement very quickly and then decays exponentially as the device input charges up. When the gate source voltage is quickly To hold a MOSFET in the off state, the gate is normally held reduced to close to zero, current flows out of the MOSFET at a voltage that is close to that of the source (VGS VTH). gate in a similar manner as shown as “discharge current” in To turn on a standard N-channel MOSFET, it is necessary Figure 3. ≪ to raise the gate voltage to a suitable positive value with When using an Allegro gate driver to turn power respect to the source to generate low RDS(ON). Figure 2 on and off, the peak of each current ‘spike’ can reach 0.5 A shows a representative plot of RDS(ON) versus VGS for a typical or higher. However, the duration of each spike is typically no power MOSFET. more than a few hundred nanoseconds. AN296216 APPLICATION INFORMATION MCO-0000998 P0079

Iav = 6 × 123 nC × 20 kHz = 14.8 mA TPWM=1/fPWM As can be seen from this result, the average current (tens of mA) is typically small compared to the peak gate driver ] ig (Charge current) A [ g

i current delivered on each switching cycle (possibly 0.5 A

Iav (Required average current) or higher). This arises because the duration of each - ing pulse is short compared to the duration of the period t [s] between switching cycles. Note that the average discharge current is equal in magnitude to the average charge current. This is effectively the time aver-

ig (Discharge current) age of all the negative-going charge current pulses in Figure 3.

Figure 3: Example gate charge switching current waveform. MOSFET Switching Speed Control

The charge represented by the area under each spike is In some applications, it may be necessary to limit the rate of change of the voltage at the motor phase connections equivalent to the total gate charge, Qg, of the MOSFET being driven. A representative gate charge versus gate- to help comply with EMC requirements at the expense of source voltage characteristic of a MOSFET is shown in increased MOSFET dissipation. Figure 4 below. The conventional method of achieving this is to add an external between the gate drive output and the gate 10 terminal of each MOSFET. This reduces the peak switching 9 current as shown in Figure 3 to increase the time required to 8 deliver/remove gate charge to/from the MOSFETs and slow 7 switching as required. ) V

( 6

S In addition to operating in this conventional switch mode, G V 5 many of Allegro’s gate drivers can be configured via their 4 serial interface to control gate drive current without an

3 external resistor between the gate drive output and the core-

2 sponding MOSFET gate terminal. For further information, VDS=20V consult Allegro gate driver product datasheets. Note that the 1 TJ=25°C ID=20A average current required to support switching is the same 0 0 10 20 30 40 50 60 70 80 90 100 regardless of whether external or the internal gate QG (nC) drive control mechanism is used. Figure 4: Typical gate charge of MOSFET. Gate Driver Output Current Capability It is possible to calculate the average current that must be When using an Allegro gate driver to switch a three-phase provided to continuously switch a MOSFET on and off at a bridge comprising six N-channel MOSFETs, the MOSFET particular frequency. This is effectively the time average of all gate current is supplied by the VREG output as generated by the positive-going charge current pulses in Figure 3. If the the gate driver regulator. switching frequency is fPWM = 1 / tPWM and the MOSFET gate charge is Qg, then the average charge current, Iav is equal to

Equation 1: Iav = fPWM × Qg If switching multiple MOSFETs, N, per PWM cycle, the aver- age current requirement scales by the number of MOSFETs given.

Equation 2: Iav = N × Qg 〖× fPWM For example, if the following parameter values representative of driving a three-phase BLDC motor are assumed for illustra- Figure 5: regulator tion: N = 6, Qg = 123 nC, fPWM = 10 kHz, then the resultant average current from Equation 2 is: VREG supplies current for the low-side gate-drive circuits and

955 PERIMETER ROAD • MANCHESTER, NH 03103 • USA +1-603-626-2300 • : +1-603-641-5336 • ALLEGROMICRO.COM 2 AN296216 APPLICATION INFORMATION MCO-0000998 P0079

the charging current for the bootstrap . When a maximum required PWM frequency is 20 kHz, the selected low-side MOSFET is turned on, the gate drive circuit will pro- bridge MOSFETs each have a total gate , Qg, of vide the high transient current to the gate that is necessary 200 nC(max) at VGS = 10 V, and that sinusoidal drive is being to turn the MOSFET on quickly. This current, which can be used (N = 6). The average current that must be provided by several hundred milliamperes, cannot be provided directly the regulator can be determined directly from Equation 2: by the limited output of the VREG regulator but must be sup- Iav = N × Qg 〖× f〗PWM plied by an external capacitor, CREG, connected between the VREG terminal and GND. Iav = 6 × 200 nC × 20 kHz The turn-on current for the high-side MOSFET is similar in = 24 mA value but is mainly supplied by the bootstrap capacitor. How- By inspection of Figure 6, it can be seen that the regula- ever, the bootstrap capacitor must then be recharged from tor will maintain a minimum VREG of 7.9 V with a VBB supply CREG through the VREG terminal. Unfortunately, the boot- voltage down to 6 V while supporting a load current IVREG [1] strap recharge can occur a very short time after the low-side of up to 50 mA. If a minimum VREG of 7.9 V is acceptable , turn-on occurs. This means that the value of CREG between then the gate driver in question will support switching of the VREG and GND should be high enough to minimize the tran- proposed MOSFETs at the specified frequency. sient voltage drop on VREG for the combination of a low-side In practice, this calculation can be considered conserva- MOSFET turn-on and a bootstrap capacitor recharge. tive for two reasons. First, the limit value of VREG read from For block commutation control (trapezoidal drive) where only Figure 6 assumes a load current, IVREG of 50 mA. As the one high side and one low side are switching during each estimated current requirement from Equation 2 is actually PWM period, a minimum value of 20 × CBOOT is reasonable. 24 mA, the minimum VREG will be higher than the stated For sinusoidal control schemes, a minimum value of 40 × value of 7.9 V. Second, as the value of VREG may be less than CBOOT is recommended. As the maximum working voltage 10 V, the actual gate charge required to turn on the selected of CREG will never exceed VREG, the capacitor voltage rating MOSFET type may be less than the specified figure of can be as low as 15 V. However, it is recommended that a 200 nC. This would lead to a value of average current of less capacitor rated to at least twice the maximum working volt- than 24 mA from Equation 2. age should be used to reduce any impact operating voltage Characteristic Symbol Test Conditions Min. Typ. Max. Unit may have on capacitance value. For best performance, CREG VBB > 9 V, IVREG = 0 to 50 mA 9 11 11.7 V should be ceramic rather than electrolytic. CREG should be VREG Output 7.5 V < VBB ≤ 9 V, IVREG = 0 to 50 mA 9 11 11.7 V V mounted as close to the VREG terminal as possible. Voltage, VRG = 1 REG 6 V < VBB ≤ 7.5 V, IVREG = 0 to 50 mA 7.9 11 11.7 V

For the gate driver, the continuous current that this charge 4.5 V < VBB ≤ 6 V, IVREG < 15 mA 7.5 8 11.7 V pump is able to produce is detailed in the Electrical Charac- teristics section of the relevant product datasheet. Figure 6: Example VREG Output Voltage Specification (A4918) Example 1 Example 2 It is sometimes the case that system designers are required It is sometimes the case that system designers are required to to determine if a particular gate driver IC can support the estimate the maximum possible three-phase bridge switch- switching of a three-phase bridge comprising MOSFETs of ing frequency when running from a particular minimum a particular type at a specified PWM frequency. This can be supply voltage. translated into determining if the VREG regulator of the gate For example, assume that the system minimum VBB is 9 V, driver in question (see Gate Driver Output Current Capability the regulator has the VREG output capability shown in the section) can provide sufficient continuous current to supply datasheet extract in Figure 6, the selected bridge MOSFETs the average current requirement for bridge switching (see each have a Qg of 200 nC(max) at VGS = 10 V, and that sinu- MOSFET Turn-On/Off Current Requirement section) while soidal drive is being used (N = 6). By inspection of Figure 6, maintaining a sufficient value of VREG at the system minimum it can be seen that the regulator will maintain a minimum VBB. [1] VREG of 9 V with a load current of up to 50 mA. By rearrang- For example, assume that the system minimum VBB is 6 V, the ing Equation 2, maximum switching frequency can then be

[1] Note that voltage drops due to bootstrap driver output stage drops should be accounted for when determining the acceptability of mini- mum VREG.

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estimated as:

fPWM(max) = Iav / (N × Qg) = 50 mA / (6 × 200 nC) = 41 kHz In practice, this calculation can be considered conservative as the MOSFET Qg is specified at VGS = 10 V, whereas the regulator is only guaranteed to maintain VREG at 9 V. Conse- quently in the limiting case the gate charge delivered to turn on each MOSFET will actually be 9/10 × 200 nC = 180 nC and the estimated maximum switching frequency will be 46 kHz. Summary The relationship between gate driver capability and MOSFET switching has been outlined. This may be used to determine if a particular gate driver IC can switch a given MOSFET type at a required PWM frequency (Example 1). Alternatively, it may be used to determine the maximum achievable PWM frequency for a given gate driver supply voltage and MOSFET type (Example 2).

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Revision History Number Date Description Responsibility S. Ehara, A. Wood, – November 19, 2020 Initial release A. Foletto

Copyright 2020, Allegro MicroSystems. The information contained in this document does not constitute any representation, warranty, assurance, guaranty, or induce- ment by Allegro to the customer with respect to the subject matter of this document. The information being provided does not guarantee that a process based on this information will be reliable, or that Allegro has explored all of the possible failure modes. It is the customer’s responsibility to do sufficient qualification testing of the final product to insure that it is reliable and meets all design requirements. Copies of this document are considered uncontrolled documents.

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