Topics MOSFET Gate as Capacitor
! Derivation of transistor characteristics. ! Basic structure of gate is parallel-plate capacitor:
gate + xox Vg SiO2 - substrate
Slides courtesy Modern VLSI Design, 3rd Edition Slides courtesy Modern VLSI Design, 3rd Edition
Parallel Plate Capacitance Threshold Voltage
! Formula for parallel plate capacitance: Components of threshold voltage Vt: C = ε /x ox ox ox ! Vfb = flatband voltage; depends on difference in work ! Permittivity of silicon: function between gate and substrate and on fixed surface ε -13 2 ox = 3.46 x 10 F/cm charge. φ φ ! Gate capacitance helps determine charge in channel which ! s = surface potential (about 2 f). forms inversion region. ! Voltage on parallel plate capacitor.
! Additional ion implantation.
Slides courtesy Modern VLSI Design, 3rd Edition Slides courtesy Modern VLSI Design, 3rd Edition
Example: Threshold Voltage of a Body Effect Transistor
φ ! Reorganize threshold voltage equation: Vt0 =Vfb + s +Qb/Cox + VII ∆ Vt = Vt0 + Vt = -0.91 V + 0.58 V + (1.4E-8/1.73E-7) + 0.92 V ! Threshold voltage is a function of source/substrate = 0.68 V voltage V . γ ε sb Body effect n =sqrt(2q SiNA/Cox) = 0.1 ! Body effect γ is the coefficienct for the V dependence ∆ γ φ sb Vt = n[sqrt( s +Vsb) - sqrt(Vs)] factor. = 0.16 V
Slides courtesy Modern VLSI Design, 3rd Edition Slides courtesy Modern VLSI Design, 3rd Edition Channel Length Modulation Length More Device Parameters Parameter
µ λ ! Process transconductance k’ = Cox. ! describes small dependence of drain corrent on Vds in ! Device transconductance β =k’W/L. saturation. ! Factor is measured empirically.
! New drain current equation: 2 λ ! Id = 0.5k’ (W/L)(Vgs -Vt) (l - Vds) ! Equation has a discontinuity between linear and saturation regions---small enough to be ignored.
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Gate Voltage and the Channel Leakage and Subthreshold Current
gate ! A variety of leakage currents draw current away from the current source drain main logic path. Vds < Vgs -Vt I d ! The subthreshold current is one particularly important type of leakage current. gate
current source drain Vds = Vgs -Vt
Id
gate
current source drain Vds > Vgs -Vt Id
Slides courtesy Modern VLSI Design, 3rd Edition Slides courtesy Modern VLSI Design, 3rd Edition
Types of Leakage Current. Subthreshold Current
! Weak inversion current (a.k.a. subthreshold current). ! Subthreshold current: [(Vgs - Vt)/(S/ln 10)] -qVds/kT ! Reverse-biased pn junctions. ! Isub=ke [1-e ]
! Drain-induced barrier lowering. ! Subthreshold slope S characterizes weak inversion current. ! Gate-induced drain leakage; ! Subthreshold current is a function of V . ! Punchthrough currents. t ! Can adjust Vt by changing the substrate bias to control leakage. ! Gate oxide tunneling.
! Hot carriers.
Slides courtesy Modern VLSI Design, 3rd Edition Slides courtesy Modern VLSI Design, 3rd Edition The Modern MOSFET Circuit Simulation
Features of deep submicron MOSFETs: ! Circuit simulators like Spice numerically solve device
! epitaxial layer for heavily-doped channel; models and Kirchoff’s laws to determine time-domain
! reduced area source/drain contacts for lower capacitance; circuit behavior.
! lightly-doped drains to reduce hot electron effects; ! Numerical solution allows more sophisticated models, non- ! silicided poly, diffusion to reduce resistance. functional (table-driven) models, etc.
Slides courtesy Modern VLSI Design, 3rd Edition Slides courtesy Modern VLSI Design, 3rd Edition
Some (by no means all) Spice Model Spice MOSFET Models Parameters
! Level 1: basic transistor equations of Section 2.2; not very ! L, W: transistor length width.
accurate. ! KP: transconductance.
! Level 2: more accurate model (effective channel length, ! GAMMA: body bias factor. etc.). ! AS, AD: source/drain areas. ! Level 3: empirical model. ! CJSW: zero-bias sidewall capacitance. ! Level 4 (BSIM): efficient empirical model. ! CGBO: zero-bias gate/bulk overlap capacitance. ! New models: level 28 (BSIM2), level 47 (BSIM3).
Slides courtesy Modern VLSI Design, 3rd Edition Slides courtesy Modern VLSI Design, 3rd Edition