Scholars' Mine Masters Theses Student Theses and Dissertations 1969 Basic design of MOSFET, four-phase, digital integrated circuits Earl Morris Worstell Follow this and additional works at: https://scholarsmine.mst.edu/masters_theses Part of the Electrical and Computer Engineering Commons Department: Recommended Citation Worstell, Earl Morris, "Basic design of MOSFET, four-phase, digital integrated circuits" (1969). Masters Theses. 5304. https://scholarsmine.mst.edu/masters_theses/5304 This thesis is brought to you by Scholars' Mine, a service of the Missouri S&T Library and Learning Resources. This work is protected by U. S. Copyright Law. Unauthorized use including reproduction for redistribution requires the permission of the copyright holder. For more information, please contact [email protected]. BASIC DESIGN OF MOSFET, FOUR-PHASE, DIGITAL INTEGRATED CIRCUITS By t_fL/ () Earl Morris Worstell , Jr./ J q¥- 2., A Thesis submitted to the faculty of THE UNIVERSITY OF MISSOURI - ROLLA in partial fulfillment of the requirements for the Degree of MASTER OF SCIENCE IN ELECTRICAL ENGINEERING Ro 11 a , M i sous ri 1969 Approved By i BASIC DESIGN OF MOSFET, FOUR-PHASE, DIGITAL INTEGRATED CIRCUITS by Earl M. Worstell, Jr. Abstract MOSFET is defined as metal oxide semiconductor field-effect transis­ tor. The integrated circuit design relates strictly to logic and switch­ ing circuits rather than linear circuits. The design of MOS circuits is primarily one of charge and discharge of stray capacitance through MOSFETS used as switches and active loads. To better take advantage of the possibilities of MOS technology, four­ phase (4¢) circuitry is developed. It offers higher speeds and lower power while permitting higher circuit density than does static or two­ phase (2cj>) logic. Equations are developed that apply directly to the design of four­ phase logic along with examples of circuitry that show their use. The most unique of these is the equation for discharge through two or more MOSFETS in series from a saturated condition. The effects of stray capacitance on circuit performance are explained. Methods for· ovE•r• corning deleter'ious effects and taking advantage of h::!!pfLd c:iflJCt:; i1r.· discussed and solved. The main effect is that of discharge o~ U.e stored charge on a logic node through the gate to source overlap capacitance when a phase clock returns to ground. In all, a complete method for designing 4¢ circuitry is developed and explained in appropriate examples. i i TABLE OF CONTENTS List of Figures and Tables--------------------------------iii I. Introduction--------------------------------------2 Purpose---------------------------------------2 Literature Review-----------------------------3 II. Background of MOS Fabrication and Parameters------5 Fabrication-----------------------------------5 Operation-------------------------------------8 · Equations and Relationships------------------10 III. Basic Design Theory------------------------------12 Two Phase and D-C Operation------------------13 Four Phase Circuitry and Operation-----------18 IV. Transistor Size Theory---------------------------29 Charge of the Load---------------------------29 Discharge of the Load------------------------32 Discharge by One Transistor--------------32 Series Discharge-------------------------34 Determination of Device Size Example---------38 V. Effects of Capacitance on Circuit Operation------43 Bit Layout I---------------------------------43 Bit Layout II--------------------------------48 VI. Summary and Conclusions--------------------------52 Acknowledgements---------------------------------53a Bibliography-------------------------------------54 Vita---------------------------------------------55 iii LIST OF FIGURES AND TABLES Tables Table Typical MOSFET Dimensions--------------------------- 8 Figures Figure 1 Cross Section of a MOSFET--------------------------- 6 Figure 2 MOSFET Fabrication Technique------------------------ 7 Figure 3a Characteristic Curve of a Typical P-channe1 MOSFET-- 9 Figure 3b Reference for Characteristics in 3a----------------- 9 Figure 4 D-C Logic Inverter----------------------------------14 Figure 5 Driver Discharge--------------------------------16, 32 Figure 6a 2¢ Dynamic Bit--------------------------------------17 Figure 6b Timing Sequence for Figure Sa-----------------------17 Figure 7 Basic 4¢ Bit----------------------------------------19 Figure 8 4¢ Timing Sequence----------------------------------19 Figure 9 Basic 4¢ Configurations------------------------~----20 Figure 10 4¢ Bit Showing Stray Capacitance--------------------22 Figure 11 Timing Sequence of Figure 10------------------------23 Figure 12 4¢ Inverter Showing Added Pull-up Capacitor Cp------26 Figure 13 Inverter Showing Inclusion of Pull-up Capacitor-----28 Figure 14 4¢ Dynamic Operation--------------------------------29 Figure 15 Charge of the Load Capacitance----------------------30 Figure 16 Characteristic Curve Showing Discharge Path---------32 Figure 17 Series Discharge------------------------------------35 Figure 18 4¢ Inverter-----------------------------------------38 Figure 19 4¢ Bit and ¢ Generator----------------------- 0 -··----44 Figure 20 ¢2 Generator Driving Inverter Bit I-----------------44 Figure 21 Bit Layout I----------------------------------------45 Figure 22 ¢2 Generator Driving Inverter Bit 11-------·-·-· ··-----48 Figure 23 Bit Layout I I-----------------------------·-·----·--·---49 Figure 24 Capacitance Model of Figure 23----------------------50 Chapter I 2 Introduction MOSFET, metal oxide semiconductor field-effect transistor, inte­ grated circuit technology has not existed long enough to have a wealth of circuit design technology available to anyone that might wish to become acquainted with the practices of industry. In fact, the practices of industry itself are not clearly presented or available to most persons desiring information. Only a scattered few articles on circuit design are available in the literature and these are usually very superficial due to the limited background of most readers. Most MOSFET literature has been in the area of processing and single device physics, stabiliza- tion of the oxide surface states and mobility. The purpose of this thesis is to develop a state-of-the-art design procedure for four-phase (4¢) circuits which are currently only beginning to appear on the commercial market. Enough background and supplementary material is supplied to enable most readers with a rudimentary knowledge of MOSFET technology to understand the design procedures without constantly referring to outside papers. The MOSFET circuit design book, MOSFET in Circuit Design by Robert H. Crawford, will be used as a source for all equations used in this thesis. 1 11 11 "MOSFET 11 wi 11 9enerally be shortened to MOS • Although MOS design technology is very scarce~ no attempt will be made to reiterate the sum of all design rules. Only the back~round necessary for an understanding of the very special area which is dev::'l oped is presented. Device fabrication and processing integrated circuits dre usually the secrets of a particular commercial enterprise and are ex­ plained only as necessary to the understanding of the parameters used in the design of a circuit. 3 Review of the Literature Only a very few papers have been published on 4¢ design. There have been a number published utilizing 2¢ design or general design. 2•3 A basic article on 4¢ design and comparison to 2¢ design, by Karp and de Atley, gives the basic beginnings of MOS logic design and elementa­ ry switching theory. 4 It is a good paper for basic equations and overall theory, but oversimplification leads to errors in their design procedures. A notable example of this is their statement that there is no need for the devices in an inverter to be different sizes in a 4¢ MOS system. Most of their conclusions are correct, but the amount of area saved and speed increase are exaggerated. One circuit is given, a J-K Flip-Flop, to illustrate 4¢ MOS circuitry, but several errors in either design or printing will keep the circuit from ever operating. They also state that time for discharge, or turn on time, is determined by the single calculation in the saturated region. This is only a rough approximation. It must also include the time spent discharging in the triode region. One of the best reports on MOS Technology is the research report published by the Air Force Avionic Laboratory. 5 The research was per­ formed by the Microelectronics Division of Philco-Ford Corporation. All circuit development in this report must be carefully considered by the individual user. At best, the report gives a good starting point, but the resuHs derived are characteristic of the init·ial assu.npU .. ns um: present very ili<rrow results especially in the realm of 4q) !·~0'3 ig1. equations. There are two books dealing mainly with MOS technology. 1 •6 The book by Crawford is generally a more circuits oriented approach and is a 4 general reference for this paper. The other by Richman is mainly a device oriented book and has excellent background material on theory of operation. For earlier work on MOS devices and structures, the reader is re­ ferred to papers by H. K. J. Ihantola7 and C. T. Sah 8. Most all impor­ tant and pertinent references other than these are thoroughly referenced in the two previously described books and in most cases are listed by both. 5 Chapter II Background of MOS Fabrication and Parameters This chapter deals with the rudiments of basic MOS fabrication only