DOCSLIB.ORG

Basic Design of MOSFET, Four-Phase, Digital Integrated Circuits

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Basic Design of MOSFET, Four-Phase, Digital Integrated Circuits Scholars' Mine Masters Theses Student Theses and Dissertations 1969 Basic design of MOSFET, four-phase, digital integrated circuits Earl Morris Worstell Follow this and additional works at: https://scholarsmine.mst.edu/masters_theses Part of the Electrical and Computer Engineering Commons Department: Recommended Citation Worstell, Earl Morris, "Basic design of MOSFET, four-phase, digital integrated circuits" (1969). Masters Theses. 5304. https://scholarsmine.mst.edu/masters_theses/5304 This thesis is brought to you by Scholars' Mine, a service of the Missouri S&T Library and Learning Resources. This work is protected by U. S. Copyright Law. Unauthorized use including reproduction for redistribution requires the permission of the copyright holder. For more information, please contact [email protected]. BASIC DESIGN OF MOSFET, FOUR-PHASE, DIGITAL INTEGRATED CIRCUITS By t_fL/ () Earl Morris Worstell , Jr./ J q¥- 2., A Thesis submitted to the faculty of THE UNIVERSITY OF MISSOURI - ROLLA in partial fulfillment of the requirements for the Degree of MASTER OF SCIENCE IN ELECTRICAL ENGINEERING Ro 11 a , M i sous ri 1969 Approved By i BASIC DESIGN OF MOSFET, FOUR-PHASE, DIGITAL INTEGRATED CIRCUITS by Earl M. Worstell, Jr. Abstract MOSFET is defined as metal oxide semiconductor field-effect transis­ tor. The integrated circuit design relates strictly to logic and switch­ ing circuits rather than linear circuits. The design of MOS circuits is primarily one of charge and discharge of stray capacitance through MOSFETS used as switches and active loads. To better take advantage of the possibilities of MOS technology, four­ phase (4¢) circuitry is developed. It offers higher speeds and lower power while permitting higher circuit density than does static or two­ phase (2cj>) logic. Equations are developed that apply directly to the design of four­ phase logic along with examples of circuitry that show their use. The most unique of these is the equation for discharge through two or more MOSFETS in series from a saturated condition. The effects of stray capacitance on circuit performance are explained. Methods for· ovE•r• corning deleter'ious effects and taking advantage of h::!!pfLd c:iflJCt:; i1r.· discussed and solved. The main effect is that of discharge o~ U.e stored charge on a logic node through the gate to source overlap capacitance when a phase clock returns to ground. In all, a complete method for designing 4¢ circuitry is developed and explained in appropriate examples. i i TABLE OF CONTENTS List of Figures and Tables--------------------------------iii I. Introduction--------------------------------------2 Purpose---------------------------------------2 Literature Review-----------------------------3 II. Background of MOS Fabrication and Parameters------5 Fabrication-----------------------------------5 Operation-------------------------------------8 · Equations and Relationships------------------10 III. Basic Design Theory------------------------------12 Two Phase and D-C Operation------------------13 Four Phase Circuitry and Operation-----------18 IV. Transistor Size Theory---------------------------29 Charge of the Load---------------------------29 Discharge of the Load------------------------32 Discharge by One Transistor--------------32 Series Discharge-------------------------34 Determination of Device Size Example---------38 V. Effects of Capacitance on Circuit Operation------43 Bit Layout I---------------------------------43 Bit Layout II--------------------------------48 VI. Summary and Conclusions--------------------------52 Acknowledgements---------------------------------53a Bibliography-------------------------------------54 Vita---------------------------------------------55 iii LIST OF FIGURES AND TABLES Tables Table Typical MOSFET Dimensions--------------------------- 8 Figures Figure 1 Cross Section of a MOSFET--------------------------- 6 Figure 2 MOSFET Fabrication Technique------------------------ 7 Figure 3a Characteristic Curve of a Typical P-channe1 MOSFET-- 9 Figure 3b Reference for Characteristics in 3a----------------- 9 Figure 4 D-C Logic Inverter----------------------------------14 Figure 5 Driver Discharge--------------------------------16, 32 Figure 6a 2¢ Dynamic Bit--------------------------------------17 Figure 6b Timing Sequence for Figure Sa-----------------------17 Figure 7 Basic 4¢ Bit----------------------------------------19 Figure 8 4¢ Timing Sequence----------------------------------19 Figure 9 Basic 4¢ Configurations------------------------~----20 Figure 10 4¢ Bit Showing Stray Capacitance--------------------22 Figure 11 Timing Sequence of Figure 10------------------------23 Figure 12 4¢ Inverter Showing Added Pull-up Capacitor Cp------26 Figure 13 Inverter Showing Inclusion of Pull-up Capacitor-----28 Figure 14 4¢ Dynamic Operation--------------------------------29 Figure 15 Charge of the Load Capacitance----------------------30 Figure 16 Characteristic Curve Showing Discharge Path---------32 Figure 17 Series Discharge------------------------------------35 Figure 18 4¢ Inverter-----------------------------------------38 Figure 19 4¢ Bit and ¢ Generator----------------------- 0 -··----44 Figure 20 ¢2 Generator Driving Inverter Bit I-----------------44 Figure 21 Bit Layout I----------------------------------------45 Figure 22 ¢2 Generator Driving Inverter Bit 11-------·-·-· ··-----48 Figure 23 Bit Layout I I-----------------------------·-·----·--·---49 Figure 24 Capacitance Model of Figure 23----------------------50 Chapter I 2 Introduction MOSFET, metal oxide semiconductor field-effect transistor, inte­ grated circuit technology has not existed long enough to have a wealth of circuit design technology available to anyone that might wish to become acquainted with the practices of industry. In fact, the practices of industry itself are not clearly presented or available to most persons desiring information. Only a scattered few articles on circuit design are available in the literature and these are usually very superficial due to the limited background of most readers. Most MOSFET literature has been in the area of processing and single device physics, stabiliza- tion of the oxide surface states and mobility. The purpose of this thesis is to develop a state-of-the-art design procedure for four-phase (4¢) circuits which are currently only beginning to appear on the commercial market. Enough background and supplementary material is supplied to enable most readers with a rudimentary knowledge of MOSFET technology to understand the design procedures without constantly referring to outside papers. The MOSFET circuit design book, MOSFET in Circuit Design by Robert H. Crawford, will be used as a source for all equations used in this thesis. 1 11 11 "MOSFET 11 wi 11 9enerally be shortened to MOS • Although MOS design technology is very scarce~ no attempt will be made to reiterate the sum of all design rules. Only the back~round necessary for an understanding of the very special area which is dev::'l oped is presented. Device fabrication and processing integrated circuits dre usually the secrets of a particular commercial enterprise and are ex­ plained only as necessary to the understanding of the parameters used in the design of a circuit. 3 Review of the Literature Only a very few papers have been published on 4¢ design. There have been a number published utilizing 2¢ design or general design. 2•3 A basic article on 4¢ design and comparison to 2¢ design, by Karp and de Atley, gives the basic beginnings of MOS logic design and elementa­ ry switching theory. 4 It is a good paper for basic equations and overall theory, but oversimplification leads to errors in their design procedures. A notable example of this is their statement that there is no need for the devices in an inverter to be different sizes in a 4¢ MOS system. Most of their conclusions are correct, but the amount of area saved and speed increase are exaggerated. One circuit is given, a J-K Flip-Flop, to illustrate 4¢ MOS circuitry, but several errors in either design or printing will keep the circuit from ever operating. They also state that time for discharge, or turn on time, is determined by the single calculation in the saturated region. This is only a rough approximation. It must also include the time spent discharging in the triode region. One of the best reports on MOS Technology is the research report published by the Air Force Avionic Laboratory. 5 The research was per­ formed by the Microelectronics Division of Philco-Ford Corporation. All circuit development in this report must be carefully considered by the individual user. At best, the report gives a good starting point, but the resuHs derived are characteristic of the init·ial assu.npU .. ns um: present very ili<rrow results especially in the realm of 4q) !·~0'3 ig1. equations. There are two books dealing mainly with MOS technology. 1 •6 The book by Crawford is generally a more circuits oriented approach and is a 4 general reference for this paper. The other by Richman is mainly a device oriented book and has excellent background material on theory of operation. For earlier work on MOS devices and structures, the reader is re­ ferred to papers by H. K. J. Ihantola7 and C. T. Sah 8. Most all impor­ tant and pertinent references other than these are thoroughly referenced in the two previously described books and in most cases are listed by both. 5 Chapter II Background of MOS Fabrication and Parameters This chapter deals with the rudiments of basic MOS fabrication only
Load more

Recommended publications
  • Understanding Performance Numbers in Integrated Circuit Design Oprecomp Summer School 2019, Perugia Italy 5 September 2019
    Understanding performance numbers in Integrated Circuit Design Oprecomp summer school 2019, Perugia Italy 5 September 2019 Frank K. G¨urkaynak [email protected] Integrated Systems Laboratory Introduction Cost Design Flow Area Speed Area/Speed Trade-offs Power Conclusions 2/74 Who Am I? Born in Istanbul, Turkey Studied and worked at: Istanbul Technical University, Istanbul, Turkey EPFL, Lausanne, Switzerland Worcester Polytechnic Institute, Worcester MA, USA Since 2008: Integrated Systems Laboratory, ETH Zurich Director, Microelectronics Design Center Senior Scientist, group of Prof. Luca Benini Interests: Digital Integrated Circuits Cryptographic Hardware Design Design Flows for Digital Design Processor Design Open Source Hardware Integrated Systems Laboratory Introduction Cost Design Flow Area Speed Area/Speed Trade-offs Power Conclusions 3/74 What Will We Discuss Today? Introduction Cost Structure of Integrated Circuits (ICs) Measuring performance of ICs Why is it difficult? EDA tools should give us a number Area How do people report area? Is that fair? Speed How fast does my circuit actually work? Power These days much more important, but also much harder to get right Integrated Systems Laboratory The performance establishes the solution space Finally the cost sets a limit to what is possible Introduction Cost Design Flow Area Speed Area/Speed Trade-offs Power Conclusions 4/74 System Design Requirements System Requirements Functionality Functionality determines what the system will do Integrated Systems Laboratory Finally the cost sets a limit
    [Show full text]
  • Advanced MOSFET Structures and Processes for Sub-7 Nm CMOS Technologies
    Advanced MOSFET Structures and Processes for Sub-7 nm CMOS Technologies By Peng Zheng A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Engineering - Electrical Engineering and Computer Sciences in the Graduate Division of the University of California, Berkeley Committee in charge: Professor Tsu-Jae King Liu, Chair Professor Laura Waller Professor Costas J. Spanos Professor Junqiao Wu Spring 2016 © Copyright 2016 Peng Zheng All rights reserved Abstract Advanced MOSFET Structures and Processes for Sub-7 nm CMOS Technologies by Peng Zheng Doctor of Philosophy in Engineering - Electrical Engineering and Computer Sciences University of California, Berkeley Professor Tsu-Jae King Liu, Chair The remarkable proliferation of information and communication technology (ICT) – which has had dramatic economic and social impact in our society – has been enabled by the steady advancement of integrated circuit (IC) technology following Moore’s Law, which states that the number of components (transistors) on an IC “chip” doubles every two years. Increasing the number of transistors on a chip provides for lower manufacturing cost per component and improved system performance. The virtuous cycle of IC technology advancement (higher transistor density lower cost / better performance semiconductor market growth technology advancement higher transistor density etc.) has been sustained for 50 years. Semiconductor industry experts predict that the pace of increasing transistor density will slow down dramatically in the sub-20 nm (minimum half-pitch) regime. Innovations in transistor design and fabrication processes are needed to address this issue. The FinFET structure has been widely adopted at the 14/16 nm generation of CMOS technology.
    [Show full text]
  • Chap01: Computer Abstractions and Technology
    CHAPTER 1 Computer Abstractions and Technology 1.1 Introduction 3 1.2 Eight Great Ideas in Computer Architecture 11 1.3 Below Your Program 13 1.4 Under the Covers 16 1.5 Technologies for Building Processors and Memory 24 1.6 Performance 28 1.7 The Power Wall 40 1.8 The Sea Change: The Switch from Uniprocessors to Multiprocessors 43 1.9 Real Stuff: Benchmarking the Intel Core i7 46 1.10 Fallacies and Pitfalls 49 1.11 Concluding Remarks 52 1.12 Historical Perspective and Further Reading 54 1.13 Exercises 54 CMPS290 Class Notes (Chap01) Page 1 / 24 by Kuo-pao Yang 1.1 Introduction 3 Modern computer technology requires professionals of every computing specialty to understand both hardware and software. Classes of Computing Applications and Their Characteristics Personal computers o A computer designed for use by an individual, usually incorporating a graphics display, a keyboard, and a mouse. o Personal computers emphasize delivery of good performance to single users at low cost and usually execute third-party software. o This class of computing drove the evolution of many computing technologies, which is only about 35 years old! Server computers o A computer used for running larger programs for multiple users, often simultaneously, and typically accessed only via a network. o Servers are built from the same basic technology as desktop computers, but provide for greater computing, storage, and input/output capacity. Supercomputers o A class of computers with the highest performance and cost o Supercomputers consist of tens of thousands of processors and many terabytes of memory, and cost tens to hundreds of millions of dollars.
    [Show full text]
  • MOS Caps II; Mosfets I
    6.012 - Microelectronic Devices and Circuits Lecture 10 - MOS Caps II; MOSFETs I - Outline G cS vGS + SiO2 – • Review - MOS Capacitor (= vGB) The "Delta-Depletion Approximation" n+ (n-MOS example) p-Si Flat-band voltage: VFB ≡ vGB such that φ(0) = φp-Si: VFB = φp-Si – φm Threshold voltage: VT ≡ vGB such B 1/2 * that φ(0) = – φp-Si: VT = VFB – 2φp-Si + [2εSi qNA|2φp-Si| ] /Cox * * Inversion layer sheet charge density: qN = – Cox [vGC – VT] • Charge stores - qG(vGB) from below VFB to above VT Gate Charge: qG(vGB) from below VFB to above VT Gate Capacitance: Cgb(VGB) Sub-threshold charge: qN(vGB) below VT • 3-Terminal MOS Capacitors - Bias between B and C Impact is on VT(vBC): |2φp-Si| → (|2φp-Si| - vBC) • MOS Field Effect Transistors - Basics of model Gradual Channel Model: electrostatics problem normal to channel drift problem in the plane of the channel Clif Fonstad, 10/15/09 Lecture 10 - Slide 1 G CS vGS + SiO2 – (= vGB) The n-MOS capacitor n+ Right: Basic device p-Si with vBC = 0 B Below: One-dimensional structure for depletion approximation analysis* vGB + – SiO 2 p-Si G B x -tox 0 * Note: We can't forget the n+ region is there; we Clif Fonstad, 10/15/09 will need electrons, and they will come from there. Lecture 10 - Slide 2 MOS Capacitors: Where do the electrons in the inversion layer come from? Diffusion from the p-type substrate? If we relied on diffusion of minority carrier electrons from the p-type substrate it would take a long time to build up the inversion layer charge.
    [Show full text]
  • Photovoltaic Couplers for MOSFET Drive for Relays
    Photocoupler Application Notes Basic Electrical Characteristics and Application Circuit Design of Photovoltaic Couplers for MOSFET Drive for Relays Outline: Photovoltaic-output photocouplers(photovoltaic couplers), which incorporate a photodiode array as an output device, are commonly used in combination with a discrete MOSFET(s) to form a semiconductor relay. This application note discusses the electrical characteristics and application circuits of photovoltaic-output photocouplers. ©2019 1 Rev. 1.0 2019-04-25 Toshiba Electronic Devices & Storage Corporation Photocoupler Application Notes Table of Contents 1. What is a photovoltaic-output photocoupler? ............................................................ 3 1.1 Structure of a photovoltaic-output photocoupler .................................................... 3 1.2 Principle of operation of a photovoltaic-output photocoupler .................................... 3 1.3 Basic usage of photovoltaic-output photocouplers .................................................. 4 1.4 Advantages of PV+MOSFET combinations ............................................................. 5 1.5 Types of photovoltaic-output photocouplers .......................................................... 7 2. Major electrical characteristics and behavior of photovoltaic-output photocouplers ........ 8 2.1 VOC-IF characteristics .......................................................................................... 9 2.2 VOC-Ta characteristic ........................................................................................
    [Show full text]
  • COSC 6385 Computer Architecture - Multi-Processors (IV) Simultaneous Multi-Threading and Multi-Core Processors Edgar Gabriel Spring 2011
    COSC 6385 Computer Architecture - Multi-Processors (IV) Simultaneous multi-threading and multi-core processors Edgar Gabriel Spring 2011 Edgar Gabriel Moore’s Law • Long-term trend on the number of transistor per integrated circuit • Number of transistors double every ~18 month Source: http://en.wikipedia.org/wki/Images:Moores_law.svg COSC 6385 – Computer Architecture Edgar Gabriel 1 What do we do with that many transistors? • Optimizing the execution of a single instruction stream through – Pipelining • Overlap the execution of multiple instructions • Example: all RISC architectures; Intel x86 underneath the hood – Out-of-order execution: • Allow instructions to overtake each other in accordance with code dependencies (RAW, WAW, WAR) • Example: all commercial processors (Intel, AMD, IBM, SUN) – Branch prediction and speculative execution: • Reduce the number of stall cycles due to unresolved branches • Example: (nearly) all commercial processors COSC 6385 – Computer Architecture Edgar Gabriel What do we do with that many transistors? (II) – Multi-issue processors: • Allow multiple instructions to start execution per clock cycle • Superscalar (Intel x86, AMD, …) vs. VLIW architectures – VLIW/EPIC architectures: • Allow compilers to indicate independent instructions per issue packet • Example: Intel Itanium series – Vector units: • Allow for the efficient expression and execution of vector operations • Example: SSE, SSE2, SSE3, SSE4 instructions COSC 6385 – Computer Architecture Edgar Gabriel 2 Limitations of optimizing a single instruction
    [Show full text]
  • Fundamentals of MOSFET and IGBT Gate Driver Circuits
    Application Report SLUA618A–March 2017–Revised October 2018 Fundamentals of MOSFET and IGBT Gate Driver Circuits Laszlo Balogh ABSTRACT The main purpose of this application report is to demonstrate a systematic approach to design high performance gate drive circuits for high speed switching applications. It is an informative collection of topics offering a “one-stop-shopping” to solve the most common design challenges. Therefore, it should be of interest to power electronics engineers at all levels of experience. The most popular circuit solutions and their performance are analyzed, including the effect of parasitic components, transient and extreme operating conditions. The discussion builds from simple to more complex problems starting with an overview of MOSFET technology and switching operation. Design procedure for ground referenced and high side gate drive circuits, AC coupled and transformer isolated solutions are described in great details. A special section deals with the gate drive requirements of the MOSFETs in synchronous rectifier applications. For more information, see the Overview for MOSFET and IGBT Gate Drivers product page. Several, step-by-step numerical design examples complement the application report. This document is also available in Chinese: MOSFET 和 IGBT 栅极驱动器电路的基本原理 Contents 1 Introduction ................................................................................................................... 2 2 MOSFET Technology ......................................................................................................
    [Show full text]
  • Power MOSFET Basics by Vrej Barkhordarian, International Rectifier, El Segundo, Ca
    Power MOSFET Basics By Vrej Barkhordarian, International Rectifier, El Segundo, Ca. Breakdown Voltage......................................... 5 On-resistance.................................................. 6 Transconductance............................................ 6 Threshold Voltage........................................... 7 Diode Forward Voltage.................................. 7 Power Dissipation........................................... 7 Dynamic Characteristics................................ 8 Gate Charge.................................................... 10 dV/dt Capability............................................... 11 www.irf.com Power MOSFET Basics Vrej Barkhordarian, International Rectifier, El Segundo, Ca. Discrete power MOSFETs Source Field Gate Gate Drain employ semiconductor Contact Oxide Oxide Metallization Contact processing techniques that are similar to those of today's VLSI circuits, although the device geometry, voltage and current n* Drain levels are significantly different n* Source t from the design used in VLSI ox devices. The metal oxide semiconductor field effect p-Substrate transistor (MOSFET) is based on the original field-effect Channel l transistor introduced in the 70s. Figure 1 shows the device schematic, transfer (a) characteristics and device symbol for a MOSFET. The ID invention of the power MOSFET was partly driven by the limitations of bipolar power junction transistors (BJTs) which, until recently, was the device of choice in power electronics applications. 0 0 V V Although it is not possible to T GS define absolutely the operating (b) boundaries of a power device, we will loosely refer to the I power device as any device D that can switch at least 1A. D The bipolar power transistor is a current controlled device. A SB (Channel or Substrate) large base drive current as G high as one-fifth of the collector current is required to S keep the device in the ON (c) state. Figure 1. Power MOSFET (a) Schematic, (b) Transfer Characteristics, (c) Also, higher reverse base drive Device Symbol.
    [Show full text]
  • Extending the Road Beyond CMOS
    By James A. Hutchby, George I. Bourianoff, Victor V. Zhirnov, and Joe E. Brewer he quickening pace of MOSFET technology scaling, as seen in the new 2001 International Technology Roadmap for Semiconductors [1], is ac- celerating the introduction of many new technologies to extend CMOS Tinto nanoscale MOSFET structures heretofore not thought possible. A cautious optimism is emerging that these new technologies may extend MOSFETs to the 22-nm node (9-nm physical gate length) by 2016 if not by the end of this decade. These new devices likely will feature several new materials cleverly incorporated into new nonbulk MOSFET structures. They will be ultra fast and dense with a voracious appetite for power. Intrinsic device speeds may be more than 1 THz and integration densities will exceed 1 billion transistors per cm2. Excessive power consumption, however, will demand judicious use of these high-performance devices only in those critical paths requiring their su- perior performance. Two or perhaps three other lower performance, more power-efficient MOSFETs will likely be used to perform less performance-criti- cal functions on the chip to manage the total power consumption. Beyond CMOS, several completely new approaches to information-process- ing and data-storage technologies and architectures are emerging to address the timeframe beyond the current roadmap. Rather than vying to “replace” CMOS, one or more of these embryonic paradigms, when combined with a CMOS plat- form, could extend microelectronics to new applications domains currently not accessible to CMOS. A successful new information-processing paradigm most likely will require a new platform technology embodying a fabric of intercon- nected primitive logic cells, perhaps in three dimensions.
    [Show full text]
  • Rapid Mapping of Digital Integrated Circuit Logic Gates Via Multi-Spectral Backside Imaging
    RAPID MAPPING OF DIGITAL INTEGRATED CIRCUIT LOGIC GATES VIA MULTI-SPECTRAL BACKSIDE IMAGING RONEN ADATO1;4;∗, AYDAN UYAR1;4, MAHMOUD ZANGENEH1;4, BOYOU ZHOU1;4, AJAY JOSHI1;4, BENNETT GOLDBERG1;2;3;4 AND M SELIM UNL¨ U¨ 1;3;4 Abstract. Modern semiconductor integrated circuits are increasingly fabricated at untrusted third party foundries. There now exist myriad security threats of malicious tampering at the hardware level and hence a clear and pressing need for new tools that enable rapid, robust and low-cost validation of circuit layouts. Optical backside imaging offers an attractive platform, but its limited resolution and throughput cannot cope with the nanoscale sizes of modern circuitry and the need to image over a large area. We propose and demonstrate a multi-spectral imaging approach to overcome these obstacles by identifying key circuit elements on the basis of their spectral response. This obviates the need to directly image the nanoscale components that define them, thereby relaxing resolution and spatial sampling requirements by 1 and 2 - 4 orders of magnitude respectively. Our results directly address critical security needs in the integrated circuit supply chain and highlight the potential of spectroscopic techniques to address fundamental resolution obstacles caused by the need to image ever shrinking feature sizes in semiconductor integrated circuits. 1. Introduction Semiconductor integrated circuits (ICs) are pervasive and essential components in virtually all modern devices, from personal computers, to medical equipment, to varied military systems and technologies. Their functionality is defined by a massive number (∼ 106 − 109 currently) of in- terconnected logic gates that correspond physically to various nanoscale doped regions, polysilicon and metal (usually copper and tungsten) structures.
    [Show full text]
  • Basics of CMOS Logic Ics Application Note
    Basics of CMOS Logic ICs Application Note Basics of CMOS Logic ICs Outline: This document describes applications, functions, operations, and structure of CMOS logic ICs. Each functions (inverter, buffer, flip-flop, etc.) are explained using system diagrams, truth tables, timing charts, internal circuits, image diagrams, etc. ©2020- 2021 1 2021-01-31 Toshiba Electronic Devices & Storage Corporation Basics of CMOS Logic ICs Application Note Table of Contents Outline: ................................................................................................................................................. 1 Table of Contents ................................................................................................................................. 2 1. Standard logic IC ............................................................................................................................. 3 1.1. Devices that use standard logic ICs ................................................................................................. 3 1.2. Where are standard logic ICs used? ................................................................................................ 3 1.3. What is a standard logic IC? .............................................................................................................. 4 1.4. Classification of standard logic ICs ................................................................................................... 5 1.5. List of basic circuits of CMOS logic ICs (combinational logic circuits)
    [Show full text]
  • Integrated Circuit Design Macmillan New Electronics Series Series Editor: Paul A
    Integrated Circuit Design Macmillan New Electronics Series Series Editor: Paul A. Lynn Paul A. Lynn, Radar Systems A. F. Murray and H. M. Reekie, Integrated Circuit Design Integrated Circuit Design Alan F. Murray and H. Martin Reekie Department of' Electrical Engineering Edinhurgh Unit·ersity Macmillan New Electronics Introductions to Advanced Topics M MACMILLAN EDUCATION ©Alan F. Murray and H. Martin Reekie 1987 All rights reserved. No reproduction, copy or transmission of this publication may be made without written permission. No paragraph of this publication may be reproduced, copied or transmitted save with written permission or in accordance with the provisions of the Copyright Act 1956 (as amended), or under the terms of any licence permitting limited copying issued by the Copyright Licensing Agency, 7 Ridgmount Street, London WC1E 7AE. Any person who does any unauthorised act in relation to this publication may be liable to criminal prosecution and civil claims for damages. First published 1987 Published by MACMILLAN EDUCATION LTD Houndmills, Basingstoke, Hampshire RG21 2XS and London Companies and representatives throughout the world British Library Cataloguing in Publication Data Murray, A. F. Integrated circuit design.-(Macmillan new electronics series). 1. Integrated circuits-Design and construction I. Title II. Reekie, H. M. 621.381'73 TK7874 ISBN 978-0-333-43799-5 ISBN 978-1-349-18758-4 (eBook) DOI 10.1007/978-1-349-18758-4 To Glynis and Christa Contents Series Editor's Foreword xi Preface xii Section I 1 General Introduction
    [Show full text]