Switched-Capacitor Circuits

Home , Capacitor, Switch, Switched capacitor

David Johns and Ken Martin University of Toronto ([email protected]) ([email protected])

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Basic Building Blocks Opamps • Ideal opamps usually assumed. • Important non-idealities — dc gain: sets the accuracy of charge transfer, hence, transfer-function accuracy. — unity-gain freq, phase margin & slew-rate: sets the max clocking frequency. A general rule is that unity-gain freq should be 5 times (or more) higher than the clock-freq. — dc offset: Can create dc offset at output. Circuit techniques to combat this which also reduce 1/f noise.

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metal C1 metal poly1

Cp1 thin oxide bottom plate C1 poly2 Cp2 thick oxide C p1 Cp2

(substrate - ac ground)

cross-section view equivalent circuit • Substantial parasitics with large bottom plate capacitance (20 percent of C1 ) • Also, metal-metal capacitors are used but have even larger parasitic capacitances.

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Basic Building Blocks Switches I I Symbol n-channel

v1 v2 v1 v2

I transmission I I gate v1 v p-channel v 2 1 v2 I • Mosfet switches are good switches. — off-resistance near G: range — on-resistance in 100: to 5k: range (depends on transistor sizing) • However, have non-linear parasitic capacitances.

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© D. Johns, K. Martin, 1997 Basic Building Blocks Non-Overlapping Clocks I1 T Von I I1 Voff n – 2 n – 1 n n + 1 tTe delay 1 I fs { --- delay V 2 T on I Voff 2 n – 32e n – 12e n + 12e tTe • Non-overlapping clocks — both clocks are never on at same time • Needed to ensure charge is not inadvertently lost.

• Integer values occur at end of I1 .

• End of I2 is 1/2 off integer value.

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Switched-Capacitor Resistor Equivalent I I 1 2 Req V V V1 V2 1 2 C1 T 'QC= V – V every clock period Req = ------1 1 2 C1

Qx = CxVx (1)

• C1 charged to V1 and then V2 during each clk period.

'Q1 = C1 V1 – V2 (2) • Find equivalent average current C V – V I = ------1 1 2 (3) avg T where T is the clk period.

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V1 – V2 Ieq = ------(4) Req • Equating two, we have T 1 Req ==------(5) C1 C1fs • This equivalence is useful when looking at low-freq portion of a SC-circuit. • For higher frequencies, discrete-time analysis is used.

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Resistor Equivalence Example • What is the equivalent resistance of a 5pF capacitance sampled at a clock frequency of 100kHz . • Using (5), we have 1 R ==------2M: eq –12 3 510u 100u 10 • Note that a very large equivalent resistance of 2M: can be realized. • Requires only 2 transistors, a clock and a relatively small capacitance. • In a typical CMOS process, such a large resistor would normally require a huge amount of silicon area.

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vc2()nT

I1 I2 C vcx()t 2 I1 vci()t vco()t

vc1()t C1 v ()n = v ()nT vi()n = vci()nT o co

• Start by looking at an integrator which IS affected by parasitic capacitances

• Want to find output voltage at end of I1 in relation to input sampled at end of I1 .

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Parasitic-Sensitive Integrator

C2 C2 v ()nT– T ci vci()nT– T e 2 C 1 v ()nT– T C1 co vco()nT– T e 2

I1 on I2 on

• At end of I2

C2vco()nT– T e 2 = C2vco()nT– T – C1vci()nT– T (6)

• But would like to know the output at end of I1

C2vco()nT = C2vco()nT– T e 2 (7) • leading to

C2vco()nT = C2vco()nT– T – C1vci()nT– T (8)

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C1 vo()n = vo()n – 1 – ------vi()n – 1 (9) C2 and taking z-transform and re-arranging, leads to

Vo()z §·C1 1 Hz(){ ------= –¨¸------(10) Vi()z ©¹C2 z – 1 • Note that gain-coefficient is determined by a ratio of two capacitance values. • Ratios of capacitors can be set VERY accurately on an integrated circuit (within 0.1 percent) • Leads to very accurate transfer-functions.

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Typical Waveforms

t I2

t vci()t

vcx()t

vco()t

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§·C z–12/ Hz()= – ------1 ------(11) ¨¸12/ –12/ ©¹C2 z – z • To find freq response, recall

ze==jZT cos ZT + jsin ZT (12) ZT ZT z12/ = cos§·------+ jsin§·------(13) ©¹2 ©¹2 ZT ZT z–12/ = cos§·------– jsin§·------(14) ©¹2 ©¹2 ZT ZT cos§·------– jsin§·------jZT §·C1 ©¹2 ©¹2 He()= –¨¸------(15) C ZT ©¹2 j2sin§·------©¹2

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Low Frequency Behavior • Above is exact but when ZT « 1 (i.e., at low freq)

jZT §·C1 1 He()# –¨¸------(16) ©¹C2 jZT • Thus, the transfer function is same as a continuous- time integrator having a gain constant of

C1 1 KI # ------(17) C2T which is a function of the integrator capacitor ratio and clock frequency only.

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I1 I2 I1 vi()n vo()n C1 Cp1

Cp2 • Accounting for parasitic capacitances, we have

§·C1 + Cp1 1 Hz()= –¨¸------(18) ©¹C2 z – 1 • Thus, gain coefficient is not well controlled and partially non-linear (due to Cp1 being non-linear).

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Parasitic-Insensitive Integrators

I1 I C 2 1 I v ()t 1 ci vco()t

I2 I1 vi()n = vci()nT vo()n = vco()nT

• By using 2 extra switches, integrator can be made insensitive to parasitic capacitances — more accurate transfer-functions — better linearity (since non-linear capacitances unimportant)

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I1 on I2 on

• Same analysis as before except that C1 is switched in polarity before discharging into C2 .

Vo()z §·C1 1 Hz(){ ------= ¨¸------(19) Vi()z ©¹C2 z – 1 • A positive integrator (rather than negative as before)

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Parasitic-Insensitive Integrators

Cp3 Cp4

C2 I1 I C 2 1 I1 vi()n vo()n I2 I1

Cp1 Cp2

• Cp3 has little effect since it is connected to virtual gnd

• Cp4 has little effect since it is driven by output

• Cp2 has little effect since it is either connected to virtual gnd or physical gnd.

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• Cp1 is continuously being charged to vi()n and discharged to ground.

• I1 on — the fact that Cp1 is also charged to vi()n – 1 does not affect C1 charge.

• I2 on — Cp1 is discharged through the I2 switch attached to its node and does not affect the charge accumulating on C2 . • While the parasitic capacitances may slow down settling time behavior, they do not affect the discrete- time difference equation

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Parasitic-Insensitive Inverting Integrator C2 I1 I1 C1 I1 vi()n vo()n Vi()z I2 I2 Vo()z

C2vco()nT– T e 2 = C2vco()nT– T (20)

C2vco()nT = C2vco()nT– T e 2 – C1vci()nT (21) • Present output depends on present input(delay-free)

Vo()z §·C1 z Hz(){ ------= –¨¸------(22) Vi()z ©¹C2 z – 1 • Delay-free integrator has negative gain while delaying integrator has positive gain.

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C1 V1()z I I 1 C 2 2 CA V2()z I I 2 1 I1 V ()z I1 I1 o C3 V3()z I2 I2

–1 –C1 1 – z V1()z –1 C2z 1 1 §·------V ()z –1 V ()z 2 ©¹CA 1 – z o

–C3 V3()z

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First-Order Filter

Vin()s Vout()s

• Start with an active-RC structure and replace resistors with SC equivalents. • Analyze using discrete-time analysis.

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I I 1 1 I1 I1 C2 C3

I2 I2 I2 I2

CA I C1 1 Vi()z Vo()z

–C3

–C2 1 1 §·------V ()z Vi()z –1 o ©¹CA 1 – z –1 –C1 1 – z

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First-Order Filter –1 –1 CA 1 – z Vo()z = – C3Vo()z – C2Vi()z – C1 1 – z Vi()z (23)

§·C1 §·C2 ¨¸------1 – z–1 + ¨¸------©¹CA ©¹CA –------Vo()z C Hz(){ ------= 1 – z–1 + ------3- (24) V ()z i CA

§·C1 + C2 C1 ¨¸------z – ------©¹CA CA = –------§·C3 ¨¸1 + ------z – 1 ©¹CA

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CA zp = ------(25) CA + C3

• For positive capacitance values, this pole is restricted to the real axis between 0 and 1 — circuit is always stable. • The zero of (24) is found to be given by

C1 zz = ------(26) C1 + C2 • Also restricted to real axis between 0 and 1.

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First-Order Filter The dc gain is found by setting z = 1 which results in –C H()1 = ------2 (27) C3 • Note that in a fully-differential implementation, effective negative capacitances for C1 , C2 and C3 can be achieved by simply interchanging the input wires. • In this way, a zero at z = –1 could be realized by setting

C1 = –0.5C2 (28)

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© D. Johns, K. Martin, 1997 First-Order Example • Find the capacitance values needed for a first-order SC-circuit such that its 3dB point is at 10kHz when a clock frequency of 100kHz is used. • It is also desired that the filter have zero gain at 50kHz (i.e. z = –1 ) and the dc gain be unity.

• Assume CA = 10pF . Solution • Making use of the bilinear transform pz=1 – 1 e z + 1 the zero at – is mapped to :f= . • The frequency warping maps the -3dB frequency of 10kHz (or 0.2S rad/sample ) to

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First-Order Example 0.2S : ==tan§·------0.3249 (29) ©¹2 • in the continuous-time domain leading to the continuous-time pole, pp , required being

pp = –0.3249 (30)

• This pole is mapped back to zp given by

1 + pp zp ==------0.5095 (31) 1 – pp • Therefore, Hz() is given by kz + 1 Hz()= ------(32) z – 0.5095

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© D. Johns, K. Martin, 1997 First-Order Example • where k is determined by setting the dc gain to one (i.e. H()1 = 1) resulting 0.24525 z + 1 Hz()= ------(33) z – 0.5095 • or equivalently, 0.4814z + 0.4814 Hz()= ------(34) 1.9627z – 1 • Equating these coefficients with those of (24) (and assuming CA = 10pF ) results in

C1 = 4.814pF (35) C2 = –9.628pF (36) C3 = 9.628pF (37)

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Switch Sharing

I1 C3

I2 C1 CA

I1 I1 C2 ) Vo()z I2 I2

• Share switches that are always connected to the same potentials.

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© D. Johns, K. Martin, 1997 Fully-Differential Filters • Most modern SC filters are fully-differential • Difference between two voltages represents signal (also balanced around a common-mode voltage). • Common-mode noise is rejected. • Even order distortion terms cancel

2 3 4 v = k v ++++k v k v k v p1 1 1 2 1 3 1 4 1 } v nonlinear 1 element 3 5 + v = 2k v +++2k v 2k v diff 1 1 3 1 5 1 } - –v nonlinear 1 element 2 3 4 v = – k v +++k v – k v k v n1 1 1 2 1 3 1 4 1 }

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Fully-Differential Filters C1 C 3 I1

I2 C I2 A I2 + C2 I1 I1 + V ()z V ()z i I o I1 1 - - C2 C I2 I2 A I2

C 3 I1

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I2 C I2 A I2 + C2 I1 I1 + V ()z V ()z i I o I1 1 - - C2 C I2 I2 A I2

C 3 I1

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Fully-Differential Filters • Note that fully-differential version is essentially two copies of single-ended version, however ... area penalty not twice. • Only one opamp needed (though common-mode circuit also needed) • Input and output signal swings have been doubled so that same dynamic range can be achieved with half capacitor sizes (from kTe C analysis) • Switches can be reduced in size since small caps used. • However, there is more wiring in fully-differ version but better noise and distortion performance.

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1 e Zo Q e Zo C = 1 A Vc1()s CB = 1 Z e k o o –1 e Zo Vin()s Vout()s 1 e k1

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Low-Q Biquad Filter

I1 I1 K4C1

I2 I2 I1 I1 K6C2 I I C 2 2 1 C V1()z 2 I1 K C I1 1 1 I1 I2 Vi()z K5C2 I1 Vo()z I2 I2 I2 I1

I1 K C I1 2 2

I2 I2

K3C2

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–K4

–K6 V1()z –K 1 K z–1 1 V ()z 1 ------5 ------V ()z i 1 – z–1 1 – z–1 o

–K2 –1 –1K3 – z

2 Vo()z K2 + K3 z ++ K1K5 –2K2 – K3 zK3 Hz(){ ------= –------(39) 2 Vi()z 1 + K6 z ++ K4K5 –2K6 – z 1

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Low-Q Biquad Filter Design 2 a z ++a za Hz()= –------2 1 0 (40) 2 b2z ++b1z 1 • we can equate the individual coefficients of “z” in (39) and (40), resulting in:

K3 = a0 (41) K2 = a2 – a0 (42) K1K5 = a0 ++a1 a2 (43) K6 = b2 – 1 (44) K4K5 = b1 ++b2 1 (45) • A degree of freedom is available here in setting internal V1()z output

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K4 ==K5 b1 ++b2 1 (46) Low-Q Biquad Capacitance Ratio • Comparing resistor circuit to SC circuit, we have

K4 ||K5 ZoT (47)

ZoT K | ------(48) 6 Q • However, the sampling-rate, 1 e T , is typically much larger that the approximated pole-frequency, Zo ,

ZoT « 1 (49)

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Low-Q Biquad Capacitance Ratio • Thus, the largest capacitors determining pole positions are the integrating capacitors, C1 and C2 .

• If Q 1 , the smallest capacitors are K4C1 and K5C2 resulting in an approximate capacitance spread of

1 e ZoT . • If Q ! 1 , then from (48) the smallest capacitor would be K6C2 resulting in an approximate capacitance

spread of Q e ZoT — can be quite large for Q » 1

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1 e Zo 1 e Q C = 1 1 C2 = 1 Zo e ko –1 e Z Vin()s o Vout()s k1 e Zo

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High-Q Biquad Filter

I1 K C I1 4 1

I2 I2 K6C1 C 1 V ()z 1 C2 I1 K C I1 1 1 I I2 V ()z 1 K5C I1 i 2 Vo()z I2 I2 I2 I1

K C 2 1

K3C2

• Q-damping now performed by K6C1

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• Input K1C1 : major path for lowpass

• Input K2C1 : major path for band-pass filters

• Input K3C2 : major path for high-pass filters • General transfer-function is: 2 Vo()z K3z ++ K1K5 + K2K5 – 2K3 zK 3 – K2K5 Hz(){ ------= –------(50) 2 Vi()z z ++ K4K5 + K5K6 – 2 z 1 – K5K6 • If matched to the following general form 2 a z ++a za Hz()= –------2 1 0 (51) 2 z ++b1zb0

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High-Q Biquad Filter K1K5 = a0 ++a1 a2 (52)

K2K5 = a2 – a0 (53)

K3 = a2 (54)

K4K5 = 1 ++b0 b1 (55)

K5K6 = 1 – b0 (56) • And, as in lowpass case, can set

K4 ==K5 1 ++b0 b1 (57)

• As before, K4 and K5 approx ZoT « 1 but K6 # 1 e Q

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I1 C3 Q6 I Q5 2 C1

CA I1 I1a C2 I1 Vi()z Q1 Q4 Vo()z I2 Q2Q3 I2a

• Advance I1a and I2a so that only their charge injection affect circuit (result is a dc offset)

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Charge Injection

• Note: I2a connected to ground while I1a connected to virtual ground, therefore ... — can use single n-channel transistors — charge injection NOT signal dependent

QCH ==–WLCoxVeff –WLCox VGS – Vt (58)

• Charge related to VGS and Vt and Vt related to substrate-source voltage.

• Source of Q3 and Q4 remains at 0 volts — amount of charge injected by Q3 Q4 is not signal dependent and can be considered as a dc offset.

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• Assume switches Q3 Q4 have Vtn = 0.8V , W = 30Pm , –3 2 L = 0.8Pm, Cox = 1.9u 10 pF e Pm , and power supplies are r2.5V .

• Channel-charge of Q3 Q4 (when on) is

QCH3 ==QCH4 –0.8 30 0.0019 2.5– 0.8 (59) –3 = –1077.5 u pC • dc feedback keeps virtual opamp input at zero volts.

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Charge Injection Example

• Charge transfer into C3 given by Q = –C v (60) C3 3 out

• We estimate half channel-charges of Q3 , Q4 are injected to the virtual ground leading to 1 --- Q + Q = Q (61) 2 CH3 CH4 C3 which leads to –3 77.5u 10 pC v ==------7 8 m V (62) out 1pF • dc offset affected by the capacitor sizes, switch sizes and power supply voltage.

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I1 C2 I I 1 1 I KC2 2

I2 I2 C1 KC1 vin()n vout()n = –Kvin()n

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SC Gain Circuits — Resettable Gain

I C2 2

vout

Voff time I2 I1 I2 I1 }

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© D. Johns, K. Martin, 1997 SC Gain Circuits Parallel RC Gain Circuit • circuit amplifies 1/f noise as well as opamp offset voltage Resettable Gain Circuit • performs offset cancellation • also highpass filters 1/f noise of opamp • However, requires a high slew-rate from opamp V off- + VC C - 2+ 2 C V 2 vout()n V v ()n + C1- - off+ in V C C off 1 + §·C 1 + Voff 1 V - = –¨¸------vin()n off- ©¹C2

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SC Gain Circuits — Capacitive-Reset • Eliminate slew problem and still cancel offset by coupling opamp’s output to invertering input

I1 C3 I2 I2

• C4 is optional de-glitching capacitor

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SC Gain Circuits — Differential Cap-Reset I1a C3 I2 I2a C 2 I I 1 + 1 C v 1 §·C1 + - in v = ¨¸------v – v out C in in I2 ©¹2 I2 C - C1 2 I1 vin I1 I 2a C3 I2

I1a • Accepts differential inputs and partially cancels switch clock-feedthrough

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© D. Johns, K. Martin, 1997 Correlated Double-Sampling (CDS) • Preceeding SC gain amp is an example of CDS • Minimizes errors due to opamp offset and 1/f noise • When CDS used, opamps should have low thermal noise (often use n-channel input transistors) • Often use CDS in only a few stages — input stage for oversampling converter — some stages in a filter (where low-freq gain high)

• Basic approach: — Calibration phase: store input offset voltage — Operation phase: error subtracted from signal

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Better High-Freq CDS Amplifier I1 C2 I 1 I2 C1 I1 v in vout I2 I I2 2 I2 Cc1 Cc2

I1 I1 I1

• I2 — C1' C2' used but include errors

• I1 — C1 C2 used but here no offset errors

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I2 I1 I I 2 1 I C1 1 vin vout I I I C 1 2 1 c2

• I1 — sample opamp offset on C2'

• I2 — C2' placed in series with opamp to reduce error • Offset errors reduced by opamp gain • Can also apply this technique to gain amps

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SC Amplitude Modulator

• Square wave modulate by r1 (i.e. Vout = rVin )

I1 C3 I2 I 2 I1 IB C2 I IA I1 2 C1 vin vout I IB A

Ica IA = II2 Ica + 1 Ica IB = II1 Ica + 2 Ica • Makes use of cap-reset gain circuit.

• Ica is the modulating signal

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v Square Wave v in Modulator out

Ica

• Use square wave modulator and comparator to make • For proper operation, comparator output should changes synchronously with the sampling instances.

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SC Peak Detector

I VDD

vin comp Q opamp 2 vout v vout in Q C 1 CH H

• Left circuit can be fast but less accurate • Right circuit is more accurate due to feedback but slower due to need for compensation (circuit might also slew so opamp’s output should be clamped)

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