Practical Issues Designing Switched-Capacitor Circuit
ECEN 622 (ESS) Fall 2011 Practical Issues Designing Switched-Capacitor Circuit
Material partially prepared by Sang Wook Park and Shouli Yan
ELEN 622 Fall 2011 1 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
MOS switch
G
G
S Cov Cox Cov D
S D Ron
o Excellent Roff
o Non-idea Effect
Charge injection, Clock feed-through
Finite and nonlinear Ron
ELEN 622 Fall 2011 2 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
Charge Injection
G
Qch1 Qch2
C VS
o During TR. is turned on, Qch is formed at channel surface
Qch = WLC OX (VGS −Vth )
When TR. is off, Qch1 is absorbed by Vs, but Qch2 is injected to C
o Charge injected through overlap capacitor
o Appeared as an offset voltage error on C
ELEN 622 Fall 2011 3 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
Charge Injection Effect
CLK Ideal sw.
Vout
MOS sw. 0.1pF 1V
CLK
o When clock changes from high to low, Qch2 is injected to C
o Compared to ideal sw., MOS sw. creates voltage error on Vout
ELEN 622 Fall 2011 4 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
Decrease Charge Injection Effect (1)
CLK
Vout
W/L = 1/0.4 0.1pF 1V
W/L = 10/0.4
o Decrease the effect of Qch
o Use either bigger C or small TR. (small ratio of Cox/C)
o Increased Ron
ELEN 622 Fall 2011 5 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
Decrease Charge Injection Effect (2)
CLK CLKb
10/0.4 3.1/0.4 Vout
With dummy sw. 0.1pF 1V
Single sw.
o Use dummy switch which provides opposite charge o Adjust size of dummy sw. for exact canceling o Needs opposite clock
ELEN 622 Fall 2011 6 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
Decrease Charge Injection Effect (3)
CLK
10/0.4 Vout CMOS sw. 23/0.4 0.1pF 1V
CLKb NMOS sw.
o Use N/PMOS complementary switch
o Both Qch cancel out due to their opposite polarity o Needs opposite clock, increased parasitic capacitance
ELEN 622 Fall 2011 7 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
Nonlinear Ron
VDD Ron
7.5/0.4 1.5V
18/0.4 PMOS NMOS Vin
GND
N/PMOS
Vin
o Ron varies with signal amplitude o CMOS sw. can adopt large signal o Needs opposite clock, increased parasitic capacitance
ELEN 622 Fall 2011 8 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
Slow Settling due to high Ron
CLK CLKb
V1 Vout
20pF 10pF Vin
o Ron varies with signal amplitude o CMOS sw. can adopt large signal o Needs opposite clock, increased parasitic capacitance
ELEN 622 Fall 2011 9 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
Slow Settling due to high Ron
Vout Vout Ideal sw.
NMOS sw.
V1 V1
o Small NMOS sw. (5/0.4)
o With high Ron, output is not settled o In case of large signal input, N/PMOS sw. should be used
ELEN 622 Fall 2011 10 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
Slow Settling due to high Ron
Vout Vout Ideal sw.
NMOS sw.
V1 V1
o Large NMOS sw. (20/0.4)
o Low Ron makes output settled fast o Close to ideal sw.
ELEN 622 Fall 2011 11 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
Switch and Clock Arrangement
CKb
M5
C3 CK
M6 CKe CKbe
CK CKbe
C1 C M1 M2
CK CKb CKb CKe
M3 M4
C2
o M2, M4 : small sw., Others : large sw. o M2, M4 turn off earlier : minimize charge injection effect o Charge injection M2, M4 (M3, M6) : Signal independent Others : Signal dependent
ELEN 622 Fall 2011 12 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
Switch and Clock Arrangement
Ideal sw.
Different sw. (30/0.4, 5/0.4) Early CLK
Same sw. (5/0.4) Same CLK
ELEN 622 Fall 2011 13 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
PSS vs. Transient Simulation
fin = 10KHz PSS-PAC simulation
fin = 100KHz
fin = 200KHz o PSS simulation is used to check the frequency response for Switched-capacitor circuit o Should be compared with transient simulation
ELEN 622 Fall 2011 14 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
Capacitor Layout
Cfr
D D D D D
C fr D C1 C2 D D C fr C1 2 Cox = Cfr D C2 C1 C2 D C2 3
D D D D D
Cfr Cox Cfr
o Capacitor is implemented with PIP (poly) or MIM (metal)
o Total capacitance is the sum of Cox and Cfr’s o Ratio is more important than absolute value o Multiples of unit capacitor can minimize ratio error o Unit capacitor can be determined by process o Surrounding capacitor bank with dummies is preferred
ELEN 622 Fall 2011 15 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
Layout Example
o Example of SC biquad circuit (TSMC 0.35um)
ELEN 622 Fall 2011 16 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit Low Voltage Switched Capacitor Circuits
• Challenges of LV SC circuit GON design [cas95] – SC circuits are widely used in filters, data converters, sample and hold, and other analog signal processing VDD building blocks. V V -V – LV SC circuit design is very T,P DD T,N challenging due to the difficulties Switch conductance for high involved in turning on MOS VDD(such as 5V) switches. GON • Solutions – Low and/or multi Vt process VDD – Clock boostering or bootstrap – Switched opamp VDD-VT,N VT,P
Switch conductance for low VDD ELEN 622 Fall 2011 17 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
Low Voltage Switched Capacitor Circuits (Cont’d)
• Low and/or multi Vt process VDD [ada90] M2 2V – Expensive M1 DD – Switch leakage while it is off – Vt is not tightly controlled for low C1 C2 M3 Vt transistors • Clock boostering or bootstrap M4 – Earlier work ( see right figure ) required that transistors could 2VDD sustain maximum breakdown voltage of 2Vdd [nak91, cho95, VDD rab98] 0 0 – This could not be used in finer technologies due to reduced breakdown voltage
ELEN 622 Fall 2011 18 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
Low Voltage Switched Capacitor Circuits (Cont’d)
– Constant overdrive bootstrap clock driving solved this problem [abo99] – Reliability is improved as each transistor just sustains Vdd as maximum voltage – More power consumption and lower speed due to its complexity – Potential reliability problem during transient
VDD VDD Msw CB φ1 φ1 φ1 At φ1 A B CB φ1 At φ1 C Msw φ1 B A B A B
ELEN 622 Fall 2011 19 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
– Detailed schematic and wave form [abo99] • M1, M2, C1, C2 and the inverter could be shared by the switches with the same phase, other components need to be repeated for every switch.
M2 M3 VDD φ1
M1 M10 M8
M7 M4 C3 M13 C1 C2 M5 Msw φ1 φ1 M9 M12 A B
ELEN 622 Fall 2011 20 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
C • Switched opamp [cro94,bas97, FB pel98] C IN S4 – In conventional SC circuits, S1 is the critical switch, as it sees S1 wide signal swing S2 S3 – Switched opamp eliminated S1 by switching on and off the VREF amplifier Conventional SC circuits CFB – True low voltage operation – Potential of low power CIN S4 consumption – Slower speed ( usually clock S2 S3 freq. is around several KHz to 1
or 2 MHz ) due to the need to VREF switch on and off the opamp Switched opamp circuits ELEN 622 Fall 2011 21 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
• Low voltage also poses difficulties for designing the SC Opamps – To maximize output voltage swing, cascoding of output transistors should be avoided – To achieve required DC gain, two stage architecture may have to be used instead of single stage OTA – Frequency compensation is an essential issue to make the amplifier stable and fast settling – Input common mode bias voltage need to close one of the supply rails to make input transistors operate correctly ( close to Vss -- PMOS input; close to Vdd – NMOS input ) – Input and output need to be biased at different DC levels, level shift may be necessary for switched opamp circuits
ELEN 622 Fall 2011 22 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
• LV SC opamp design example I [abo99] – Two-stage architecture is adopted to achieve high enough gain – Simple output stage maximizes output voltage swing – First stage is folded-cascode stage with cascode load to obtain a high gain, as nodes A and B have a small signal voltage swing, and supplyV voltage=1.5 V and VTN permit this luxury DD M12 M4 M3 M5 M13
M6 M7 V Cc Cc VO- O+ VI+ VI- A M1 M2 B
M8 M9
M14 M10 M11 M15
ELEN 622 Fall 2011 23 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
– Cascode frequency compensation [ahu83] is used to have a higher bandwidth over conventinal Miller compensation
– The functionality of the circuit is independent of VIN_CM setting, thus VIN_CM could be set to a DC level which makes the amplifier work properly
Cf S1 VIN VOUT
S1 1.5b ADC 1.5b ADC Cs output
S1 VIN_CM
+V -V R 0 R The X2 residue amplifier for 1.5b/stage pipeline A/D converter
ELEN 622 Fall 2011 24 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
• LV SC opamp design example II [rab97] – Two-stage architecture with miller compensation – Push-pull operation of the second stage maximize driving capacity – Two common-mode feedback loops are required to stablize the bias condition
ELEN 622 Fall 2011 25 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
• LV SC opamp design example III [pel98] – One-stage architecture is used due to relaxed system requirement for the DC gain – Class AB operation lowers power consumption – Low voltage current mirror makes more room for the input transistors
ELEN 622 Fall 2011 26 / 27 Switched-Capacitor practical issues Practical Issues Designing Switched-Capacitor Circuit
References
[abo99] A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999 [ada90] T. Adachi, A. Ishikawa, A. Barlow, and K. Takasuka, “A 1.4 V switched capacitor filter,” IEEE CICC 1990, pp. 8.2.1-8.2.4, 1990 [ahu83] B. K. Ahuja, “An improved frequency compensation technique for CMOS operational amplifiers,” IEEE J. Solid-State Circuits, vol. SC-18, no. 6, pp. 629-633, Dec. 1983 [bas97] A. Baschirotto and R. Castello, “A 1-V 1.8-MHz CMOS switched-opamp SC filter with rail-to-rail output swing ,” IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1979-1986, Dec. 1997 [cas95] R. Castello, F. Montecchi, F. Rezzi, and A. Baschirotto, “Low-voltage analog filters,” IEEE Trans. Circuits and Systems – I, vol. 42, no. 11, pp. 827-840, Nov. 1995 [cho95] T. B. Cho and P. R. Gray, “A 10 b, 20 Msample/s, 35 mW pipeline A/D converter,” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166-172, March 1995 [cro94] J. Crols and M. Steyaert, “Switched-opamp: an approach to realize full CMOS switched- capacitor circuits at very low power supply voltages,” IEEE J. Solid-State Circuits, vol. 29, no. 8, pp. 936-942, Aug. 1994 [nak91] Y. Nakagome, et al. “An experimental 1.5-V 64-Mb DRAM,” IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 465-472, April 1991 [pel98] V. Peluso, P. Vancorenland, A. M. Marques, M. S. J. Steyaert, and W. Sansen, “A 900- mV low-power Σ∆ A/D converter with 77-dB dynamic range,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1887-1897, Dec. 1998 [rab97] S. Rabii and B. A. Wooley, “A 1.8-V digital audio sigma-delta modulator in 0.8 um CMOS,” IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 783-796, June 1997
ELEN 622 Fall 2011 27 / 27 Switched-Capacitor practical issues