ECE1371 Advanced Analog Circuits

Lecture 3 Switched-Capacitor Circuits

Trevor Caldwell [email protected] Circuit of the Day: Schmitt Trigger

Problem: Input is noisy or slowly varying

How do we turn this into a clean digital output?

2 ECE1371 Lecture Plan

Date Lecture (Wednesday 2-4pm) Reference Homework 2020-01-07 1 MOD1 & MOD2 PST 2, 3, A 1: Matlab MOD1&2 2020-01-14 2 MODN +  Toolbox PST 4, B 2:  Toolbox 2020-01-21 3 SC Circuits R 12, CCJM 14 2020-01-28 4 Comparator & Flash ADC CCJM 10 3: Comparator 2020-02-04 5 Example Design 1 PST 7, CCJM 14 2020-02-11 6 Example Design 2 CCJM 18 4: SC MOD2 2020-02-18 Reading Week / ISSCC 2020-02-25 7 Amplifier Design 1 2020-03-03 8 Amplifier Design 2 2020-03-10 9 Noise in SC Circuits 2020-03-17 10 Nyquist-Rate ADCs CCJM 15, 17 Project 2020-03-24 11 Mismatch & MM-Shaping PST 6 2020-03-31 12 Continuous-Time  PST 8 2020-04-07 Exam 2020-04-21 Project Presentation (Project Report Due at start of class)

3 ECE1371 What you will learn…

• Motivation for SC Circuits • Basic sampling switch and charge injection errors • Fundamental SC Circuits Sample & Hold, Gain and Integrator • Other Circuits Bootstrapping, SC CMFB

4 ECE1371 Why Switched-Capacitor?

• Used in discrete-time or sampled-data circuits Alternative to continuous-time circuits • Capacitors instead of resistors Capacitors won’t reduce the gain of high output impedance OTAs No need for low output impedance buffer to drive resistors • Accurate frequency response Filter coefficients determined by capacitor ratios (rather than RC time constants and clock frequencies) Capacitor matching on the order of 0.1% - when the transfer characteristics are a function of only a capacitor ratio, it can be very accurate RC time constants vary by up to 20%

5 ECE1371 Basic Building Blocks

• Opamps Ideal usually assumed Some important non-idealities to consider include: 1. DC Gain: sets the accuracy of the charge transfer, how ‘grounded’ the virtual ground is 2. Unity-gain freq, Phase Margin & Slew Rate: determines maximum clock frequency 3. DC Offsets: circuit techniques to combat this and 1/f noise – Correlated Double Sampling, Chopping • Capacitors Large absolute variation, good matching Large bottom plate capacitor adds parasitic cap

6 ECE1371 Basic Building Blocks

• Switches MOSFET switches are good – large off resistance (G), small on resistance (100 -5k, depending on transistor sizing) MOSFET switches have non-linear parasitic capacitors

• Non-Overlapping Clocks Clocks are never on at the same time Required so that charge is never lost/shared

7 ECE1371 Basic Sampling Switch

• MOSFET used as sample-and-hold

When CLK is HIGH, VOUT follows VIN through the low- pass filter created by RON and C

RON varies depending on VIN, VOUT, and VDD

When CLK is LOW, VOUT holds the value on C

8 ECE1371 On-Resistance Variation

• With an NMOS sampling switch, as VIN approaches VDD-VTH, RON increases dramatically

In smaller technologies, as VDD decreases the swing at VIN is severely limited ON 1 R  ON W  CVVV() noxL DD IN TH

IN VDD-VTH

Sampling switch must be sized for worst case RON so that the bandwidth is still sufficient

9 ECE1371 On-Resistance Variation

• PMOS switches suffer from the same problem as VIN approaches VTH • Complementary switch can allow rail-to-rail input swings

Ignoring variation of ON,n ON,p V with V , R is TH IN ON,eq RON,p constant with VIN if R WW  ON,n noxCC pox  LLnp 

IN TH DD TH DD

10 ECE1371 On-Resistance Variation

• In smaller technology nodes, VDD is dropping faster than VTH

In small planar technology nodes VDD ~ |VTH,P| + VTH,N

• New technologies introduce different VTH options Designers can optimize their circuits with choice of VTH Ex. HVT, SVT, LVT

• FinFET technology VTH Due to superior gate control, VTH is a smaller fraction of VDD Improved subthreshold slope

11 ECE1371 Settling Accuracy

• Two situations to consider 1. Discrete-time signal When analyzing a signal within a switched-capacitor circuit (for example, at the output of the first OTA) 2. Continuous-time signal When analyzing a signal that is sampled at the input

12 ECE1371 Settling Accuracy - DT

• Discrete-Time Signal Settle in T/4 seconds Settling Error = e-T/4RC For N-bit accuracy T RC ON 4ln2N

This is the maximum RON (for a given C) • Example: 1 Assume 1 GHz to 4 GHz variation of 2 RC Input sinusoidal signal at 50 MHz ON

For fS=100 MHz, N=22 bits with discrete-time signal (typically you are limited by the OTA)

13 ECE1371 Settling Accuracy - CT

• Continuous-Time Signal

RONC acts as a low-pass filter and introduces amplitude and phase change Variations in the input signal size cause variations in RON, causing distortion in the sampled signal • Input ~50 MHz, sampled 0 at 100MHz -20 57dB distortion, or ~9 bits -40 This is larger than the -60 maximum variation in dBFS -80 amplitude (phase error must be significant) -100

-120 0 0.1 0.2 0.3 0.4 0.5 Normalized Frequency

14 ECE1371 Amplitude Error

• Variation in RC filter magnitude

RON varies depending on input voltage, causes amplitude through RC filter to be signal dependent

At 50 MHz (with same RONC variation as DT case), maximum variation in amplitude is 0.1%

15 ECE1371 Phase Error

• Variation in RC filter phase

RON varies depending on input voltage, causes phase shift through RC filter to be signal dependent

At 50 MHz (with same RONC variation as DT case), maximum variation is a few percent (error is less than that)

16 ECE1371 Charge Injection

• When a transistor turns off, the channel charge QCH goes into the circuit Doesn’t exactly divide in half - depends on impedance seen at each terminal and the clock transition time

QWLCVVVCH ox() DD IN TH

• Charge into VIN has no impact on output node Doesn’t create error in the circuit

• Charge into C causes error V in VOUT Q V CH 2C WLC() V V V  ox DD IN TH 2C

17 ECE1371 Charge Injection

• In previous analysis, charge injection introduces a gain and offset error This is still linear and could be tolerated or corrected

VVOUT IN V

WLCox WLC ox() V DD V TH VIN 1  22CC • But…

VTH is actually a function of ~ VIN Introduces non-linear term that cannot be corrected in the circuit

18 ECE1371 Charge Injection vs. Speed

• Charge injection Proportional to transistor size (WL) • Speed

RON inversely proportional to aspect ratio (W/L) • Figure of Merit Product of speed (1/) and charge injection (1/V)

1 1 1 C WLCox ()VVVV (DD  IN TH ) noxCWLV(/)( DDINTH V V )  C   n L2

19 ECE1371 Clock Feedthrough

• Overlap capacitance allows clock to couple from the gate to drain/source terminals Change in voltage V independent of the input signal Error is an offset voltage which is cancelled with differential operation

VCLK 0 OV OV Cov IN OUT VVCLK CC ov

20 ECE1371 Charge Error Cancellation

• Differential operation Cancels offset errors, depending on the matching between differential circuits Applies to signal independent portion of charge injection error, and clock feedthrough error

• Complementary Switches Error cancelled for 1 input level

WLCVn n ox()() CLK V IN V TH,, n  WLCVV p p ox IN  TH p Clock feedthrough cancelled depending on similarity of overlap capacitance for PMOS and NMOS switches

21 ECE1371 Charge Error Cancellation

• Dummy Switch Use second transistor to remove charge injection by main transistor Inverted clock operates on dummy switch

Charge from M1: qWLCVVVMoxCKINTH111()/2 1

Charge from M2: qWLCVVVMoxCKINTH222() 2 If charge splits equally in M1 (not quite true), then with

M2 half the size of M1, qqMM12

22 ECE1371 Sample and Hold Amplifier

• Input dependent charge from S1 onto C

When S1 turns off, charge q adds to C

VOUT is then equal to VIN+q/C where q has a non-linear dependence on VIN

We can improve on this by making VOUT independent of input-dependent charge…

23 ECE1371 S/H Amplifier

• Two phases

Phase 1: S1 and S2 closed, VIN sampled on C

Phase 2: S3 closed, C is tied to VOUT • Phase 1

Charge on C is CVIN

S2 opens, injecting signal independent charge at node X

Then S1 opens, injecting signal dependent charge q onto C + Cp

24 ECE1371 S/H Amplifier

• Phase 2

S3 closes, node X is a virtual ground

Charge on Cp is zero, charge on C is still CVIN

S3 injects charge on X that must be discharged due to virtual ground node – it does not disturb charge on C VOUT = VIN

S1 / S3 are non-overlapping, S2 slightly ahead of S1

25 ECE1371 Gain of the S/H

• Finite OTA gain reduces gain of sampler

On Phase 1, C charges to VIN

On Phase 2, node X goes from 0 to VX = -VOUT/A

Charge comes from C, changing qC to CVIN + CpVX

VOUT -(CVIN + CpVX)/C = VX

VIN VOUT  1 Cp 11 AC

1 Cp VIN 11  AC

26 ECE1371 Speed of the S/H

• In sampling mode (Phase 1)

At node X, RX ~ 1/GM , 1 ~ (Ron1+1/GM)C • In amplification mode (Phase 2)

Replace charge on C by voltage source VIN (like switching in voltage source at start of Phase 2)

After analysis, 2 = (CLCp+CpC+CCL)/GMC

Reduces to 2 ~ CL/GM if Cp is small

27 ECE1371 Basic Amplifier

• Sampling phase when S1 and S2 closed

Input signal sampled onto C1

• Amplifying phase when S3 closed

Charge on C1 transferred to C2 so that the final output is C1 VVOUT IN C2

28 ECE1371 Basic Amplifier

• S2 must open before S1 for the charge injection to be signal independent

Charge from S2 opening is deposited on C1, but is not signal dependent

Charge from S1 opening causes glitch in VOUT

When S3 closes, VOUT goes to final value, regardless of what happened between S2 opening and S3 closing

29 ECE1371 Precision Gain-2

• Sampling phase when S1, S2, S3 closed

Input signal sampled onto C1 and C2

• Amplifying phase when S4, S5 closed

Charge on C1 is transferred to C2 , doubling the charge on C2

Final output is 2VIN since C1 = C2

30 ECE1371 Precision Gain-2

• How is it more precise? The feedback factor in both gain circuits is

C2

CCC21p

In the precision Gain-2 circuit, C1 = C2

The basic amplifier has C1 = 2C2, resulting in a smaller feedback factor and a slower circuit The gain error is inversely proportional to the feedback factor, so the precision circuit is more accurate for a given amplifier gain A

VOUT CCC21p 21 VACIN 2

31 ECE1371 Integrators: Resistor Equivalence of SC

• Average current through switched-capacitor

11::QCVQCV 12  2  2 QQ CVV() I 12 12 AVG TT

• Equivalent current through a resistor (fIN << fS)

VV12 T 1 IEQ  REQ  REQ CCfS 32 ECE1371 Switched-Capacitor Integrator

• Two non-overlapping clock phases control S1,S2 Phase 1: Sampling phase – input is sampled onto capacitor C1 Phase 2: Integrating phase – additional charge is added to previous charge on C2

33 ECE1371 Switched-Capacitor Integrator 1 1 2 2 [n]C [n]C I I -V +V 2 [n]C 2 [n]C O O -V +V [n]C [n]C O O -V +V

• Final charge on L.S. of C2 is +VO[n+1]C2

VnOOI[1] C221 VnC [] VnC []

zVOOI() zC221 V () zC V () zC VC1 O ()z  1 VCzI 2  1

34 ECE1371 Parasitic Sensitive

• Parasitic capacitances Cp1, Cp3 and Cp4 have no impact on transfer function

• Cp2 in parallel with C1, changes transfer function V ()CC 1 O ()z  12p VCzI 2  1

35 ECE1371 Parasitic Insensitive

• Transfer function is non-inverting, delaying

VC1 O ()z  1 VCzI 2  1

36 ECE1371 Parasitic Insensitive

• Parasitics have no impact on transfer function Better linearity since non-linear capacitors are unimportant • Top plate on virtual ground node Minimizes parasitics, improves amplifier speed and resolution, reduces noise coupled to node • Two extra switches needed More power to drive the switches for the same on- resistance

37 ECE1371 Delay-Free Integrator

• Same structure, still parasitic insensitive • Transfer function is inverting, delay-free

VCz O ()z  1 VCzI 2  1

38 ECE1371 Bootstrapping

• At low supply voltages, signal swing is limited Maximum distortion determines the tolerable variation in RON, and this limits the signal swing

• Want to increase VGS on the sampling switch Can do this by increasing the supply voltage for the sampling switch, but this requires slower thick oxide devices Alternatively, add a constant voltage to the input signal and use that as the gate voltage – keep VGS constant, reducing the variation in RON

39 ECE1371 Bootstrapped Circuit

• Basic operation

2: C is charged to VDD and gate of sampling switch is discharged to VSS (turned off)

1: VIN is added to voltage across C, sampling switch turns on, gate voltage of the sampling switch SS DD is VIN + VDD

2 2 Ideally, there is 1 2 always VGS = VDD 3 4 for the sampling 1 1 2 SS switch 5

IN OUT

40 ECE1371 Bootstrapped Circuit

• C must be sized so that charge sharing between gate capacitance of switch is not significant C VVVGINDD() CC G

• Rise time controlled by size of S4, fall time controlled by size of S5

• Extra transistors required to limit gate-source voltages to VDD and prevent overstress See Dessouky, JSSC Mar.2001

41 ECE1371 Switched-Capacitor CMFB

• Two parts to a CMFB circuit 1. Sense the common mode of the output 2. Compare the common mode to the expected common mode, and adjust the bias accordingly • Sensing Could use 2 resistors – they are either too small and reduce the gain, or they can get prohibitively large Could use 2 capacitors – they don’t reduce the gain, but the voltage across them is undefined and must be refreshed every clock cycle

42 ECE1371 Switched-Capacitor CMFB

• One alternative…

Phase 1: precharge VB1 capacitors to ideal value 2 C C 2 Phase 2: sense the difference and 1 1 VCM VCM adjust the bias accordingly VIN+VIN-

1 VB2 CP

But… there may be large changes in the tail current bias

43 ECE1371 Switched-Capacitor CMFB

• Alternatively, use 2 capacitors so that only a fraction of the charge is shared to adjust the bias voltage

Typically, C2 is 4-10 times C1

VB1

1 2 2 1 VCM VCM

C1 C2 C2 C1 1 2 2 1 VB2 VB2

VIN+VIN-

CP

44 ECE1371 What You Learned Today

• Errors introduced with simple sampling switch

RON variation, charge injection • Main SC Circuits – S/H, Gain and Integrators Parasitic Insensitive Signal-independent charge injection • Bootstrapped Circuit • Switched Capacitor CMFB

45 ECE1371 Circuit of the Day: Schmitt Trigger

46 ECE1371