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High-Accuracy Switched-Capacitor Techniques for Filter and ADC Design HIGH-A CCURACY S WITCHED-C APACITOR T ECHNIQUES APPLIED T O F ILTER A ND ADC D ESIGN High-Accuracy Switched-Capacitor Techniques for Filter and ADC Design PATRICK J OHN Q UINN Cover design: different capacitor implementations are shown for various SC circuits; background is a SEM image of the cross-section of a high-density metal filament capacitor in 65nm CMOS. © Patrick John Quinn: 2006 All rights reserved. Reproduction in whole or in part is prohibited without the written consent of the copyright owner. Printing: Printservice TU/e HIGH-A CCURACY S WITCHED-C APACITOR T ECHNIQUES APPLIED T O F ILTER A ND ADC D ESIGN High-Accuracy Switched-Capacitor Techniques for Filter and ADC Design PROEFSCHRIFT ter verkrijging van de graad van doctor aan de Technische Universiteit Eindhoven, op gezag van de Rector Magnificus, prof.dr.ir. C.J. van Duijn, voor een commissie aangewezen door het College voor Promoties in het openbaar te verdedigen op woensdag 13 september 2006 om 16.00 uur door Patrick John Quinn geboren te Dublin, Ierland Dit proefschrift is goedgekeurd door de promotor: prof.dr.ir. A.H.M. van Roermund Samenstelling promotiecommissie: prof.dr.ir. J.H. Blom (Voorzitter) prof.dr.ir. A.H.M. van Roermund (Promotor) prof. ir. A.J.M. van Tuijl (UT) prof.dr.ir. G.C.M. Meijer (TUD) prof.dr.ir. P.G.M. Baltus prof.dr.ir. J.W.M. Bergmans prof.dr.ir. R.H.J.M. Otten dr.ir. J.A. Hegt CIP-DATA LIBRARY TECHNISCHE UNIVERSITEIT EINDHOVEN Quinn, Patrick J. High-accuracy switched-capacitor techniques applied to filter and ADC design / by Patrick John Quinn. – Eindhoven : Technische Universiteit Eindhoven, 2006. Proefschrift. – ISBN-10: 90-386-1813-1 ISBN-13: 978-90-386-1813-5 NUR 959 Trefw.: geschakelde capaciteiten / elektronische filters / analoog-digitale conversie / CMOS- schakelingen. Subject headings: switched capacitor filters / analogue-digital conversion / CMOS integrated circuits /mixed analogue-digital integrated circuits. To Orla, Siobhán, and my parents ABSTRACT Abstract In this thesis, innovative techniques are proposed as alternatives to traditional switched- capacitor (SC) charge-transfer techniques for the more accurate creation of key functions such as required for analogue signal conditioning and data conversion. Active charge transport with the help of an amplifier is replaced by passive ( delta ) charge redistribution with reduced dependency on capacitor mismatch and with the amplifier used predominantly for buffering. Orthogonal hardware modulation is used in conjunction with N-path filtering, thus achieving very high accuracy, while preventing the problem of pattern noise. A floating-hold buffer is proposed which enables accurate addition of signal voltages without requiring precisely matching and linear components. The new methods have been applied to the design of CMOS SC bandpass filters and algorithmic ADC stages (both cyclic and pipelined). The intrinsic accuracies achieved go beyond those achieved with previous state-of-the-art solutions with a consequent reduction in power for the same speed applications. x Abstract CONTENTS Contents Abstract1 ix Contents2 xi List3 of Symbols and Abbreviations xvii Symbols . xvii Abbreviations . xix Chapter1 1: Introduction 1 1.1 Cost-Performance Trade-offs in IC Design . 1 1.2 Modern IC Design Challenges . 2 1.2.1 Digital IC Design Challenges . 3 1.2.2 Analogue IC Design Challenges . 4 1.2.3 Test Challenges . 4 1.2.4 Process and Design Work-Arounds . 5 1.3 Switched Capacitors for analogue Signal Conditioning. 5 1.4 Key Points for High Performance SC Design . 6 1.5 Scope of thesis . 7 1.6 Outline of thesis . 7 Chapter2 2: Key Concepts for Accurate SC Design 9 2.1 Orthogonal Design Procedures in Filter and ADC Realizations . 9 2.2 Delta Charge Flow SC Techniques. 10 2.2.1 The Sample-And-Hold Stage: Voltage Buffer . 12 2.2.2 The Delta-Charge-Redistribution Stage: Voltage Down-Scaler . 13 2.2.3 C+C Concept: Voltage Up-Scaler. 14 2.3 The Floating-Hold-Buffer. 14 2.4 Conclusions. 15 Chapter3 3: SC Amplifier Design at Black-Box Level 17 3.1 Amplifier Design Considerations . 17 xii Contents 3.2 The Settling Error Model . 18 3.2.1 Static Error . 18 3.2.2 Dynamic Error . 19 3.3 Design Procedure for Optimized Settling. 22 3.3.1 Single-Ended or Fully-Differential. 22 3.3.2 Capacitor Sizes . 24 3.3.3 OTA Architecture . 24 3.3.4 Choice of Von . 25 3.3.4.1 OTA Transconductance. 25 3.3.4.2 Matching Considerations. 27 3.3.4.3 Influence of Channel Mobility Factor . 28 3.3.4.4 Choice of Gate Lengths . 29 3.3.5 Minimum Settling Time Constant and Bias Current . 29 3.4 OTA Slewing Requirement in SC Applications. 31 3.4.1 The Slew Rate Model . 31 3.4.2 Minimum OTA Tail Current for No Slewing. 32 3.4.3 Calculation of Slew Time, tslew . 33 3.4.4 Dynamic Settling Error including OTA Slewing . 35 3.5 Conclusions . 36 4Chapter 4: Amplifier Architectures for SC Applications 37 4.1 Review of Amplifier Architectures . 37 4.1.1 Primary OTA Stages. 37 4.1.1.1 Telescopic OTA. 37 4.1.1.2 Current Mirror OTA . 39 4.1.1.3 Folded OTA. 41 4.1.1.4 General Conclusions for the Three Primary OTA Stages . 42 4.1.2 OTA Cascade Stages. 43 4.1.2.1 Pre-buffer Stage. 43 4.1.2.2 Pre-gain Stage . 44 4.1.2.3 Miller Output Stage . 45 4.1.2.4 Ahuja Output Stage . 46 4.2 The Dual-Input Telescopic OTA . 48 4.2.1 The SC Single-Input Telescopic OTA . 49 4.2.2 SC DITO Architectures. 50 4.2.3 Design Considerations . 52 4.2.4 Amplifier Noise . 53 4.2.5 Signal Range . 54 4.3 Cascode Frequency Response Design Issues . 55 4.3.1 The Effect of Cascoding on the Closed-Loop Settling Response. 55 4.3.2 Low Frequency Miller Multiplication . 58 4.3.3 Neutralization . 59 Contents xiii 4.4 Boosting the gm of a Cascode Stage using Active Feedback . 60 4.4.1 The RGC with High Frequency Design Considerations . 60 4.4.2 Reducing Low Frequency Miller Multiplication . 63 4.5 Low Voltage High Frequency RGC Architectures. 64 4.5.1 Suitability of RGCs for Low Voltage . 64 4.5.2 LV RGC using Level Shift Buffers. 64 4.5.3 LV RGC using Folded Cascode Voltage Sensing. 65 4.5.4 LV RGC using Dynamic Biasing . 66 4.6 OTA DC Gain Improvement using Partial Positive Feedback . 67 4.6.1 OTA Design Strategy . 68 4.6.2 Circuit Implementation of Partial Positive Feedback . 69 4.7 Optimization of SC Settling Response with Inclusion of Feedback Loop Switches 70 4.7.1 Effect on Settling of Switch Resistance in OTA Feedback Loop . 71 4.7.2 Switch Design Strategy for Speed-up . 72 4.8 Conclusions. 76 Chapter5 5: Low-Sensitivity SC BPF Concepts 77 5.1 Sensitivity comparison of SC and CT Filters . 77 5.2 BPF Function Including Hardware Imperfections . 79 5.3 SC BPF Based on.
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