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Switched-Capacitor Networks for Implementation Switched-Capacitor Networks for Image Processing: Analysis, Synthesis, Response Bounding, and Implementation by Mark N. Seidel S.B. (EE & CS), Massachusetts Institute of Technology (1985) S.M. (EE & CS), Massachusetts Institute of Technology (1985) Submitted to the Department of Electrical Engineering and Computer Science in partial fulfillment of the requirements for the degree of Doctor of Science at the MASSACHUSETTS INSTITUTE OF TECHNOLOGY February 1994 @ Massachusetts Institute of Technology 1994 Signature of Author Department of Electrical Engineering and Computer Science January 29, 1994 Certified by John L. Wyatt, Jr. Professor S // Thesis Supervisor Certified by 'omas T F. Knight, Jr. Principal Research Scientist I A Thesis Supervisor Accepted by - MASSaC, CH(,STu-S TS !PE Frederic R. Morgenthaler ' "•:"ihairman, Dep rtmental Committee on Graduate Students APR 06 1994 Switched-Capacitor Networks for Image Processing: Analysis, Synthesis, Response Bounding, and Implementation by Mark N. Seidel Submnitted to the Department of Electrical Engineering and C(omputer Science on January 29, 1994, in partial fulfillment of the requirements for the degree of Doctor of Science Abstract This thesis presents aspects of analysis and synthesis of linear and nonlinear steady- state switched-capacitor (SC) networks. Though the application area stressed is early vision image processing, the results and strategy apply to other areas involving linear and nonlinear resistive networks, such as coupled-equation solvers. Foundational results involve translating between (a) continuous-time networks con- taining nonlinear capacitors, ideal voltage sources, and nonlinear resistive MOSFET- based switches, and (b) stable discrete-time systems embodied by ideal SC networks. In addition, steady-state source transferred charges are shown to be independent of initial capacitor voltages. Finally, step-response bounds and estimates are found for a large class of such discrete-time systems; these bounding expressions are presented in direct and inverted forms, and are shown to tend towards the continuous-time RC-tree bounds in the appropriate limits. Resistive equivalent circuits are found for arbitrary passive SC networks in steady- state, with the emphasis being on element equivalences. These analysis results are com- pared with currently available analysis techniques, and are used to explain several aspects of multiple-frequency networks (i.e., SCl networks with multiple clock phases, where the intention is to control relative conductance values through the control of relative switch- ing frequencies). In the reverse direction, this thesis includes a general strategy for synthesizing a SC network given a resistive network comprised of two-terminal resistors, two-port lossy transformers, multiterminal and multiport lossy generalized circulators, and several types of resistive constraint boxes. The analysis and synthesis results are extended to certain classes of nonlinear SC networks. Analysis of SC networks containing nonlinear capacitors follows the same conceptual framework as the linear theory, and the class of networks that can be syn- thesized is broadened to include two-terminal voltage-controlled nonlinear resistors. The nonlinear analysis and synthesis results are applied to resistive fuse networks for image smoothing and segmentation. In the last portion of the thesis, the analysis and synthesis results are discussed in the context of a designed, fabricated, and tested VLSI circuit implementation of the one- dimensional coupled depth and slope network for surface reconstruction. This network combines information from different early vision modules to yield a dense representation of a surface. The 13-section linear SC network was fabricated in a 2,m double-poly CMOS process, and includes compensation for parasitic capacitances associated with both plates of the floating capacitors. The experimental results agree quite closely with the analysis theory, both for the case of parasitic capacitance compensation as well as with the compensation disabled. This disabling also demonstrates that the compensation is effective in approaching the expected results for ideal SC networks. Finally, it is argued and experimentally demonstrated that compensation for clock feedthrough and channel charge is unnecessary in the interior of the networks designed, resulting in a more compact and simpler layout. Thesis Supervisor: John L. Wyatt, Jr. Title: Professor Thesis Supervisor: Thomas F. Knight, Jr. Title: Principal Research Scientist Acknowledgments First, I deeply thank my two thesis supervisors, John Wyatt and Tom Knight. Their patient tutoring and endless stream of ideas contributed greatly to the content and pre- sentation of this work. I am thrilled to call each of them advisor and friend. Jacob White, the third member of the committee, was a constant source of advice, ideas, and support. Many thanks to all three. Cam Searle and Marilyn Pierce made the administrative side of things absolutely painless, allowing me to fully concentrate on the academics and research. .Jim Roberge deserves a special thanks. Always with a wave and a grin, opinionated and supportive, never too busy to stop and chat, I count him a treasure. My office and floor mates are too numerous to mention, but special thanks go to Miguel, Bob, Ricardo, and Abe. Hi Mom! Hi Dad! Can you believe it? Thanks for everything. Robert, Rulthanna, Timothy, and Christina have been so loving to their Daddy. They teach inme every (lay to stop and savor life. What a gift they are! Most importantly, I dedicate this thesis to my wife, Katja, my beloved. Throughout our married life together, she has given of herself to support mine, never being satisfied with second-best in our marriage, family, and understanding of our life and faith in Christ .Jesus. Babe, you're the greatest! This work was supported by the National Science Foundation and the Advanced Research Projects Agency under NSF Grant MIP-91-17724, NSF and ARPA Contracts MIP-88-14612, and ARPA Contract N0014-91-.J-1698. Contents 1 Introduction and Background 1.1 Early Vision Image Processing . ............ 1.2 Implementing Image Processing Algorithms 1.2.1 Smoothing and Segmentation ......... 1.2.2 The Coupled Depth and Slope Network . 1.3 Other Applications: Coupled-Equation Solvers . 1.4 Switched-Capacitor (SC() Implementation ....... 1.4.1 SC Implementation Advantages ........ 1.4.2 Basic SC' Resistors ............... 1.4.3 SC Circuits and Discrete-Time (DT) Systems 1.5 Bounding the Network Step-Response . ........ 1.5.1 Continuous-Time (CT) Step-Response Bounds 1.5.2 Step-Response Bounds and M-matrices 1.6 Steady-State SC Analysis and Synthesis 1.6.1 Equivalent-(Circuit SC Analysis Techniq lies . 1.6.2 UImminger's Steady-State Networks . 1.6.3 Novel Linear SC Elements ....... 1.6.4 Nonlinear SC Elements and Networks . 1.7 Synopsis ..................... 2 Foundations: From CT SC Circuits to Stable DT Systems 2.1 Fundamental Questions . ............ 2.2 (lharacteristics of SC Networks Studied . 2.2.1 Topological Constraints 2.2.2 SC Network (Classes . .......... 2.3 M ain Results 2.4 Ideal SC Network Clocking and Notation . 2.4.1 Ideal SC Network Clocking Scheme . 2.4.2 Discrete-Time System Notation . 2.4.3 The Linear Discrete-Time System . 2.5 Ideal Linear SC Network Long-Term Stability 2.5.1 Ideal Linear G(rounded SC Networks 2.5.2 Long-Term Stability Issues of SC' Loops . CONTENTS 2.5.3 Ideal Linear Bridging SC Networks .. .... 2.6 Real SC Network Characteristics . .. 2.6.1 General Class .............. 2.6.2 Element Descriptions ............. 2.6.3 Clock Description ............... 2.6.4 Classes of Real SC Networks ......... 2.7 Clock Phase Stability of Real SC Networks ..... 2.7.1 Passivity WRT an Operating Point ..... 2.7.2 The System Differential Equation ...... 2.7.3 Stability of the System .... ........ 2.7.4 Clock-Phase Uniqueness .. ........ 2.8 Real SC Network Properties .... ...... ... 2.8.1 Replacement with Ideal Switches ...... 2.8.2 Irrelevancy of Switch Closing Times ...... 2.8.3 Clock Timing ................. 2.8.4 System State ................ 2.9 Energy Considerations of Real SC Networks . 2.9.1 Clock-Phase Stability .. ........ ... 2.9.2 Switch Dissipated Energy .. ..... ... 2.9.3 General Energy Expressions and Results .. 2.10 Steady-State Transferred Charge Uniqueness . .. 2.11 Sum m ary .. ...... ...... .. ... 3 Step-Response Bounds for Ideal Linear Grounded SC Networkss 85 3.1 Notation and Definitions .... .. ......... .... 85 3.2 System Formulation ... ... ............. ... 86 3.3 The M ain Result ................... •.. .. , •.. , • .... 87 3.4 Some Introductory Examples ............ .. ., ... °.. .... 90 3.5 Useful Facts and Lemmas .............. ... 94 3.6 The Reduced-Order Model .... ......... ... 98 3.7 Determining Step-Response Bounds ...... ... ... 101 3.7.1 Basic Idea ..... ........ ...... .... 101 3.7.2 Algorithms for Deriving the Bounds ..... ... 102 3.7.3 Floor and Ceiling Functions ..... .... .... 104 3.7.4 Determining ni n .... .... .... .... .... 105 3.7.5 Determining nmax ............... .... 107 3.8 Proof of the Main Result (Bounding Expressions) . ... 113 3.9 Inverting the Bounding Expressions .. ...... ... 114 3.9.1 Inverting n•,in.. ................. .... 114 3.9.2 Inverting nmax. ................. .... 117 3.9.3 Combined Inversion . ...... ..... .. ... 123 3.10 Proof of the Main Result (Inverted Bounding Expressions) .. 124 3.11 Tightening the Bounds .................... ... 124 3.12 Discrete-Time
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