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ECE 410: VLSI Design Course Lecture Notes (Uyemura Textbook)

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ECE 410: VLSI Design Course Lecture Notes (Uyemura Textbook) ECE 410: VLSI Design Course Lecture Notes (Uyemura textbook) Professor Andrew Mason Michigan State University ECE 410, Prof. A. Mason Lecture Notes Page 2.1 CMOS Circuit Basics • CMOS = complementary MOS drain source – uses 2 types of MOSFETs gate gate to create logic functions •nMOS source drain nMOS pMOS •pMOS • CMOS Power Supply VDD CMOS – typically single power supply + CMOS VDD logic = – VDD, with Ground reference - logic circuit circuit • typically uses single power supply • VDD varies from 5V to 1V V •Logic Levels VDD logic 1 – all voltages between 0V and VDD voltages – Logic ‘1’ = VDD undefined – Logic ‘0’ = ground = 0V logic 0 voltages ECE 410, Prof. A. Mason Lecture Notes Page 2.2 Transistor Switching Characteristics •nMOS drain Vout nMOS –switching behavior gate • on = closed, when Vin > Vtn Vin nMOS – Vtn = nMOS “threshold voltage” + Vgs > Vtn = on Vgs – Vin is referenced to ground, Vin = Vgs - source • off = open, when Vin < Vtn •pMOS + source pMOS –switching behavior Vsg • on = closed, when Vin < VDD - |Vtp| - pMOS – |Vtp| = pMOS “threshold voltage” magnitude Vin Vsg > |Vtp| = on gate – Vin is referenced to ground, Vin = VDD-Vsg Vsg = VDD - Vin • off = open, when Vin > VDD - |Vtp| drain Rule to Remember: ‘source’ is at • lowest potential for nMOS • highest potential for pMOS ECE 410, Prof. A. Mason Lecture Notes Page 2.3 Transistor Digital Behavior •nMOS drain Vout nMOS Vin Vout (drain) gate Vin nMOS 1 Vs=0 device is ON + Vgs > Vtn = on 0 ? device is OFF Vgs - source •pMOS Vin Vout (drain) pMOS + source 1 ? device is OFF Vsg 0 Vs=VDD=1 device is ON - pMOS Vin Vsg > |Vtp| = on gate Vsg = VDD - Vin Vin drain pMOS Vout VDD off VDD-|Vtp| on Notice: on When Vin = low, nMOS is off, pMOS is on When Vin = high, nMOS is on, pMOS is off Vtn off Æ Only one transistor is on for each digital voltage nMOS ECE 410, Prof. A. Mason Lecture Notes Page 2.4 MOSFET Pass Characteristics • Pass characteristics: passing of voltage from drain (or source) to source (or drain) when device is ON (via gate voltage) • Each type of transistor is better than the other at passing (to output) one digital voltage – nMOS passes a good low (0) but not a good high (1) – pMOS passes a good high (1) but not a good low (0) VDD VDD + nMOS Vgs=Vtn Passes a good low ON when gate 0 V ? VDD ?- Max high is VDD-Vtn is ‘high’ Vy = 0 V Vy = VDD-Vtn 0 V 0 V - pMOS Vsg=|Vtp| Passes a good high ON when gate VDD ? 0 V ? + Min low is |Vtp| is ‘low’ Vy = VDD Vy = |Vtp| Rule to Remember ‘source’ is at lowest potential for nMOS and at highest potential for pMOS ECE 410, Prof. A. Mason Lecture Notes Page 2.5 MOSFET Terminal Voltages • How do you find one terminal voltage if the other 2 are known? –nMOS • case 1) if Vg > Vi + Vtn, then Vo = Vi (Vg-Vi > Vtn) Vo – here Vi is the “source” so the nMOS will pass Vi to Vo Vg • case 2) if Vg < Vi + Vtn, then Vo = Vg-Vtn (Vg-Vi < Vtn) – here Vo is the “source” so the nMOS output is limited Vi For nMOS, max(Vo) = Vg-Vtn –pMOS • case 1) if Vg < Vi - |Vtp|, then Vo = Vi (Vi-Vg > |Vtp|) Vi – here Vi is the “source” so the pMOS will pass Vi to Vo Vg • case 2) if Vg > Vi - |Vtp|, then Vo = Vg+|Vtp| (Vi-Vg < |Vtp|) Vo – here Vo is the “source” so the pMOS output is limited For pMOS, min(Vo) = Vg+|Vtp| IMPORTANT: Rules only apply if the devices is ON (e.g., Vg > Vtn for nMOS) ECE 410, Prof. A. Mason Lecture Notes Page 2.6 MOSFET Terminal Voltages: Examples –nMOSrules max(Vo) = Vg-Vtn • case 1) if Vg > Vi + Vtn, then Vo = Vi (Vg-Vi > Vtn) • case 2) if Vg < Vi + Vtn, then Vo = Vg-Vtn (Vg-Vi < Vtn) •nMOSexamples (Vtn=0.5V) Vo 2 1.5 Vo – 1: Vg=5V, Vi=2V acts as • Vg=5 > Vi +Vtn = 2.5 ⇒ Vo = 2V Vg5 Vg2 the source – 2: Vg=2V, Vi=2V • Vg=2 < Vi+Vtn = 2.5 ⇒ Vo = 1.5V 2Vi source 2Vi –pMOSrules min(Vo) = Vg+|Vtp| • case 1) if Vg < Vi - |Vtp|, then Vo = Vi (Vi-Vg > |Vtp|) • case 2) if Vg > Vi - |Vtp|, then Vo = Vg+|Vtp| (Vi-Vg < |Vtp|) •pMOSexamples (Vtp=-0.5V) – 1: Vg=2V, Vi=5V 5Vi source 2Vi • Vg=2 < Vi-|Vtp|=4.5 ⇒ Vo = 5V Vg2 Vg2 acts as – 2: Vg=2V, Vi=2V the source • Vg=2 > Vi-|Vtp|=1.5 ⇒ Vo = 2.5V Vo 52.5Vo ECE 410, Prof. A. Mason Lecture Notes Page 2.7 Switch-Level Boolean Logic • Logic gate are created by using sets of controlled switches • Characteristics of an assert-high switch nMOS acts like an assert-high switch – y = x • A, i.e. y = x if A = 1 AND, or multiply function Series switches ⇒ AND function Parallel switches ⇒ OR function a AND b a OR b ECE 410, Prof. A. Mason Lecture Notes Page 2.8 Switch-Level Boolean Logic • Characteristics of an assert-low switch pMOS acts like an y=x y=? assert-low switch – y = x • A, i.e. y = x if A = 0 error in figure 2.5 Series assert-low switches ⇒ ? NOT function, combining assert- a b high and assert-low switches NOT (a OR b) NOR Remember This?? a=1 ⇒ SW1 closed, SW2 open ⇒ y=0 = a a • b = a + b, a + b = a • b DeMorgan relations a=0 ⇒ SW1 open, SW2 closed ⇒ y=1 = a ECE 410, Prof. A. Mason Lecture Notes Page 2.9 CMOS “Push-Pull” Logic • CMOS Push-Pull Networks –pMOS assert-low pMOS •“on”when input is low logic • pushes output high inputs output –nMOS assert-high •“on”when input is high logic nMOS • pulls output low • Operation: for a given logic function – one logic network (p or n) produces the logic function and pushes or pulls the output – the other network acts as a “load” to complete the circuit, but is turned off by the logic inputs – since only one network it active, there is no static current (between VDD and ground) •zero static power dissipation ECE 410, Prof. A. Mason Lecture Notes Page 2.10 Creating Logic Gates in CMOS • All standard Boolean logic functions (INV, NAND, OR, etc.) can be produced in CMOS push-pull circuits. • Rules for constructing logic gates using CMOS – use a complementary nMOS/pMOS pair for each input – connect the output to VDD through pMOS txs – connect the output to ground through nMOS txs assert-low pMOS – insure the output is always either high or low logic inputs output • CMOS produces “inverting” logic assert-high logic nMOS – CMOS gates are based on the inverter – outputs are always inverted logic functions e.g., NOR, NAND rather than OR, AND Useful Logic Properties • Logic Properties 1 + x = 1 0 + x = x DeMorgan’s Rules 1 ⋅ x = x 0 ⋅ x = 0 Properties which can be proven (a ⋅ b)’ = a’ + b’ x + x’ = 1 x ⋅ x’ = 0 (a+b)(a+c) = a+bc a ⋅ a = a a + a = a a + a'b = a + b (a + b)’ = a’ ⋅ b’ ab + ac = a (b+c) ECE 410, Prof. A. Mason Lecture Notes Page 2.11 Review: Basic Transistor Operation CMOS Circuit Basics + source Vg= Vsg Vout - pMOS Vin Vin assert-low pMOS Vin Vsg > |Vtp| = on 0 1 on = closed pMOS gate Vsg = VDD - Vin logic 1 ? off = open VDD drain off inputs output VDD-|Vtp| drain on assert-high Vg= nMOS gate Vout on logic Vin nMOS Vin + Vgs > Vtn = on 0 ? off = open Vtn Vgs off source 1 0 on = closed - nMOS CMOS Pass Characteristics ‘source’ is at lowest potential (nMOS) and highest potential (pMOS) VDD VDD + •nMOS Vgs=Vtn –0 in Æ 0 out nMOS 0 V VDD - –VDD in Æ VDD-Vtn out Vy = 0 V Vy = – strong ‘0’, weak ‘1’ VDD-Vtn •pMOS 0 V 0 V - Vsg=|Vtp| –VDD in Æ VDD out pMOS VDD 0 V + –0 in Æ |Vtp| out Vy = VDD Vy = |Vtp| – strong ‘1’, weak ‘0’ ECE 410, Prof. A. Mason Lecture Notes Page 2.12 Review: Switch-Level Boolean Logic • assert-high switch – y = x • A, i.e. y = x if A = 1 – series = AND a AND b – parallel = OR a OR b • assert-low switch – y = x • A, i.e. y = x if A = 0 =x – series = NOR a b – parallel = NAND NOT (a OR b) ECE 410, Prof. A. Mason Lecture Notes Page 2.13 CMOS Inverter • Inverter Function • Inverter Symbol • toggle binary logic of a signal x y • Inverter Switch Operation • Inverter Truth Table xy= x 0 1 =VDD Vin=VDD 1 0 • CMOS Inverter Schematic + Vsg - input low Æ output high input high Æ output low pMOS nMOS off/open nMOS on/closed Vin pMOS on/closed pMOS off/open Vout = Vin pMOS “on” nMOS “on” nMOS Æ output high (1) + Æ output low (0) Vgs - ECE 410, Prof. A. Mason Lecture Notes Page 2.14 nMOS Logic Gates • We will look at nMOS logic first, more simple than CMOS • nMOS Logic (no pMOS transistors) – assume a resistive load to VDD – nMOS switches pull output low based on inputs VDD VDD (a) nMOS is off Æ output is high (1) nMOS Inverter =VDD VDD (b) nMOS is on Æ output is low (0) nMOS NOR nMOS NAND c = ab c = a+b • parallel switches = OR function • series switches = AND function • nMOS pulls low (NOTs the output) • nMOS pulls low (NOTs the output) ECE 410, Prof.
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