Logic Styles with

NMOS Logic

One way of using MOSFET to produce logic circuits uses only n-type (n-p-n) transistors, and this style is called NMOS logic (N for n-type transistors). An circuit in NMOS is shown in the figure with n-p-n transistors replacing both the and the of the inverter circuit examined earlier.

The lower in the circuit operates as a switch exactly as the idealised switch in the original circuit: with 5V on the Gate input, the conducting channel is created in the transistor and the “switch” is closed; with 0V on the Gate there is no channel and the transistor is non-conducting - the “switch” is open.

The depletion mode transistor is produced by adding a small amount of donor material to the The upper transistor, called a depletion mode channel region of a n-p-n transistor, so that there are a small number of free in the channel transistor, operates as a resistor to limit current even when there is no electric field across the flow when the “switch” is closed. This transistor is insulator. This provides a connection through the a modified n-p-n transistor that always has a transistor for all Gate voltages. The conductivity of channel present and is always conducting, although the channel is lowest (Resistance is highest) when the conductivity is low when there is 0V on the the Gate is at 0V. When the Gate is at 5V and more Gate and higher when 5V is on the Gate: see Box. free electrons are pulled into the channel by the electric field, the conductivity is highest (Resistance The function of this transistor is purely resistive is lowest). The transistor acts a variable Resistance. and is present, as in the earlier circuit, to restrict This is quite useful in NMOS circuits as when there is current flow through the circuit and the output current flow and limit power consumption in the voltage is at 0V, the resistance of the depletion circuit. A transistor is used as a resistor because mode transistor is highest limiting the current flow. the space taken up on the substrate is much less When the circuit is opened and the output voltage than with other methods of producing on starts rising to 5V, the resistance decreases allowing silicon. a more rapid switching of the output to 5V.

An NMOS NAND circuit is shown in the figure to the right. Again n-p-n transistors are used to replace the ideal of the earlier circuit, while a depletion mode n-p-n transistor replaces the resistor. It operates in exactly the same way as the earlier circuit.

NMOS circuits suffer the same faults as our earlier circuits but have an extra electrical problem as well. The problems seen are:-

• continuous power consumption when a circuit is made through the logic and a current flows. • Asynchronous switching times as it is quicker to switch the output from 5V→0V → than from 0V 5V (see earlier explanation) • the new electrical problem is that the switch transistors have a small resistance, so that when a current flows there is a small voltage drop across the switch transistors and the output voltage does not quite reach 0V. This causes problems when there are large collections of interconnected circuits, and extra circuitry has to be added to restore the voltage to 0V.

A large number of circuits can be placed on a single piece of silicon and interconnected to produce complex circuits. NMOS logic was used extensively in the 1970s and early 1980s for most digital semi-conductor devices, “chips”, e.g. the 8086 and Motorola 68000 .

17 CMOS Logic

Most modern chips use CMOS logic, as it has many advantages over NMOS: there were operational problems with CMOS in the past that caused NMOS logic to be used for many years. In CMOS circuits both n-p-n and p-n-p MOSFET transistors are used with circuits structured into 2 parts. One part consisting of purely n-p-n transistors controls the connection of the output of the circuit to the 0V power supply terminal, i.e. it sets the output to a ‘0’, while the other part consisting of purely p-n-p transistors controls the connection of the output to the 5V power supply terminal, i.e. it sets the output to a ‘1’. This can be seen in the figure to the right which shows a CMOS inverter circuit. CMOS stands for Complementary MOS. The Complementary comes from the operation of the circuit parts such that only one part makes a connection between the output and the power supply at any time: the n-p-n part or the p-n-p part. There must never be an arrangement when the output has a good connection to both power supply terminals as then a short-circuit condition exists and the circuit will be damaged. In the inverter, the input controls both the upper p-n-p transistor and the lower n-p-n transistor. With 5V on the input the lower transistor conducts, but not the upper, and the output is at 0V; with 0V on the input the upper transistor conducts, but not the lower, and the output is 5V. Either the upper or lower circuit connects the output to a power supply terminal, but there is never a good connection to both. The figure to the left shows the 2 possible configurations of the inverter with switches replacing the transistors: the circle on the input to the upper switches indicates that the switch is closed when 0V is on the switch control.

The figure on the next page shows the CMOS logic for the 2-input NOR gate. It has 2 n-p-n and 2 p- n-p transistors. The circuit outputs 5V only when both p-n-p transistors are conducting, i.e. when both inputs are 0V. At all other times one of the inputs is at 5V, one of the n-p-n transistors is conducting, and at most one of the p-n-p transistors, but not both, so that the output is at 0V. The different configurations of the NOR circuit can be seen in the switch diagrams in the figure. Again, there is never a constant current flow through the circuit and never a short-circuit. Examining the lower part of the circuit (at the bottom of the figure), the output is at ‘0’ if input A is ‘1’ or input B is ‘1’ - the NOR function. For the upper part of the circuit the output is at ‘1’ if both input A is ‘0’ and input B is ‘0’ - this function is NOT(A) AND NOT(B). Of course this function is, by deMorgan’s Rule, just the NOR of A and B. Thus both the upper and lower parts perform the NOR function: the upper part gives the 1s in the NOR truth table, the lower part the 0s.

CMOS circuits are much better than their NMOS equivalents:- • For no set of inputs is there a circuit through the transistors connecting the power supply terminals, so that there is no continuous current flow and no continuous power consumption. However, as is set out below, there is some power consumption when the circuit configuration is changing. • the transistors can be made to provide symmetric switching times for both output transitions: 5V→0V and 0V→5V. This makes CMOS logic faster than the equivalent NMOS circuit as the latter has a longer 0V→5V switching time. • Since there are no constant current flows, there are no voltage drops across the transistors and CMOS circuits output full 5V and 0V signals. • There is always a good connection between the output and the power supply: in NMOS there is a resistive connection to 5V.

The last 2 points make building large circuits much easier than for NMOS: it is just a matter of plugging CMOS circuits together, although there are times when more complex circuits provide faster and/or smaller solutions. It should be noted that there are many ways to put n-p-n and p-n-p transistors together that do not produce CMOS circuits, i.e. circuits without complementary action.

18

Power Consumption in CMOS circuits

This arrives from 2 effects, which can be examined by considering the inverter circuit with its input at 0V and its output at 5V. When the input is changed to 5V both transistors start to change, the upper to a non-conducting state and the lower to a conducting state, and electrons start to move through the lower transistor from 0V to the output which is still at 5V. Since they move across a voltage drop power is consumed, until enough electrons arrive at the output to reduce its voltage to 0V. There is a similar effect on switching the input from 5V to 0V: the output changes from 0V to 5V, but this time it is the electrons moving through the voltage drop across the upper transistor that causes the power consumption, until enough positive charge has built up at the output for it to be at 5V. The amount of energy consumed is determined by the number of electrons that have to cross to or from the output to change the voltage to 0V or 5V respectively. The number of electrons in each case is the same and is

19 controlled by the capacitance of the output (capacitance of a body is the amount of charge required to change its voltage by 1 Volt), which is controlled by structural factors. Essentially, on every cycle of the output signal, e.g. 5V‰0V‰5V, some number of electrons, sufficient to charge the output to 0V, move from the negative terminal of the power supply through the transistors of the logic circuit to the positive terminal of the power supply with the corresponding release of energy from the power supply into heating the material of the circuit.

The second cause of power consumption in both switching situations is that while the transistors are changing state, there is a period when both are conducting and there is a circuit though the transistors between the power supply terminals so that a current flows. The period of current flow is very short and the current is not large as the conducting path is not particularly good, as the transistors channel are not fully formed. However, some power is consumed. The amount of energy released in this second case is controlled by the rate at which the input voltage changes and by how fast the transistors respond to the change on their Gate inputs: the faster both these occur the lower the energy release.

Thus it can be seen that CMOS circuits consume power only on switching and that the more often switching occurs the more power is consumed. CMOS circuits are said to have no static power consumption, but to have dynamic power consumption. This is why digital watch batteries can last for 2 years: the switching rate is low and so the power consumption is low.

CMOS Circuit layout

A question that needs to be answered is how both p-n-p and n-p-n transistors can be laid out on the same piece of silicon. Usually the silicon on which the circuit is laid out is p-type silicon, so that the n-p-n transistors can be directly built on the surface by adding the appropriate n-regions, insulators and Gate material. For the p-n-p transistors a region of n-type material must first be built into the p-

Inverter Layout

type material (this region is called a well or an n-well), and then p-regions are added to the n-well surface to produce the p-n-p transistors, followed by the insulators and Gate material. This can be seen in the figure. Connections to the transistors are carried over the silicon surface. Substrate connections to the power supply terminals (0V to the p-type substrate, 5V to the n-substrate in the wells) are also carried over the surface and are made near to the transistors. It should be noted that the p-n junction where the well meets the substrate is reverse-biased, as the well is tied to 5V power supply terminal and the substrate is tied to the 0V power supply terminal.

Manufacture of Silicon Circuits

Silicon chips are built layer by layer on the surface of single crystal of silicon. For each layer there is a pattern (usually called a mask), which determines the areas of the crystal where the material of the layer are to be placed. The stages of development of a chip are:-

• design and simulation of the circuit to be produced, • production of a layout for the circuit on the chip, • extraction from the layout of the mask for each layer of the chip manufacturing process, • manufacturer of the chip.

The first 3 stages are nowadays all performed by computer. A design engineer, or a design team for a large circuit, produces the circuit design using a range of computer-aided-design (CAD) tools. The process is not unlike the design of a large software system. There are requirements analysis and

20 system specification stages with a division of the final system into sub-parts and a specification of the interconnection between these parts. These circuit sub-components are designed and entered into a computer with a CAD tool, where the designs can be simulated and have their performance checked against the specification. Once all the components have been designed and interconnected, another tool can be used to produce a prospective layout of the circuit on silicon, i.e. defining where each transistor is place and the routes taken by their interconnections. It is only at this stage that a detailed analysis can be made to calculate the electrical parameters of the circuit, so that a more complete simulation of the circuit can be performed. Testing is a major issue since once a chip has been made it is too late for any changes, so tests must fully cover all aspects of performance: logical operation (does it do what is required), timing (does it run at the required speed), and electrical operations (does it produce the right voltage levels, is its power consumption within the defined limits), physical (is the chip area small enough for manufacture to be economic). If problems arise in the testing, the design will be have to be reworked: sometimes this means going back to much earlier stage of the design process and repeating the subsequent design stages. Once the design and layout have been finalised, the production of the masks, that define where different materials are to be placed in the manufacturing process, is easily performed by a computer. Some components, particularly memories, may have spare logic sections, which can be used to replace similar sections that are non-functional due to manufacturing faults.

The manufacturing process starts with the production of a large single crystal of p-type silicon. This is made as a large cylinder from a vat of molten p-type silicon. A small seed crystal attached to a metal rod is lowered onto the surface of the just molten silicon. Material solidifies slowly onto the crystal and as it does so the rod is very slowly lifted. In this way a rough cylinder of solid material is pulled from the vat. Because of the slow solidification, the crystal structure of the seed crystal is extended so that a single very large crystal is produced. By adjusting the speed of extraction, the diameter of the crystal can be controlled. Once produced the crystal is machine to have a circular cross-section and then it is sawn into thin wafers, usually several inches in diameter and 1 mm thick. On a wafer a number of chips will be manufactured simultaneously, then the wafer will be sawn up into individual chips, which are tested to check their functionality. Wafer diameters are 5 to 8 inches.

The order of laying down material on the wafer to build circuits is obviously to place the deepest material first: first build the n-wells, then add the n-type source/drain regions for the n-p-n transistors, the p-type source/drain regions for the p-n-p transistors, the polysilicon material to produce the gate regions, a first layer of metal for interconnections, and then a second layer of metal interconnections. Where necessary, insulation material (silicon oxide) is placed to prevent unwanted connections, e.g. between polysilicon and underlying transistor, between the different metal layers. Where a good connection between a metal layer and underlying material is required a vertical shaft is cut and filled with metal to ensure the connection. Two or more metal layers are provided to make routing signals around the circuit easier: for short interconnections, polysilicon can be used and sometimes a second polysilicon layer is provided to further ease signal routing. Signal routing has a major impact on circuit area. Note different routing layers can be run over each other to provide 3-dimensional routing.

All stages of processing of a wafer are carefully controlled, as manufacture is a very precise process. Processing is performed in clean rooms where the level of airborne dust particles are kept extremely low, as dust on the wafer interferes with the manufacturing process (dust particles are much bigger than the structures being produced and could block material being laid down under the dust particle).

The process of putting down a layer of material has a number of steps, which can be illustrated by considering the production of the n-wells on a wafer:

1. the wafer is cleaned first and then it is exposed to oxygen which rapidly reacts with the surface silicon atoms to produce a thin layer of silicon oxide over the surface. Silicon oxide besides being an insulator is also very hard. 2. the wafer is coated with photo-sensitive material which is washed on and allowed to dry. 3. the mask that identifies where the n-wells are to be placed is carefully positioned over the surface of the wafer and then illuminated, so that the mask pattern is transferred on to the photo-sensitive

21 material: positioning is crucial as many layers are added one-at-a-time on to the surface and all layers must be carefully aligned with each other to ensure correct corrections are made. 4. The wafer is then washed in an acid bath which In large-scale production, the mask is differentially etches away the photo-sensitive produced on a glass plate which is placed material and underlying silicon oxide where the over the wafer and then the mask and wafer is material has been exposed to the light but not illuminated with UV lamp. Since making the elsewhere. Thus the mask pattern is reproduced on glass plates is expensive, for small-scale the wafer: where the n-wells are be placed the production, a computer-controlled UV laser surface of the wafer is exposed, elsewhere there is a traces the mask pattern on to the wafer using layer of hard silicon oxide. the mask information which is stored on disk. 5. The wafer is placed in a near-vacuum in a container [The wavelength of the light used controls the and is bombarded with Phosphorus atoms. In a minimum size of structures on the wafer, and to reduce these X-ray or beams may small chamber at the top of the container a small be used in future instead of UV light. amount of Phosphorus is heated so that it evaporates to produce a cloud of hot Phosphorus atoms, these are allowed to escape through a small hole in the chamber and they stream down on to the wafer. Where they hit the exposed silicon surface of the wafer they penetrate a short way. Where they hit the silicon oxide layer, they bounce off. This deposits Phosphorus (donor) atoms into the n-well and this process is continued until the required density of phosphorus has been produced in the well regions: sufficient to change the regions from their original p-type to n-type.

The other n-type and p-type regions are produced in a similar way. For the polysilicon and metal layers, the wafer is first covered all over with the material to be put down, then the photo-sensitive material is placed and exposed, and finally etching as above removes unwanted material to leave the material in the required patterns.

Not all chips will work because there can be some failure in manufacture. A major problem is that there are always defects in the crystal structure of the wafer and if such a defect occurs in the area covered by a chip, that chip will fail. The probability that a defect will occur in the area covered by a chip increases with a chip’s area, so that the bigger the chip the more likely it is that it will have a crystal defect and fail. Thus the yield of working chips, the ratio of working chips to chips manufactured, decreases as chip area increases: for chips with an area greater than about 125 mm2 the yield used to be (mod 1990s) too low for manufacture to be economic, so 125 mm2 was the upper limit on chip area. Improvements in crystal production has improved matters and the most recent version (2001-2002) version of the Intel Itanium CPU has a chip area of 464 mm2, a very big chip by everybody’s standards and very difficult to get a very large production yield (% of working chips per chips manufactured). This low yield makes the chip very expensive to make and to buy!

22