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Techniques of Energy-Efficient VLSI Chip Design for High-Performance

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Techniques of Energy-Efficient VLSI Chip Design for High-Performance Louisiana State University LSU Digital Commons LSU Doctoral Dissertations Graduate School 9-13-2018 Techniques of Energy-Efficient VLSI Chip Design for High-Performance Computing Zhou Zhao Louisiana State University and Agricultural and Mechanical College, [email protected] Follow this and additional works at: https://digitalcommons.lsu.edu/gradschool_dissertations Part of the Electrical and Electronics Commons, and the VLSI and Circuits, Embedded and Hardware Systems Commons Recommended Citation Zhao, Zhou, "Techniques of Energy-Efficient VLSI Chip Design for High-Performance Computing" (2018). LSU Doctoral Dissertations. 4702. https://digitalcommons.lsu.edu/gradschool_dissertations/4702 This Dissertation is brought to you for free and open access by the Graduate School at LSU Digital Commons. It has been accepted for inclusion in LSU Doctoral Dissertations by an authorized graduate school editor of LSU Digital Commons. For more information, please [email protected]. TECHNIQUES OF ENERGY-EFFICIENT VLSI CHIP DESIGN FOR HIGH-PERFORMANCE COMPUTING A Dissertation Submitted to the Graduate Faculty of the Louisiana State University and Agricultural and Mechanical College in partial fulfillment of the requirements for the degree of Doctor of Philosophy in The Division of Electrical and Computer Engineering by Zhou Zhao B.S., University of Electronic Science and Technology of China, Chengdu, China, 2011 M.S., University of Electronic Science and Technology of China, Chengdu, China, 2014 December 2018 ACKNOWLEDGMENTS Firstly, I sincerely dedicate my dissertation to my parents and my maternal grandmother for their great and endless support and education to my entire life. I would like to thank my doctoral advisor, Dr. Ashok Srivastava. His solid understanding of VLSI circuit theory and kind encouragement gave me invaluable help during my graduate study. I sincerely appreciate Dr. Lu Peng for his help on the computer architecture with open mined vision. I would like to thank Dr. Lu Peng’s former doctoral student, Dr. Shaoming Chen, for his help on the modeling of power delivery network. I also thank Dr. Saraju P. Mohanty of the University of North Texas for help and discussion. I would like to thank Dr. Ramachandran Vaidyanathan, Dr. David Koppelman and Dr. Scott Baldridge as my committee members with their precious suggestions on my dissertation. I deeply thank my friends I met in LSU, Xinlu, Xiaohan, Boyuan, William, Jojoe, Xiaochen and Wei. Part of the work is supported under NSF Grant No. 1422408. Finally, I would like to thank everyone for blooming in my life like the fireworks beauty. ii TABLE OF CONTENTS ACKNOWLEDGMENTS .............................................................................................................. ii LIST OF TABLES .......................................................................................................................... v LIST OF FIGURES ....................................................................................................................... vi LIST OF ABBREVIATIONS ......................................................................................................... x ABSTRACT ................................................................................................................................. xiii CHAPTER 1. INTRODUCTION ................................................................................................... 1 1.1 Challenge of Computations in VLSI Chips...................................................................... 1 1.2 Power Regulation in Computational Chips ...................................................................... 2 1.3 Overview of Multiple Logic Styles .................................................................................. 3 1.4 Circuit Design for Logarithmic Computation ................................................................ 10 1.5 Overview of Optimization in ALU Design .................................................................... 13 1.6 Circuit Design for Neural Computation ......................................................................... 15 1.7 Goals and Objectives ...................................................................................................... 19 CHAPTER 2. SWITCHABLE PIN USED FOR POWER REGULATION IN CHIP- MULTIPROCESSOR ................................................................................................................... 21 2.1 Analysis of IR Droop ..................................................................................................... 21 2.2 Overview of Switchable Pin ........................................................................................... 24 2.3 Performance Evaluation using PDN .............................................................................. 27 2.4 Customized Design of I/O Pad ....................................................................................... 30 2.5 Circuit Verification ........................................................................................................ 35 2.6 Conclusion ...................................................................................................................... 44 CHAPTER 3. LOGARITHMIC CONVERTER WITH A NOVEL CALIBRATION SUPPLIED BY DC/CLOCKED POWER ....................................................................................................... 46 3.1 Study of Logarithmic Conversion .................................................................................. 46 3.2 Circuit Implementation .................................................................................................. 51 3.3 Error Analysis ................................................................................................................ 59 3.4 Circuit Verification ........................................................................................................ 61 3.5 Conclusion ...................................................................................................................... 71 CHAPTER 4. ALU DESIGN BASED ON NEURON-LIKE CELLS USING MULTIPLE INPUT FLOATING GATE MOSFETS ....................................................................................... 72 4.1 Design of Neuron-Like Cells ......................................................................................... 72 4.2 ALU Design ................................................................................................................... 76 4.3 Result and Discussion .................................................................................................... 81 4.4 Conclusion ...................................................................................................................... 91 iii CHAPTER 5. LONG SHORT-TERM MEMORY NETWORK DESIGN FOR ANALOG COMPUTING ............................................................................................................................... 92 5.1 Long Short-Term Memory Network .............................................................................. 92 5.2 MIFG MOSFETs for DAC Design ................................................................................ 95 5.3 Long Short-Term Memory Network Design .................................................................. 96 5.4 Result and Discussion .................................................................................................. 112 5.5 Conclusion .................................................................................................................... 129 CHAPTER 6. SUMMARY AND SCOPE OF FUTURE WORK .............................................. 132 6.1 On-Chip Power Regulating Using Switchable Pins ..................................................... 132 6.2 Logarithmic Conversion with Calibration.................................................................... 133 6.3 Optimization and Calibration of ALU ......................................................................... 134 6.4 Neural Accelerator based on ASP ................................................................................ 135 BIBLIOGRAPHY ....................................................................................................................... 137 APPENDIX A. MOSIS SPICE LEVEL 7 CMOS MODEL PARAMETERS ........................... 148 A.1 AMI 500nm Technology .............................................................................................. 148 A.2 TSMC 180nm Technology ........................................................................................... 149 APPENDIX B. PROPOSED DESIGN FLOW OF AUTOMATIC PLACEMENT AND ROUTING USING MENTOR GRAPHICS EDA TOOLS........................................................ 152 B.1 APR with Verilog Entry ............................................................................................... 152 B.2 APR with Customized Schematic Entry ...................................................................... 152 APPENDIX C. ERROR TEST IN PSPICE SIMULATION ...................................................... 155 VITA ........................................................................................................................................... 157 iv LIST OF TABLES Table 2.1 Summary of dimension in via……………………………………………………...31 Table 2.2 Summary of parameters in PDN…………………………………………………...31 Table 2.3 Summary of testing cases…………………………………………………………..36 Table 2.4 Pin allocation of the chip in Figure 2.10……………………………………………42
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