DOCSLIB.ORG

Lecture2.Pdf

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Lecture2.Pdf Design of Scaled CMOS Circuits in the Nano -meter Regime: Leakage Tolerance and Computing with Leakage Kaushik Roy Professor of Electrical & Computer Engineering Purdue University VLSI Applications General purpose computing: internet server, database server, real-time Ultralow power jobs etc. applications: medical, space, ER specific sensor W network etc. PO Portable applications: mobile computing, wireless, multimedia etc. PERFORMANCE • Different applications have different power-performance demands • Scaling affects all applications in different ways 1 Cha llenges a hea d … in Si nanometer regime Challenge No. 1: Device Scaling Bulk MOS UTB-SOI MOS DG-SOI MOS Retograde Well, Halo Fully-depleted ultra-thin body Planar double-gate structure Strained Channel Ground-plane Independent gate control FinFET Tri-gate Vertical MOS Quasi-planar DG structure Quasi-planar with 3 gates Conduction normal to plane Most promising device Better area efficiency Difficult to fabricate 2 Scaling & Ion/Ioff 1 um 100 nm 10 nm Silicon micro Silicon nano Non-Silicon electronics electronics technology • Increasing I leakage V • Increasing process variations • Carbon Nanotubes • Short Channel • Molecular transistors Effects • Molecular RTDs I ION 3 I ON =106 =10 ON =104 I IOFF OFF IOFF 2. Power & Power Density 100 P6 Pentium ® proc ) 2 10 tts) cm a 486 286 8086 386 8085 1 8080 Power (W 8008 4004 Power Density (W/ 0.1 1971 1974 1978 1985 1992 2000 Year Year Increased Average Power • Battery Life Increased Power Density • Cooling Cost • Reliability Source: Intel 3 Challenge 3: Process Variations Device 1 Device 2 Leff1<Leff2 A. Asenov, TED03 Dopant Line-Edge atoms Roughness M. Hane, et. al., SISPAD 2003 Variation in channel length Random Dopant Fluctuations (RDF) 1.4 NMOS z Intrinsic parameter variations: PMOS ON 1.2 – Channel length and width d I e – Variations due to line edge 1.0 2X roughness 0.8 – Threshold voltage (Vt) variations Normaliz 0.6 100X 150nm, 110°C due to random dopant fluctuation 0.4 0.01 0.1 1 10 100 Normalized IOFF Device parameters are no longer deterministic Challenge 4: Reliability Temporal degradation of performance -- NBTI Tech. generation ailure probability F Time Defects Life time degradation 4 Power Consumption • Leakage Power – Subthreshold, Gate, Junction, GIDL, Punchthrough, …. • Dynamic Power – Due to charging/discharging of capacitive load – Short-circuit power due to direct path currents when there is a temporary connection between power and ground Leakage Vs. Dynamic Power (Projection) 1200 15 mm Die 1000 Leakage ~54% Dynamic 800 600 ~32% Power (W) 400 7% 1% 3% ~16% ~ ~ 200 ~ 0 Source: Intel 0.25u 0.18u 0.13u 90nm 65nm 45nm Leakage power limits Vth scaling 5 Leakage Power Scaling and Other Leakage Components • Leakage Components Subthreshold Gate Leakage Leakage – Subthreshold Leakage Gate Source Drain – Gate Leakage n+ n+ – Reverse-biased Junction Band- Reverse Biased To-Band-Tunneling (BTBT) Junction BTBT Leakage. –Others Bulk Long Channel Short Channel Very Short Nano-scaled ( ( L > 1 μm) ( L > 180 nm, Channel ( L < 90 nm, Tox > 30A0) L > 90 nm, Tox Tox < 20A0) Negligible Subthreshold > 20A0) Subthrehold leakage leakage Subthrehold + + Gate + Jn. Gate Leakage BTBT leakage 6 Leakage Power Consumption V DD VDD Vout = VDD Diode leakage Vq / kT IO = is (e −1) Sub-threshold leakage (Vgs −Vt )q / nkT Vdsq / kT I D = K ⋅e (1− e ) Pstatic = Ileakage. VDD Diode Leakage • Leakage current through the reverse biased diode junctions • For typical devices it is between 0 .1nA - 0. 5nA at room temperature • For a die with 1 million devices operated at 5 V, this results in 0.5mW power consumption → not much • Junction leakage current is caused by thermally generatedid carriers -> thfherefore is a strong funct ion of temperature • More important is sub-threshold leakage, gate leakage, and Junction BTBT leakage 7 Leakage Components •Vt Scaling Subthreshold •Short Channel Leakage Ç Effects Gate Scale Tox Leakage Ç •Scale Wd-doping Ç Junction •Channel Engg. – patches of higher BTBT doping in the channel Leakage Ç Doping -1 has more effective “halo” doping to reduce SCE Jn. Band-To-Band-Tunneling Current (IBTBT) Electron tunneling from EC q(V +V ) VB of p-side to the CB of bi app E n-side. V EC BTBT Current density p-side depends on Junction field EV (ξ), junction voltage(Vapp) , n-side band-gap (Eg). High BTBT in scaled 3/2 ξVEapp⎛⎞ g devices JA=− expB⎜⎟ bb− 1/2 ⎜⎟ High junction doping: Eg ⎝⎠ξ ' *3 * “Halo” profiles 242mq m 'Small depletion width AB==32 , and 43π hhq 'Large electric field 8 Gate Leakage (Igate) Φ Direct tunneling of electron ox, ECB=3.1 eV ECB through gate oxide. Gate current density EVB depends on oxide thickness, oxide field and HVB voltage drop across oxide n+ poly p substrate ⎛⎞−BV11−− /φ 3/2 2 goxox( ( ) ) JAVTexp= ⎜⎟ DT g() ox ox ⎜⎟ ⎜⎟VTox/ ox ⎝⎠ High Gate leakage in scaled devices: Low oxide thickness and high oxide field Components of Gate Leakage Gate leakage components Gate to source/drain overlap region • I I (Igso, Igdo) gso gdo ¾Controlled by Vgd and Vgs I gc • Gate to channel (Igc)= to source (Igcs) + to drain (Igcd) ¾Controlled by Vox≈Vgs- Igcs I gcd VFB -Φs –Vpoly. I gb • Gate to body (Igb) ¾Controlled by Vgb Transistor off (Vg=‘0’) – Igdo and Igso dominates. Transistor on (Vg=‘1’) – Igc (Igcs & Igcd) dominates. Igb small compared to others. 9 Subthreshold leakage (Isub) Exponentially dependence on Vgs and Vth. wqNε ⎛⎞⎛⎞ VV− ⎛⎞−V Ivexpexp=−effμ si cheff2 gs th 1 ds sub T ⎜⎟⎜⎟⎜⎟ Lnvveff2Φ s⎝⎠⎝⎠ T⎝⎠ T Vth modulation 9 Short channel Effect – Vth reduction due to ¾ Increase in Vds (DIBL), ¾ Reduction in Channel Length (Vth roll off). 9 Body effect – negative Vbs increases Vth. 9 Quantum confinement effect – increases Vth ⎛⎞W VV=+Φ−ΔΦ+Φ−−γλ V1 dm ++ V V th FB() s00 s s bs⎜⎟ nce QM ⎝⎠Leff ΔΦ =2(VVeeandlTW −φεεη ) + ×⎡⎤−−Ll/2cc + 2 Ll / = sbiSds[]0 ⎣⎦ Csioxoxdm( ) Subthreshold Leakage Subthreshold leakage reduces with 9Negative Vbs, Reduction of Vds 9Application of Quantum Correction 10 Total Leakage “Sum of Current Source Model ” Voltage Controlled Current Sources describing each leakage comp. Total Transistor Leakage= IIIIoverall= BTBT++ sub gate Leakage Estimation Method Logic Gates Isub I gate Isub Itotal ‘00’ ‘01’ ‘10’ ‘11’ Leakage Table Curr en t M odeling Estimated Total INPUT Circuit Leakage OUTPUT Logic Circuits 11 Low-Vdd Low-Vt Design • Stacked CMOS • Dual-threshold CMOS • Dynamic-threshold CMOS Leakage Reduction (Logic & Memory) Circuit Techniques DiDesign Time Run Time Dual V th Standby Leakage Active Leakage Reduction Reduction Natural Stacking DVTS Sleep Transistor FBB/RBB 12 Self-Reverse Bias (Source-Biasing, Supply-Gating, Stacking) log(I ) V DS • Primary effect: D –VGS < 0 VG= 0V VS = 0 – move down VS subthreshold V > 0 slope S VGS • Secondary effects: – Drain Induced Barrier Lowering VDS ↓⇒ VT ↑ – Body effect VS ↑⇒ VT ↑ Leakage Control: Stacking Vdd Vdd M1 ‘0’ ‘0’ VM>0 ‘0’ M2 Vgs=0,Vbs=0,Vds=Vdd For M1: 9NtiVNegative Vgs, Vgs =-VM< 0,Vbs =-VM<0, 9Negative Vbs- More Vds = Vdd-V <Vdd Body effect, M For M2: 9Reduced Vds-Less DIBL Vgs =0,Vbs =0, 2-T stack has lower Vds = V < Vdd subthreshold leakage M 13 Input Vector Control - Subthreshold Vdd Vdd M1 M1 ‘0’ ‘1’ VM>0 Vdd-Vth_M1 ‘0’ ‘0’ M2 M2 Minimum Vgs is For M1: Minimum Vgs is For M2: VM10Vgs_M1 < 0, VM20Vgs_M2 = 0, Vds_M1= Vdd - VM Vds_M2=Vdd-Vth_M1 ‘00’ gives minimum subthreshold leakage. Turn ‘off’ maximum number of transistors in a stack to reduce subthreshold leakage Leakage vs. Transistors Off Leakage [nA] 10 8 6 4 2 0 1234 Number of transistors off in stack 14 Input Vector Control – Gate Leakage 9Vg=‘0’ – EDT dominates Vdd ¾Ig = Igdo + Igso Igdo_M1(Vdd) 9Vg=‘1’ – Gate to Channel M1 tunneling is significant ‘0’ ¾Ig = Igdo + Igso + Igc Igso_M1(VM) VM>0 With ‘00’ – Igdo_M2(VM) Igdo_M1(Vdd) >> ‘0’ Igso_M1(VM) + Igdo_M2(VM) M2 Igdo of M1 dominates the total gate current ⎛⎞−−−BV11 /φ 3/2 2 ( ()dd ox ) IWLAVTexp= ⎜⎟ gstack SDE() dd ox ⎜⎟ ⎜⎟VTdd/ ox ⎝⎠ Input Vector Control – Gate Leakage With ‘01’ – Vdd Igdo_M1(Vdd) is high. Igdo_M1(Vdd) Igdo_M2(Vdd) is high. M1 Igso_M2(Vdd) is high. ‘0’ Gate to channel leakage of M2 is controlled by : 0 Vox_M2 = Vdd - VFB -Φs – Igdo_M2(VM) Vpoly. ‘1’ Igc_M2(Vdd) Igso_M2(V ) M2 Total gate current is high. M 15 Input Vector Control – Gate Leakage With ‘10’ the major gate Vdd currents are: 9Igso_M1(Vth) M1 Igc_ M1(Vth) 9Ig do_ M2(Vdd - Vth_ M1) ‘1’ 9Igc_M1(Vgs = Vth) Igso_M1(Vth_M1) Vdd-Vth_M1 Igdo_M2(V ) =V Igdo_M2 dominates the INT INT total current. ‘0’ M2 3/2 2 ⎛⎞ −−−−BVV11(dd th_1 M )/φ ox ⎛⎞()VVdd− th_1 M ⎜⎟( ()) IWLAgstack= SDE ⎜⎟ exp TVVT⎜⎟()/− ⎝⎠ox⎜⎟ dd th_1 M ox ⎝⎠ Input Vector Control – Gate Leakage Vdd Vdd Igdo_M1(Vdd) M1 M1 Igc_M1(Vth) ‘0’ ‘1’ Igso_M1(VM) Igso_M1(Vth_M1) Vdd-Vth_M1 VM>0 Igdo_M2(VM) Igdo_M2(VINT) =VINT ‘0’ ‘0’ M2 M2 I(Vdd)I(VddIg(Vdd) > Ig(Vdd-Vth_ M1) Rate of change of gate current increases with an increase in Vox (exponential) Gate current with ‘10’ is lower than ‘00’ 16 Gate Leakage Gate leakage increases with 9 Increase in Vox 9 Reduction in Tox. Rate of change of current is higher at higher Vox Input Vector Control – BTBT Vdd Vdd Vdd IBTBT_d_M1 IBTBT_d_M1 M1 ‘1’ ‘0’ ‘0’ IBTBT_s_M1 M1 Vdd-Vth_M1 =V M1 INT V >0 M 0 IBTBT_d_M2 ‘0’ ‘0’ ‘1’ M2 M2 M2 ’00’ an d ’01’ –didrain-subtbstra te BTBTfM1dBTBT of M1 dom ina tes. ’10’ – additional BTBT components drain-substrate of M2 and source-substrate of M1. ’10’ gives maximum BTBT. However, BTBT is not very sensitive to stacking.
Load more

Recommended publications
  • Role of Mosfets Transconductance Parameters and Threshold Voltage in CMOS Inverter Behavior in DC Mode
    Preprints (www.preprints.org) | NOT PEER-REVIEWED | Posted: 28 July 2017 doi:10.20944/preprints201707.0084.v1 Article Role of MOSFETs Transconductance Parameters and Threshold Voltage in CMOS Inverter Behavior in DC Mode Milaim Zabeli1, Nebi Caka2, Myzafere Limani2 and Qamil Kabashi1,* 1 Department of Engineering Informatics, Faculty of Mechanical and Computer Engineering (milaim.zabeli@uni-pr.edu) 2 Department of Electronics, Faculty of Electrical and Computer Engineering (nebi.caka@uni-pr.edu, myzafere.limani@uni-pr.edu) * Correspondence: qamil.kabashi@uni-pr.edu; Tel.: +377-44-244-630 Abstract: The objective of this paper is to research the impact of electrical and physical parameters that characterize the complementary MOSFET transistors (NMOS and PMOS transistors) in the CMOS inverter for static mode of operation. In addition to this, the paper also aims at exploring the directives that are to be followed during the design phase of the CMOS inverters that enable designers to design the CMOS inverters with the best possible performance, depending on operation conditions. The CMOS inverter designed with the best possible features also enables the designing of the CMOS logic circuits with the best possible performance, according to the operation conditions and designers’ requirements. Keywords: CMOS inverter; NMOS transistor; PMOS transistor; voltage transfer characteristic (VTC), threshold voltage; voltage critical value; noise margins; NMOS transconductance parameter; PMOS transconductance parameter 1. Introduction CMOS logic circuits represent the family of logic circuits which are the most popular technology for the implementation of digital circuits, or digital systems. The small dimensions, low power of dissipation and ease of fabrication enable extremely high levels of integration (or circuits packing densities) in digital systems [1-5].
    [Show full text]
  • Logic Styles with Mosfets
    Logic Styles with MOSFETs NMOS Logic One way of using MOSFET transistors to produce logic circuits uses only n-type (n-p-n) transistors, and this style is called NMOS logic (N for n-type transistors). An inverter circuit in NMOS is shown in the figure with n-p-n transistors replacing both the switch and the resistor of the inverter circuit examined earlier. The lower transistor in the circuit operates as a switch exactly as the idealised switch in the original circuit: with 5V on the Gate input, the conducting channel is created in the transistor and the “switch” is closed; with 0V on the Gate there is no channel and the transistor is non-conducting - the “switch” is open. The depletion mode transistor is produced by adding a small amount of donor material to the The upper transistor, called a depletion mode channel region of a n-p-n transistor, so that there are a small number of free electrons in the channel transistor, operates as a resistor to limit current even when there is no electric field across the flow when the “switch” is closed. This transistor is insulator. This provides a connection through the a modified n-p-n transistor that always has a transistor for all Gate voltages. The conductivity of channel present and is always conducting, although the channel is lowest (Resistance is highest) when the conductivity is low when there is 0V on the the Gate is at 0V. When the Gate is at 5V and more Gate and higher when 5V is on the Gate: see Box.
    [Show full text]
  • MOSFET - Wikipedia, the Free Encyclopedia
    MOSFET - Wikipedia, the free encyclopedia http://en.wikipedia.org/wiki/MOSFET MOSFET From Wikipedia, the free encyclopedia The metal-oxide-semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET), is by far the most common field-effect transistor in both digital and analog circuits. The MOSFET is composed of a channel of n-type or p-type semiconductor material (see article on semiconductor devices), and is accordingly called an NMOSFET or a PMOSFET (also commonly nMOSFET, pMOSFET, NMOS FET, PMOS FET, nMOS FET, pMOS FET). The 'metal' in the name (for transistors upto the 65 nanometer technology node) is an anachronism from early chips in which the gates were metal; They use polysilicon gates. IGFET is a related, more general term meaning insulated-gate field-effect transistor, and is almost synonymous with "MOSFET", though it can refer to FETs with a gate insulator that is not oxide. Some prefer to use "IGFET" when referring to devices with polysilicon gates, but most still call them MOSFETs. With the new generation of high-k technology that Intel and IBM have announced [1] (http://www.intel.com/technology/silicon/45nm_technology.htm) , metal gates in conjunction with the a high-k dielectric material replacing the silicon dioxide are making a comeback replacing the polysilicon. Usually the semiconductor of choice is silicon, but some chip manufacturers, most notably IBM, have begun to use a mixture of silicon and germanium (SiGe) in MOSFET channels. Unfortunately, many semiconductors with better electrical properties than silicon, such as gallium arsenide, do not form good gate oxides and thus are not suitable for MOSFETs.
    [Show full text]
  • Vlsi Design Lecture Notes B.Tech (Iv Year – I Sem) (2018-19)
    VLSI DESIGN LECTURE NOTES B.TECH (IV YEAR – I SEM) (2018-19) Prepared by Dr. V.M. Senthilkumar, Professor/ECE & Ms.M.Anusha, AP/ECE Department of Electronics and Communication Engineering MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY (Autonomous Institution – UGC, Govt. of India) Recognized under 2(f) and 12 (B) of UGC ACT 1956 (Affiliated to JNTUH, Hyderabad, Approved by AICTE - Accredited by NBA & NAAC – ‘A’ Grade - ISO 9001:2015 Certified) Maisammaguda, Dhulapally (Post Via. Kompally), Secunderabad – 500100, Telangana State, India Unit -1 IC Technologies, MOS & Bi CMOS Circuits Unit -1 IC Technologies, MOS & Bi CMOS Circuits UNIT-I IC Technologies Introduction Basic Electrical Properties of MOS and BiCMOS Circuits MOS I - V relationships DS DS PMOS MOS transistor Threshold Voltage - VT figure of NMOS merit-ω0 Transconductance-g , g ; CMOS m ds Pass transistor & NMOS Inverter, Various BiCMOS pull ups, CMOS Inverter Technologies analysis and design Bi-CMOS Inverters Unit -1 IC Technologies, MOS & Bi CMOS Circuits INTRODUCTION TO IC TECHNOLOGY The development of electronics endless with invention of vaccum tubes and associated electronic circuits. This activity termed as vaccum tube electronics, afterward the evolution of solid state devices and consequent development of integrated circuits are responsible for the present status of communication, computing and instrumentation. • The first vaccum tube diode was invented by john ambrase Fleming in 1904. • The vaccum triode was invented by lee de forest in 1906. Early developments of the Integrated Circuit (IC) go back to 1949. German engineer Werner Jacobi filed a patent for an IC like semiconductor amplifying device showing five transistors on a common substrate in a 2-stage amplifier arrangement.
    [Show full text]
  • Class 08: NMOS, Pseudo-NMOS
    Class 08: NMOS, Pseudo-NMOS Topics: •02 NMOS Logic Gates •03 NMOS Logic Gates •04 Pseudo-NMOS •05 Pseudo-NMOS •06 Transistor Equivalency Dr. Joseph Elias; Dr. Andrew Mason 1 Class 08: NMOS, Pseudo-NMOS NMOS (Martin c. 1) § nMOS Inverter with resistive load § nMOS Inverter with depletion load Depletion nMOS, Vtn < 0 always ON for VGS = 0 § switch level model W/L Q1 > W/L Q2 so Q1 can “pull down” Vout § nMOS NOR gate c = a+b (a) NMOS off (b) NMOS on want to realize resistor with a transistor § nMOS NAND gate § Including transistor resistance c = ab rds º channel resistance RL >> rds so output close to 0V Dr. Joseph Elias; Dr. Andrew Mason 2 Class 08: NMOS, Pseudo-NMOS NMOS (Martin c. 1) • General nMOS schematic Examples: depletion-load nMOS logic – single load transistor – parallel and series nMOS transistor to complete the compliment of the desired function i.e., they determine when the output is low “0” rather than high “1” Dr. Joseph Elias; Dr. Andrew Mason 3 Class 08: NMOS, Pseudo-NMOS Pseudo-NMOS (Martin c. 4) •NMOS Common-Source Amplifier with •Pseudo-NMOS inverter with PMOS load current sourrce load and load capacitor •Choose W/L so that: •Choose Vbias in between VDD and ground Q2 always on since |Vgs| > |Vtp| Q2 in saturation if (for VDD=3.3) |Vds| > |Veff| > |Vgs| – |Vt| VDD – Vout > |Vgs| - |Vt| Vout < VDD - |Vgs| + |Vt| Vout < 1.65 + Vt < 2.45 Q1 in saturation if Vgs = Vin > Vt Vds > Veff > Vgs – Vt => •Current-source realized with a PMOS transistor Vout > Vin - Vt •Power Dissipation: Veff = Vgs - Vt output low (Vin is high): P = IL * VDD Vds = Vgs + Vdg at saturation, Vdg=-Vt output high (Vin is low): P = 0 Valid if: average static dissipation: P = ½ * IL * VDD Veff = |Vds-sat| > |Vgs| - |Vtp| -want drain at least Vt from gate Dr.
    [Show full text]
  • Comparative Analysis of Low Power Adiabatic Logic Circuits in DSM Technology
    International Journal of Engineering Trends and Technology (IJETT) – Volume-45 Number3 -March 2017 Comparative Analysis of Low Power Adiabatic Logic Circuits in DSM Technology Shaefali Dixit #1, Ashish Raghuwanshi #2, # PG Student [VLSI], Dept. of ECE, IES college of Eng. Bhopal, RGPV Bhopal, M.P. India Abstract— With the continuous scaling down of dissipation energy loss takes place. While in technology, in the field of integrated circuit design, semiconductor devices, the charge transfer between low power dissipation has become one of the primary different nodes is the process of energy exchange and focus of the research. With the increasing demand for different techniques can be used for minimizing this low power devices adiabatic logic gates proves to be energy loss due to charge transfer. While fully an effective solution. This paper investigates different adiabatic operation is the ideal condition of a circuit adiabatic logic families such as ECRL, 2N-2N2P and operation, in practical cases partial adiabatic operation PFAL. The main aim of this paper is to simulate of circuit is used which gives considerable various logic gates using conventional CMOS and performance. different adiabatic logic families, and thus compare In conventional CMOS circuits the energy stored in for the effectiveness in terms of lower power load capacitors was dissipated to ground. While, dissipation. All simulations are carried out using adiabatic logic, in contrast, offers a way to reuse this HSPICE at 65nm technology with supply voltage is 1V energy and thus prevents the wastage of this energy. at 100MHz frequency, for fair comparison of results By adding the ideas of both the conventional and the W/L ratio of all the circuit is same.
    [Show full text]
  • 3. Implementing Logic in CMOS
    3. Implementing Logic in CMOS Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2020 September 3, 2020 ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 1 / 37 Static CMOS Circuits N- and P-channel Networks N- and P-channel networks implement logic functions Each network connected between Output and VDD or VSS Function defines path between the terminals ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 1 / 37 Duality in CMOS Networks Straightforward way of constructing static CMOS circuits is to implement dual N- and P- networks N- and P- networks must implement complementary functions Duality sufficient for correct operation (but not necessary) ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 2 / 37 Constructing Complex Gates Example: F = (A · B) + (C · D) 1 Take uninverted function F = (A · B) + (C · D) and derive N-network 2 Identify AND, OR components: F is OR of AB, CD 3 Make connections of transistors ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 3 / 37 Construction of Complex Gates, Cont'd 4 Construct P-network by taking complement of N-expression (AB + CD), which gives the expression, (A + B) · (C + D) 5 Combine P and N circuits ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 4 / 37 Layout of Complex Gate AND-OR-INVERT (AOI) gate Note: Arbitrary shapes are not allowed in some nanoscale design rules ECE Department, University of Texas at Austin Lecture 3.
    [Show full text]
  • Designing Combinational Logic Gates in Cmos
    CHAPTER 6 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS In-depth discussion of logic families in CMOS—static and dynamic, pass-transistor, nonra- tioed and ratioed logic n Optimizing a logic gate for area, speed, energy, or robustness n Low-power and high-performance circuit-design techniques 6.1 Introduction 6.3.2 Speed and Power Dissipation of Dynamic Logic 6.2 Static CMOS Design 6.3.3 Issues in Dynamic Design 6.2.1 Complementary CMOS 6.3.4 Cascading Dynamic Gates 6.5 Leakage in Low Voltage Systems 6.2.2 Ratioed Logic 6.4 Perspective: How to Choose a Logic Style 6.2.3 Pass-Transistor Logic 6.6 Summary 6.3 Dynamic CMOS Design 6.7 To Probe Further 6.3.1 Dynamic Logic: Basic Principles 6.8 Exercises and Design Problems 197 198 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS Chapter 6 6.1Introduction The design considerations for a simple inverter circuit were presented in the previous chapter. In this chapter, the design of the inverter will be extended to address the synthesis of arbitrary digital gates such as NOR, NAND and XOR. The focus will be on combina- tional logic (or non-regenerative) circuits that have the property that at any point in time, the output of the circuit is related to its current input signals by some Boolean expression (assuming that the transients through the logic gates have settled). No intentional connec- tion between outputs and inputs is present. In another class of circuits, known as sequential or regenerative circuits —to be dis- cussed in a later chapter—, the output is not only a function of the current input data, but also of previous values of the input signals (Figure 6.1).
    [Show full text]
  • Super-Threshold Adiabatic Finfet SRAM with PAL-2N Logic
    Metallurgy and heat treatment of metals Super-Threshold Adiabatic FinFET SRAM with PAL-2N Logic Yuejie Zhang, Jianping Hu, Tianfang Ma, Beibei Qi Faculty of Information Science and Technology, Ningbo University, Ningbo 315211, China Corresponding author is Jianping Hu Abstract With IC process scaling, the leakage consumption has been an important factor in the power consumption of IC chips, which limits the scaling of SRAM. The FinFET device has the advantage in lower leakage current and higher on-state current than the CMOS devices. In this paper, a FinFET SRAM is verified by using adiabatic com- puting. All the circuits of the SRAM except for the storage array are realized by PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) circuits. The storage uses 8T cell that can improve the read margin and keep the write current against the synchronous read/write disturb. All circuits are simulated with HSPICE at a PTM (Predictive Technology Model) 32nm FinFET technology. The results indicated that the energy consumption of the adiabatic FinFET SRAM decreased 49% compared with the SRAM based on CMOS devices. Keywords: SUPER-THRESHOLD, SRAM, ADIABATIC, FINFET, LOW POWER 1. Introduction age current from supply to the ground, and T is oper- The power consumption has been a critical con- ating cycle of the circuits. cern in the VLSI circuit design. Especially the power The adiabatic circuits have advantages compared consumption of embedded SRAM is a significant with the conventional CMOS circuits in low power concern in processors [1]. The SRAM circuits have aspects [5]. The conventional CMOS circuits will large storage density and small access latency, and consume a portion of energy in the form of heat dissi- thus it is used extensively in processors as on-chip pation.
    [Show full text]
  • The Depletion Load.Doc 1/5
    11/19/2004 The Depletion Load.doc 1/5 The Depletion Load Say we connect the gate of a depletion NMOS to its source— we now have a two-terminal device! This device is called a depletion load. Since the depletion load is a two-terminal device, its behavior is defined by the i + relationship between the voltage v across the v device and the current i through it. − For example, a resistor is a two terminal device whose behavior (i.e., its The Depletion Load relationship between i and v) is defined by Ohm’s Law (ivR= ). Although the depletion load is decidedly not a resistor, its i -v relationship does have some similarities with Ohm’s Law. Q: So what is “Ohm’s Law” for a depletion load (i.e., what is ifv= ())? Jim Stiles The Univ. of Kansas Dept. of EECS 11/19/2004 The Depletion Load.doc 2/5 A: A result easily found by implementing our knowledge of depletion MOSFETs! For a depletion load, we find that: iD + iiD = vGS = 0 vDS + vvDS = vGS vGS−VV t=− t − − Q: But since vGS = 0, isn’t the NMOS device in cutoff? A: Nope! Notice that this is a depletion MOSFET, and a depletion MOSFET will conduct when vGS = 0! Thus the MOSFET in a depletion load will always be either in: a) triode or b) saturation. a) Depletion load MOSFET is in triode if: vDS <vVGS− t vV<−0 t vV<−t Jim Stiles The Univ. of Kansas Dept. of EECS 11/19/2004 The Depletion Load.doc 3/5 Therefore, the current will be: =−−⎡ 2 ⎤ iKDDSDS⎣2( vGS Vvv t ) ⎦ =−−⎡⎤2 iK⎣⎦20() Vvvt =−⎡⎤ −2 iK⎣⎦2 Vvvt b) Depletion load MOSFET is in saturation if: vDS >−vVGS t vV>−0 t vV>−t Therefore, the current will be: 2 vDS iKvVD =−+()GS t ro 2 v iK=−+()0 V t r o Channel-Length 2 v Modulation! iKV=−()t + ro 2 v iKV=+t ro where in this case: 111 ro ===222 λKv()GS− V t λKV()0 − t λVt Jim Stiles The Univ.
    [Show full text]
  • ECE 410: VLSI Design Course Lecture Notes (Uyemura Textbook)
    ECE 410: VLSI Design Course Lecture Notes (Uyemura textbook) Professor Andrew Mason Michigan State University ECE 410, Prof. A. Mason Lecture Notes Page 2.1 CMOS Circuit Basics • CMOS = complementary MOS drain source – uses 2 types of MOSFETs gate gate to create logic functions •nMOS source drain nMOS pMOS •pMOS • CMOS Power Supply VDD CMOS – typically single power supply + CMOS VDD logic = – VDD, with Ground reference - logic circuit circuit • typically uses single power supply • VDD varies from 5V to 1V V •Logic Levels VDD logic 1 – all voltages between 0V and VDD voltages – Logic ‘1’ = VDD undefined – Logic ‘0’ = ground = 0V logic 0 voltages ECE 410, Prof. A. Mason Lecture Notes Page 2.2 Transistor Switching Characteristics •nMOS drain Vout nMOS –switching behavior gate • on = closed, when Vin > Vtn Vin nMOS – Vtn = nMOS “threshold voltage” + Vgs > Vtn = on Vgs – Vin is referenced to ground, Vin = Vgs - source • off = open, when Vin < Vtn •pMOS + source pMOS –switching behavior Vsg • on = closed, when Vin < VDD - |Vtp| - pMOS – |Vtp| = pMOS “threshold voltage” magnitude Vin Vsg > |Vtp| = on gate – Vin is referenced to ground, Vin = VDD-Vsg Vsg = VDD - Vin • off = open, when Vin > VDD - |Vtp| drain Rule to Remember: ‘source’ is at • lowest potential for nMOS • highest potential for pMOS ECE 410, Prof. A. Mason Lecture Notes Page 2.3 Transistor Digital Behavior •nMOS drain Vout nMOS Vin Vout (drain) gate Vin nMOS 1 Vs=0 device is ON + Vgs > Vtn = on 0 ? device is OFF Vgs - source •pMOS Vin Vout (drain) pMOS + source 1 ? device is OFF Vsg 0 Vs=VDD=1 device is ON - pMOS Vin Vsg > |Vtp| = on gate Vsg = VDD - Vin Vin drain pMOS Vout VDD off VDD-|Vtp| on Notice: on When Vin = low, nMOS is off, pMOS is on When Vin = high, nMOS is on, pMOS is off Vtn off Æ Only one transistor is on for each digital voltage nMOS ECE 410, Prof.
    [Show full text]
  • Monolithic Integration of Gan-Based NMOS Digital Logic Gate Circuits with E-Mode Power Gan Moshemts
    1 Proceedings of the 30th International Symposium on Power Semiconductor Devices & ICs May 13-17, 2018, Chicago, USA View metadata, citation and similar papers at core.ac.uk brought to you by CORE Monolithic Integration of GaN-Based NMOSprovided by Infoscience - ÉcoleDigital polytechnique fédérale de Lausanne Logic Gate Circuits with E-Mode Power GaN MOSHEMTs Minghua Zhu and Elison Matioli Power and Wide-band-gap Electronics Research Laboratory (POWERLAB) École Polytechnique Fédérale de Lausanne (EPFL) Lausanne, Switzerland minghua.zhu@epfl.ch, elison.matioli@epfl.ch Abstract— In this work, we demonstrate high-performance NOT NAND NOR NMOS GaN-based logic gates including NOT, NAND, and NOR 5 by integration of E/D-mode GaN MOSHEMTs on silicon ()WL/ 4 α = E ()WL/ substrates. The load-to-driver resistance ratio was optimized in Vout Vout Vout D (V) 3 these logic gates by using a multi-finger gate design of E-mode α =1 out α GaN MOSHEMT to increase the logic swing voltage and noise V 2 =2 α α=4 margins, and reduce the transition periods. State-of-the-art Vin VA VA VB 1 α=10 NMOS inverter was achieved with logic swing voltage of 4.93 V V at a supply voltage of 5 V, low-input noise margin of 2.13 V and B 0 (a) (c) 012345 high-input noise margin of 2.2 V at room temperature. Excellent E-mode Vin (V) high temperature performance, at 300°C, was observed with a D-mode GND Vin Vout VDD logic swing of 4.85 V, low-input noise margin of 1.85 V and high- Vin NOT output noise margin of 2.2V.
    [Show full text]