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Bicmos LOGIC CIRCUIS CHAPTER 12 BiCMOS LOGIC CIRCUIS 12.1. Introduction The signal propagation delay due to large interconnect capacitances is a major factor which limits the performance of CMOS digital integrated circuits. The system speed is ultimately restricted by the current-driving capability of CMOS gates that drive large capacitive loads, such as the word lines in memory arrays, or data bus lines between large logic blocks. The problem of driving large off-chip as well as on-chip loads is tradition- ally solved by using specific CMOS buffer circuits with enhanced current driving capabilities, which will be examined in further detail in Chapter 13. Most of these buffer configurations require a significant amount of silicon area for improvement in the signal propagation delay. Consider a large capacitive load being driven by a CMOS inverter circuit, which in turn is driven by another CMOS inverter, or any CMOS logic gate in general, as shown in Fig. 12.1. Assume that the propagation delay of the output buffer is represented by Tot, and the propagation delay of the entire two-stage structure is represented by rotal. Simple dynamic analysis suggests that, to drive a large capacitive load with a specified propagation delay, we have to design the output buffer with sufficiently large transistor channel widths, Wn and W . However, simply increasing the transistor dimensions will not necessarily help to recfuce the propagation delay time. 492 As we make the channel widths of the nMOS and the pMOS transistors larger, the proportionally increasing drain parasitics will eventually annihilate the speed improve- CHAPTER 12 ment to be gained by larger transistor sizing. Thus, the output stage propagation delay may not be reducible beyond a certain limit due to the increase in drain parasitics, as illustrated in Fig. 12.2. In fact, the overall delay of the two-stage structure shown in Fig. 12.1 will even increasewith larger W, and W , because of the large gate capacitance being imposed on the first stage. Tout ttotal Vout >0 Wn, p load Figure 12.1. A two-stage CMOS buffer structure used for driving a large capacitive load. T Wn, Wp Figure 12.2. Propagation delay of the CMOS buffer vs. transistor size in the output stage. The only feasible solution using conventional CMOS structures is to build a tapered or scaled buffer chain, consisting of several stages which gradually increase in size from the input stage toward the output. The detailed design issues associated with scaled buffer chains will be investigated in Chapter 13. Yet scaled or tapered buffer structures typically require a large silicon area to implement, which increases the overall cost, especially if many on-chip and off-chip loads must be considered. In comparison, bipolar junction transistors (BJTs) have more current driving 493 capability, and hence, can overcome such speed bottlenecks using less silicon area. However, the power dissipation of bipolar logic gates is typically one or two orders of BiCMOS magnitude larger than that of comparable CMOS gates. Therefore, such all-bipolar high- Logic Circuits speed VLSI circuits are difficult to realize and require very elaborate heat-sink arrange- ments. An alternative solution to the problem of driving large capacitive loads can be provided by merging CMOS and bipolar devices (BiCMOS) on chip. Taking advantage of the low static power consumption of CMOS and the high current driving capability of the bipolar transistor during transients, the BiCMOS configuration can combine the "best of both worlds" (Fig. 12.3). In view of the limited driving capabilities of MOS transistors 1 Out Vin Figure 12.3. A typical BiCMOS inverter circuit, with four MOSFETs and two BJTs. in general, the BiCMOS combination has significant advantages to offer, such as improved switching speed and less sensitivity with respect to the load capacitance. In general, BiCMOS logic circuits are not bipolar-intensive, i.e. most logic operations are performed by conventional CMOS subcircuits, while the bipolar transistors are used only when high on-chip or off-chip drive capability is required. The most significant drawback of the BiCMOS circuits lies in the increased fabrication process complexity. The fabrication of the bipolar transistors involves more process steps beyond the CMOS process. But many of the conventional CMOS process steps can be utilized to concurrently fabricate bipolar transistor structures along with the MOS transistors, as shown in the simplified cross-section in Fig. 12.4. For example, the 494 process used to create the n-well (n-tub) on a p-type substrate can also be used to create the n-type collector region of the npn bipolar transistor. The source and drain diffusion CHAPTER 12 steps in the CMOS process can be used to form the emitter region and the base contact region of the bipolar transistor. The silicided polysilicon gate of the MOS transistor forms the emitter contact. In fact, the only bipolar fabrication step which cannot be adopted from the CMOS process is the creation of the base region. The BiCMOS fabrication process typically requires only 3-4 masks in addition to the well-established CMOS process. npn Bipolar Transistor pMOS Transistor nMOS Transistor Figure 12.4. Simplified cross-section showing an npn bipolar transistor, an n-channel MOS transistor, and a p-channel MOS transistor fabricated on the same p-type silicon substrate. Notice that many standard CMOS process steps can be used to create bipolar and MOS transistors side- by-side on the chip. In the following sections, we will present the basic building blocks of BiCMOS logic circuits, discuss the static and dynamic behavior of BiCMOS circuits, and examine some applications. To provide the necessary analytical basis for the upcoming discussions, we start by investigating the structure and the operation of the bipolar junction transistor (BJT). 12.2. Bipolar Junction Transistor (BJT): Structure and Operation The simplified cross-section of an npn bipolar junction transistor (BJT) is shown in Fig. 12.5. The structure consists of several regions and layers of doped silicon, which essentially form the three terminals of the device: emitter (E), base (B), and collector (C). The npn-type bipolar transistor shown in Fig. 12.5 is fabricated on a p-type Si substrate. In full-bipolar ICs, a lightly doped n-type epitaxial layer created on top of the p-type substrate serves as the collector (note: in BiCMOS ICs, the n-well is used as the collector region). The collector contact region is doped with a higher concentration of n-type impurities in order to reduce the contact resistance. The base region is created by forming a p-type diffusion in the n-type epitaxial layer, and the heavily doped n-type emitter is formed within this p-type base diffusion region. 495 Emitter (E) Base (B) Collector (C) BiCMOS Logic Circuits Figure 12.5. Cross-section of an npn-type bipolar junction transistor (BJT). The rectangular slice highlighted in Fig. 12.5 represents the basic functional BJT device, which essentially consists of two back-to-back connected pnjunctions. This basic structure is shown separately in Fig. 12.6 with applied bias voltages, VBE and VCB. Notice that with the voltage source polarities shown here, the base-emitter junction is forward- biased, whereas the base-collector junction is reverse-biased. We will call this particular operating mode the forwardactive mode. The circuit symbol of the npn transistor is also shown in Fig. 12.6. E B C 0 0 VBE Figure 12.6. The simplified view of the bipolar junction transistor (BJT) biased in the forward active mode with VBE and V, and the corresponding circuit symbol. Note that the depletion regions at both pn junctions are also highlighted. BJT Operation:A Qualitative View Underthe bias conditions shown in Fig. 12.6, the positivebase-emitter voltage VBEcauses the base-emitter pn junction to become forward-biased and to conduct a current which corresponds to the emitter terminal current IE. The emitter current consists of two 496 components: electrons injected from the emitter into the base region, and holes injected from the base into the emitter. Since the doping concentration of the emitter region is CHAPTER 12 much higher than that of the base region, the magnitude of the injected electron current component is larger than the injected hole current component. The injected electrons which enter the very thin base region are the minority carriers in the p-type base. Their concentration is highest at the emitter side of the base and lowest (zero) at the collector side of the base region. The reason for the zero concentration at the collector side is that the positive collector voltage VCB causes the electrons at the collector-base junction to be swept across the depletion region, and into the collector. Thus, electrons injected from the emitter into the base region will diffuse toward the collector, since the local electron concentration profile decreases in that direction. The diffusion current made up of electrons in the base is directly proportional to the minority carrier concentration difference between the emitter side and the collector side of the base. Electrons that diffuse through the thin base region and reach the collector junction will be swept into the collector, making up the collector current Ic' Therefore, we can see that the amount of the collector current depends on the amount of electrons which successfully diffuse through the base region. Ideally, it is preferred that almost all of the electrons injected into the base at the emitter junction diffuse through the base region, reach the collector junction and are swept into the collector region, thus making the collector current IC approximately equal to the emitter current E In order to meet this requirement, the thickness W of the base region must be much smaller than the diffusion length LD of electrons in the base, i.e., W <<LD.
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