Digital Logic and Design (Course Code: EE222) Ltlecture 6: Lliogic Famili Es
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Lecture17 08 04 2010
EE40 Lecture 17 Josh Hug 8/04/2010 EE40 Summer 2010 Hug 1 Logistics • HW8 will be due Friday • Mini-midterm 3 next Wednesday – 80/160 points will be a take-home set of design problems which will utilize techniques we’ve covered in class • Handed out Friday • Due next Wednesday – Other 80/160 will be an in class midterm covering HW7 and HW8 • Final will include Friday and Monday lecture, Midterm won’t – Design problems will provide practice EE40 Summer 2010 Hug 2 Project 2 • Booster lab actually due next week – For Booster lab, ignore circuit simulation, though it may be instructive to try the Falstad simulator • Project 2 due next Wednesday – Presentation details to come [won’t be mandatory, but we will ask everyone about their circuits at some point] EE40 Summer 2010 Hug 3 Project 2 • For those of you who want to demo Project 2, we’ll be doing demos in lab on Wednesday at some point – Will schedule via online survey EE40 Summer 2010 Hug 4 CMOS/NMOS Design Correction • (Sent by email) • My on-the-fly explanation was correct, but not the most efficient way – If your FET circuit is implementing a logic function with a bar over it, i.e. • 푍 = 퐴 + 퐵퐶 + 퐷 + 퐸퐹 퐺 + 퐻 – Then don’t put an inverter at the output, it just makes things harder and less efficient • Sorry, on-the-fly-explanations can be dicey EE40 Summer 2010 Hug 5 CMOS • CMOS Summary: – No need for a pull-up or pull-down resistor • Though you can avoid this even with purely NMOS logic (see HW7) – Greatly reduced static power dissipation vs. -
A Vertical Resonant Tunneling Transistor for Application in Digital Logic Circuits
1028 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 6, JUNE 2001 A Vertical Resonant Tunneling Transistor for Application in Digital Logic Circuits Jürgen Stock, Jörg Malindretos, Klaus Michael Indlekofer, Michael Pöttgens, Arno Förster, and Hans Lüth Abstract—A vertical resonant tunneling transistor (VRTT) has In this paper, we report on the fabrication of a vertical res- been developed, its properties and its application in digital logic onant tunneling transistor (VRTT) with low peak voltage and circuits based on the monostable-bistable transition logic element good peak current control by means of a Schottky gate. The (MOBILE) principle are described. The device consists of a small mesa resonant tunneling diode (RTD) in the GaAs/AlAs material asymmetric behavior of the current-voltage ( ) character- system surrounded by a Schottky gate. We obtain low peak voltages istics is analyzed and the transistors are characterized with re- using InGaAs in the quantum well and the devices show an excel- spect to their peak voltage, peak-to-valley ratio (PVR), peak cur- lent peak current control by means of an applied gate voltage. A rent density, and gate function. We demonstrate the switching self latching inverter circuit has been fabricated using two VRTTs functionality of a self latching inverter circuit consisting of two and the switching functionality was demonstrated at low frequen- cies. VRTTs. Index Terms—Monostable-bistable transition logic element (MOBILE), monostable-to-bistable transition, resonant tunneling II. DEVICE FABRICATION diode (RTD), resonant tunneling transistor. A. Layer Structure The epitaxial structure used to fabricate the VRTT device was I. INTRODUCTION grown by molecular beam epitaxy (MBE) on semi-insulating N recent years, several new memory and logic circuits based (100)-orientated GaAs substrate. -
EE 434 Lecture 2
EE 330 Lecture 6 • PU and PD Networks • Complex Logic Gates • Pass Transistor Logic • Improved Switch-Level Model • Propagation Delay Review from Last Time MOS Transistor Qualitative Discussion of n-channel Operation Source Gate Drain Drain Bulk Gate n-channel MOSFET Source Equivalent Circuit for n-channel MOSFET D D • Source assumed connected to (or close to) ground • VGS=0 denoted as Boolean gate voltage G=0 G = 0 G = 1 • VGS=VDD denoted as Boolean gate voltage G=1 • Boolean G is relative to ground potential S S This is the first model we have for the n-channel MOSFET ! Ideal switch-level model Review from Last Time MOS Transistor Qualitative Discussion of p-channel Operation Source Gate Drain Drain Bulk Gate Source p-channel MOSFET Equivalent Circuit for p-channel MOSFET D D • Source assumed connected to (or close to) positive G = 0 G = 1 VDD • VGS=0 denoted as Boolean gate voltage G=1 • VGS= -VDD denoted as Boolean gate voltage G=0 S S • Boolean G is relative to ground potential This is the first model we have for the p-channel MOSFET ! Review from Last Time Logic Circuits VDD Truth Table A B A B 0 1 1 0 Inverter Review from Last Time Logic Circuits VDD Truth Table A B C 0 0 1 0 1 0 A C 1 0 0 B 1 1 0 NOR Gate Review from Last Time Logic Circuits VDD Truth Table A B C A C 0 0 1 B 0 1 1 1 0 1 1 1 0 NAND Gate Logic Circuits Approach can be extended to arbitrary number of inputs n-input NOR n-input NAND gate gate VDD VDD A1 A1 A2 An A2 F A1 An F A2 A1 A2 An An A1 A 1 A2 F A2 F An An Complete Logic Family Family of n-input NOR gates forms -
Diode Logic). • Explain the Need for Introducing Transistors in the Output (DTL and TTL
Lecture 02: Logic Families R.J. Harris & D.G. Bailey Objectives • Show how diodes can be used to form logic gates (Diode logic). • Explain the need for introducing transistors in the output (DTL and TTL). • Explain why Schottky transistors improve the speed of gates. • Describe the operating principles of CMOS logic gates. • Explain the definitions of noise margin, fanout, propagation delay, rise and fall time. Semester 2 - 2006 Digital Electronics Slide 2 Review of Previous Lecture • You can now: – Describe the important differences between analogue and digital signals. – Show how to represent more than two levels using digital signals. – Manipulate different codes for representing numbers and letters: • natural binary, signed binary, twos complement, offset binary, Gray codes, ASCII characters. – Show how to convert between binary and base 10. – Write down the logic symbols for • AND, OR, NOT, NAND and NOR gates. – Draw up a truth table to represent relationships between inputs and outputs of a logic circuit. Semester 2 - 2006 Digital Electronics Slide 3 Presentation Outline • Diode Transistor Logic • TTL • Schottky TTL • CMOS • Tristate logic outputs • Definitions: – Noise margin, fanout – Timing: rise and fall times, propagation delay – Power dissipation • Power supply decoupling Semester 2 - 2006 Digital Electronics Slide 4 Diode Logic – AND Gate • Recall that a diode behaves like a switch. – When the diode is forward biased, the switch is closed, allowing a current to flow through it. When reverse biased, it is like a switch that is turned off - no current flows. • First we shall look at an AND gate. – If either input A or input B goes low, it will forward bias the corresponding diode. -
CSCE 5730 Digital CMOS VLSI Design
Lecture 2: Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides are borrowed from various books, websites, authors pages, and other sources for academic purpose only. The instructor does not claim any originality. CSCE 5730: Digital CMOS VLSI Design 1 Lecture Outline • Historical development of computers • Introduction to a basic digital computer • Five classic components of a computer • Microprocessor • IC design abstraction level • Intel processor family • Developmental trends of ICs • Moore’s Law CSCE 5730: Digital CMOS VLSI Design 2 Introduction to Digital Circuits CSCE 5730: Digital CMOS VLSI Design 3 What is a digital Computer ? A fast electronic machine that accepts digitized input information, processes it according to a list of internally stored instruction, and produces the resulting output information. List of instructions Æ Computer program Internal storage Æ Memory CSCE 5730: Digital CMOS VLSI Design 4 Different Types and Forms of Computer • Personal Computers (Desktop PCs) • Notebook computers (Laptop computers) • Handheld PCs • Pocket PCs • Workstations (SGI, HP, IBM, SUN) • ATM (Embedded systems) • Supercomputers CSCE 5730: Digital CMOS VLSI Design 5 Five classic components of a Computer Computer Processor Memory Devices Control Input Datapath Output (1) Input, (2) Output, (3) Datapath, (4) Controller, and (5) Memory CSCE 5730: Digital CMOS VLSI Design 6 What is a microprocessor ? • A microprocessor is an integrated circuit (IC) built on a tiny piece of silicon. It contains thousands, or even millions, of transistors, which are interconnected via superfine traces of aluminum. The transistors work together to store and manipulate data so that the microprocessor can perform a wide variety of useful functions. -
Logic Families – Characteristics and Types Table of Content
1 Module-1: Logic Families – Characteristics and Types Table of Content 1.1 Introduction 1.2 Logic families 1.3 Positive and Negative logic 1.4 Types of logic families 1.5 Characteristics of logic families 1.6 Evolution of logic families 1.7 Classification of logic families 1.8 Summary Learning Outcome: After completing this module, you will be able to 1. Understand need of logic digital ICs 2. Understand significance of logic families 3. Understand characteristics of logic families 4. Identify different types of logic families 5. Know about evolution of different logic families Digital Electronics Electronic Science 1. Logic families 2 1.1 Introduction The first logic circuit was developed using discrete circuit components. Using advance techniques, these complex circuits can be miniaturized and produced on a small piece of semiconductor material like silicon. Such a circuit is called integrated circuit (IC). Now-a-days, all the digital circuits are available in IC form. While producing digital ICs, different circuit configurations and manufacturing technologies are used. This results into a specific logic family. Each logic family designed in this way has identical electrical characteristics such as supply voltage range, speed of operation, power dissipation, noise margin etc. In this module, we discuss significance and types of logic families. The positive and negative logic and its significance are also discussed. In addition to this, different characteristics which are the key parameters in deciding the logic family for any circuit design are discussed in detail. The module is concluded with explanation of the brief history of the logic family in terms of discrete logic circuits. -
Chapter6-6.Pdf
MEMS1082 Chapter 6 Digital Circuit 6-6 Department of Mechanical Engineering TTL and CMOS ICs , TTL and CMOS output circuit totem pole configuration When the upper transistor is forward biased and the bottom When input is high, the p- transistor is off, the output is type transistor (top) is off, high. The resistor, transistor, n-type is on. So the and diode drop the actual output is pulled low. The output voltage to a value device sinks current typically about 3.4 V. When the lower transistor is forward When input is low, the n- biased and the top transistor is type transistor (bottom) is off, the output is low. off, p-type is on. So the The TTL device sources current output is pulled high. The when there is a high output and device sources current. sinks current when the output is low. TTL device dissipates power continuously regardless of whether the output is high or low. Department of Mechanical Engineering The MOSFET and MOSFET switching states There are presently two general types of MOSFETs: depletion and enhancement. MOS digital ICs use enhancement MOSFETs exclusively The direction of the arrow indicates either P- or N-channel. The symbols show a broken line between the source and drain to indicate that there is normally no conducting channel between these electrodes. Symbol also shows a separation between the gate and the other terminals to indicate the very high resistance (typically around 1012 Ω ) between the gate and channel. Department of Mechanical Engineering The MOSFET and MOSFET switching states Department of Mechanical Engineering N-MOS Inverter Department of Mechanical Engineering N-MOS NAND Gate Department of Mechanical Engineering N-MOS NOR Gate Department of Mechanical Engineering CMOS Logic The complementary MOS (CMOS) logic family uses both P- and N- channel MOSFETs in the same circuit to realize several advantages over the P-MOS and N- MOS families. -
VLSI Overview
Lecture 1: VLSI Overview Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides are borrowed from various books, websites, authors pages, and other sources for academic purpose only. The instructor does not claim any origgyinality. Digital CMOS VLSI Design 1 Lecture Outline • Historical development of computers • ItIntro duc tion toabibasic dig ita l computer • Five classic components of a computer • Microprocessor • IC design abstraction level • Processor Trend • DlDevelopmen tltal tdtrendsof ICs • Moore’s Law Digital CMOS VLSI Design 2 Introduction to Digital Circuits Digital CMOS VLSI Design 3 What is a digital Computer ? A fast electronic machine that accepts digitized input information, processes it according to a list of internally stored instruction, and produces the resulting output information. List of instructions Computer program Internal storage Memory Digital CMOS VLSI Design 4 Different Types and Forms of Computer • Personal Computers (Desktop PCs) • Notebook computers (Laptop computers) • Handheld PCs • Pocket PCs • WkttiWorkstations (SGI, HP, IBM, SUN) • ATM (Embedded systems) • Supercomputers Digital CMOS VLSI Design 5 Five classic components of a Computer Computer Processor Memory Devices Control Input Datapath Output (1) Input, (2) Output, (3) Datapath, (4) Controller, and (5) Memory Digital CMOS VLSI Design 6 What is a microprocessor ? • A microprocessor is an integrated circuit (IC) built on a tiny piece of silicon. It contains thousands, or even millions, of transistors, which are interconnected via superfine traces of aluminum. The transistors work together to store and manipulate data so that the microprocessor can perform a wide variety of useful functions. The particular functions a microprocessor performs are dictated by software. -
Logic Families/Objectives
Logic Families/Objectives – Digital Logic Voltage and Current Parameters • Fan-out, Noise Margin, Propagation Delay – TTL Logic Family – Supply current spikes and ground bounce – TTL Logic Family Evolution –ECL – CMOS Logic Families and Evolution – Logic Family Overview 29/09/2005 EE6471 (KR) 121 Logic Families/Level of Integration – SSI <12 gates/chip Level of integration ever increasing, because of – MSI 12..99 gates/chip •cost •speed – LSI ..1000 gates/chip •size •power – VLSI …10k gates/chip •reliability – ULSI …100k gates/chip Limits of integration: – GSI …1Meg gates/chip •packaging •power dissipation •inductive and capacitive components Note: Ratio gate count/transistor count •flexibility is roughly 1/10 •critical quantity 29/09/2005 EE6471 (KR) 122 Logic Families/Level of Integration – Remember: Gordon Moore, 1975. Predictions: • Mosfet device dimensions scale down by a factor of 2 every 3 years • #transistors/chip double every 1-2 years. Source: G. Sery, Intel 29/09/2005 EE6471 (KR) 123 Logic Families/Static VI Parameters Vcc Vcc Vcc Ioh Iih Iol Iil Voh Vih Vol Vil Parameter Comment Voh(min) High-Level Output Voltage. The minimum voltage level at a logic circuit output in the logical 1 state under defined load conditions. Vol(max) Low-Level Output Voltage. The maximum voltage level at a logic circuit output in the logical 0 state under defined load conditions. 29/09/2005 EE6471 (KR) 124 Logic Families/Static VI Parameters Vcc Vcc Vcc Ioh Iih Iol Iil Voh Vih Vol Vil Parameter Comment Vih(min) High-Level Input Voltage. The minimum voltage level required for a logical 1 at an input. -
Computer Architectures an Overview
Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements. -
Designing Combinational Logic Gates in Cmos
CHAPTER 6 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS In-depth discussion of logic families in CMOS—static and dynamic, pass-transistor, nonra- tioed and ratioed logic n Optimizing a logic gate for area, speed, energy, or robustness n Low-power and high-performance circuit-design techniques 6.1 Introduction 6.3.2 Speed and Power Dissipation of Dynamic Logic 6.2 Static CMOS Design 6.3.3 Issues in Dynamic Design 6.2.1 Complementary CMOS 6.3.4 Cascading Dynamic Gates 6.5 Leakage in Low Voltage Systems 6.2.2 Ratioed Logic 6.4 Perspective: How to Choose a Logic Style 6.2.3 Pass-Transistor Logic 6.6 Summary 6.3 Dynamic CMOS Design 6.7 To Probe Further 6.3.1 Dynamic Logic: Basic Principles 6.8 Exercises and Design Problems 197 198 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS Chapter 6 6.1Introduction The design considerations for a simple inverter circuit were presented in the previous chapter. In this chapter, the design of the inverter will be extended to address the synthesis of arbitrary digital gates such as NOR, NAND and XOR. The focus will be on combina- tional logic (or non-regenerative) circuits that have the property that at any point in time, the output of the circuit is related to its current input signals by some Boolean expression (assuming that the transients through the logic gates have settled). No intentional connec- tion between outputs and inputs is present. In another class of circuits, known as sequential or regenerative circuits —to be dis- cussed in a later chapter—, the output is not only a function of the current input data, but also of previous values of the input signals (Figure 6.1). -
Design of 64-Bit Arithmetic Logic Unit (ALU) Based on BSIM4 Model Using Tanner
IJSART - Volume 2 Issue 10 –OCTOBER 2016 ISSN [ONLINE]: 2395-1052 Design of 64-bit Arithmetic Logic Unit (ALU) Based on BSIM4 Model Using Tanner Pragati Nagdeote1, Prof. Manisha Waje2 1, 2 Department of ENTC 1, 2 SPPU/G.H.Raisoni College of Engineering and Management, Pune, Maharashtra/Zone, India Abstract- Arithmetic circuits play a vital role in computational CMOS provides: an exceptionally low power-delay product, and digital circuits. Arithmetic Logic Unit (ALU) can perform the ability to accommodate millions of devices on a single various arithmetic and logical functions. Proposed 64-bit ALU chip, and flexible, custom design methodologies which permit comprises of different arithmetic functions such as addition, optimization, as required, for lowest cost, lowest power, or subtraction and logical functions like AND logic, OR logic, highest speed. In the recent years, there has been a large NOR logic and NAND logic. ALU always faces the issues of progress in the area of computer systems which are produce power consumption when there are the complex operations, and based on general purpose micro-processors [4]. ALU is therefore to overcome this problem the low power 64-bit ALU one of the most power hungry building blocks in the is designed using adiabatic logic with 180nm CMOS processor, increasing the power and thermal issues. The technology. BSIM4 model is used for the implementation of presence of multiple ALUs in current-day processors further 64-bit full adder, 64-bit AND logic, 64-bit OR logic, 4:1 creates the problem, impacting the circuit reliability and Multiplexer, 2:1 Multiplexer and Proposed design is verified increasing the power cost.