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Digital Logic and Design (Course Code: EE222) Ltlecture 6: Lliogic Famili Es

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Indian Institute of Technology Jodhpur, Year 2018‐2019 Digital Logic and Design (Course Code: EE222) LtLecture 6: LiLogic Fam ilies Course Instructor: Shree Prakash Tiwari EilEmail: sptiwari@iitj .ac.i n Webpage: http://home.iitj.ac.in/~sptiwari/ Course related documents will be uploaded on http://home.iitj.ac.in/~sptiwari/DLD/ Note: The information provided in the slides are taken form text books Digital Electronics (including Mano & Ciletti), and various other resources from internet, for teaching/academic use only 1 Overview •Early families (DL, RTL) • TTL •Evolution of TTL family • CMOS family and its evolution 2 Logic families Diode Logic (DL) •simpp;lest; does not scale •NOT not possible (need = an active element) Resistor-Transistor Logic (RTL) • replace diode switch with a tittransistor switc h •can be cascaded = • large power draw 3 Logic families Diode-Transistor Logic (DTL) • essentially diode logic with transistor amplification • reduced power consumption •faster than RTL = DL AND gate Saturating inverter 4 Logic Families • The bipolar transistor as a logical switch TTL Bipolar Transistor-Transistor Logic (TTL) •First introduced by in 1964 (Texas Instruments) •TTL has shaped digital technology in many ways • Standard TTL family (e.g. 7400) is obsolete •Newer TTL families used (e.g. 74ALS00) 6 TTL Bipolar Transistor-Transistor Logic (TTL) Distinct features •Multi‐emitter transistors 7 TTL A Standard TTL NAND gate 8 TTL A standard TTL NAND gate with open collector output 9 TTL evolution Schottky series (74LS00) TTL •A major slowdown factor in BJTs is due to transistors going in/out of saturation • Shottky diode has a lower forward bias (0.25V) •When BC jijunction would become fdforward biase d, the Schottky diode bypasses the current preventing the transistor from going into saturation 10 TTL family evolution Legygacy: don’t use in Widelyyy used today new designs 11 ECL Emitter-Coupled Logic (ECL) •PROS: Fastest logic family available (~1ns) •CONS: low noise margin and high power dissipation • Operated in emitter coupled geometry (recall different ia l amplifier or emitter‐fllfollower ), transistors are biased and operate near their Q‐point (never near saturation!) •Logic levels. “0”: –1.7V. “1”: –0.8V •Such strange logic levels require extra effort when interfacing to TTL/CMOS logic families. 12 CMOS Logic Gates 2‐input AND Inverter 2‐itinput NOR 2‐itinput NAND 2‐input OR 13 CMOS Logic Gates Number of transistors per logic gate: # of inputs AND / OR NAND / NOR 2 64 3 86 4 10 8 5 12 10 Thus, in terms of transistor count, it is “cheaper” to didesign lilogic ciitircuits using NAND and NOR gates. 14 Logic families: V levels VOH(min) –The minimum voltage level at an output in the logical “1” state under defined load conditions VOL(max) – The maximum voltage level at an output in the logical “0” state under defined load conditions VIH(min) – The minimum voltage required at an input to be recognized as “1” logical state VIL(max) –The maximum voltage required at an input that still will be recognized as “0” logical state V V OH IH VOL VIL 15 Logic families: I requirements IOH –Current flowing into an output in the logical “1” state under specified load conditions IOL –Current flowing into an output in the logical “0” state under specified load conditions IIH – CtCurrent flow ing itinto an itinput when a specifie d HI lllevel is applied to that input IIL – Current flowing into an input when a specified LO level is applied to that input IOH IIH IOL IIL V V OH IH VOL VIL 16 Logic families: fanout Fanout: the maximum number of logic inputs (of the same logic family) that an output can drive reliably I I DC fanout = min( OH , OL ) I IH I IL 17 Logic families: propagation delay TPD,HL TPD,LH TPD,HL – input‐to‐output propagation delay from HI to LO output TPD,LH – input‐to‐output propagation ddlelay from LO to HI output SdSpeed-power prodtduct: TPD Pavg 18 Logic Families • Timing considerations – all gates have a certain propagation delay time, tPD – this is the average of the two switching times 1 tPD 2 (tPHL tPLH ) Logic families: noise margin HI state noise margin: VNH = VOH(min) – VIH(min) LO state noise margin: VNL = VIL(max) –VOL(max) VNH Noise margin: VN = min(VNH,VNL) VNL 20 CMOS Logic Gates • CMOS logic levels and noise immunity CMOS Complimentary MOS (CMOS) • Other variants: NMOS, PMOS (obsolete) •Very low static power consumption • Scaling capabilities (large integration all MOS) •Full swing: rail‐to‐rail output • Things to watch out for: – don’ t leave inputs floating (in TTL these will float to HI, in CMOS you get undefined behaviour) – susceptible to electrostatic damage (g(finger of death) 22 CMOS/TTL power requirements •TTL power essentially constant (no frequency dependence) •CMOS power scales as f C V2 freqqyuency supply volt. eff. capacitance • At high frequencies (>> MHz) CMOS dissipates more power than TTL •Overall advantage is still for CMOS even for very fast chips –only a relatively small portion of complicated circuitry operates at highest frequencies 23 CMOS family evolution obsolete General trend: • Reduction of dynamic losses through successively decreasing supply voltages: 12V 5V 33V3.3V 25V2.5V 18V1.8V CD4000 LVC/ALVC/AVC • Power reduction is one of the keys to progressive growth of integration 24 TTL Overview Logic Noise TPD Trise/fall VIH,min VIL,max VOH,min VOL,max Family Margin • Values typical for Vcc/Vdd = 5V CMOS • When interfacing different families, pay attention to their input/output voltage, current (fanout) specs. 25 Summary • Logic gates are manufactured in various logic families • The ability of a gate to ignore noise is its ‘noise immunity’ • Both MOSFETs and bipolar transistors are used in gates • All logic gates exhibit a propagation delay when responding to changes in their inputs • The most widely used logic families are CMOS and TTL • CMOS is available in a range of forms offering high speed or very low power consumption.
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