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Introduction to Digital Circuits Introduction to Digital Circuits Basic Logic Circuits The CMOS NOR Gate W W ≈ 2.5N L L + VDD PMOS NMOS + VDD N= number of inputs B B Y = A + B Y = A + B A A 1 ©Loberg INTRODUCTION TO DIGITAL CIRCUITS Basic Logic Circuits The CMOS NAND Gate W 2.5 W ≈ L PMOS N L NMOS + VDD N= number of inputs Y = A ⋅ B B A 2 ©Loberg INTRODUCTION TO DIGITAL CIRCUITS Basic Logic Circuits Complex CMOS Gates The pull-up and pull-down networks must have complementary Boolean functions. +VDD Example function : A Pull-up network For the pull-up B PMOS devices Y Y = A ⋅ (B + C ⋅ D) Y and its complement Pull-down For the pull-down A B network Y Y = A ⋅ (B + C ⋅ D) = A + B ⋅ (C + D) NMOS devices A general CMOS logic gate. Both the pull-up and pull-down networks have the same inputs. 3 ©Loberg INTRODUCTION TO DIGITAL CIRCUITS Basic Logic Circuits Complex CMOS Gates It can be shown that the pull-up and pull-down networks + of a complementary CMOS structure are dual networks. VDD (De Morgan) A = ⋅ + ⋅ Y A (B C D) A parallel connection of transistors in the pull-up B Pull-up network network corresponds to a series connection of the C corresponding devices in pull-down network, and vice versa. D Pull-up network : Subnet CD has series connection − Y (C D) Subnet B has parallel connection with CD B (C − D) B Y = A + B ⋅ (C + D) Subnet A has series connection with A − (B (C − D)) Pull-down network previous parallel net A C D Pull-down network : Subnet CD has parallel connection (C D) Subnet B has series connection with CD (B − (C D)) Subnet A has parallel connection with A (B − (C D)) previous net 4 ©Loberg INTRODUCTION TO DIGITAL CIRCUITS Basic Logic Circuits Complex CMOS Gates Example function : Y = B + A + VDD Y = B + A = B ⋅ A Q1 Q3 Q4 A PU Y = B + A B B B A Y Q1 Q2 Q3 Q4 Q5 Q6 PD PU Q5 0 0 1 ON OFF OFF ON OFF ON OFF ON PD OFF ON ON ON OFF OFF OFF ON A 0 1 1 A Q2 Q6 1 0 0 ON OFF OFF OFF ON ON ON OFF 1 1 1 OFF ON ON OFF ON OFF OFF ON PU=Pull-up PD=Pull-down 5 ©Loberg INTRODUCTION TO DIGITAL CIRCUITS Basic Logic Circuits CMOS Transmission Gate Parallel connected NMOS and PMOS transistor, controlled by the C and comlement of C respectively. C NMOS A S D B PMOS C C A B C 6 ©Loberg INTRODUCTION TO DIGITAL CIRCUITS Basic Logic Circuits CMOS Transmission Gate Assumption: C = -1- v = V (1) V (1) G1 C NMOS v = V (0) G1 G2 V (1) A B If A = -1- = V(1) S D G2 ⇒ vGS1 = V (1)− V (1) = 0 NMOS is cutoff C PMOS V (0) vGS2 = V (1)− V (0) > VTO PMOS conducts V (1) NMOS If A = -0- = V(0) C G1 V (0) ⇒ vGS1 = V (1)− V (0) > VTO NMOS conducts A S D B v = V (0)− V (0) = 0 PMOS is cutoff GS2 G2 C PMOS V (0) 7 ©Loberg INTRODUCTION TO DIGITAL CIRCUITS Basic Logic Circuits CMOS Transmission Gate V (0) NMOS Assumption: C = -0- vG1 = V (0) C G1 vG2 = V (1) V (1) A S D B If A = -1- = V(1) G2 C = ( )− ( ) < NMOS is cutoff PMOS ⇒ vGS1 V 0 V 1 0 V (1) vGS2 = V (1)− V (1) = 0 PMOS is cutoff V (0) C NMOS If A = -0- = V(0) V (0) G1 v = V (0)− V (0) = 0 ⇒ GS1 NMOS is cutoff A S D B G2 V (0) < V (1) ⇒ vS2 < vG2 PMOS is cutoff C PMOS V (1) 8 ©Loberg INTRODUCTION TO DIGITAL CIRCUITS Basic Logic Circuits CMOS Transmission Gate A = B when C = −1 − Example of two-input multiplexer = ⋅ + ⋅ C F (A S B S) A 1 A B F v B 0 o S C Transmission gates S +VDD A S vo B S 9 ©Loberg INTRODUCTION TO DIGITAL CIRCUITS Basic Logic Circuits CMOS Families HC High-speed CMOS - for example 74HC30 AHC Advanced High-speed CMOS - for example 74AHC30 HCT High-speed CMOS, TTL compatible AHCT Advanced High-speed CMOS, TTL compatible - for example 74AHCT30 AUC Advanced Ultra-low-voltage CMOS : 0.8-2.5V Product Life Cycle CBT LV AHC LVC 3.3V GTLP HC VME CD4000 ALVC Little Logic ACL AVC FCT CBTLV TVC CB3x PCA/PCF 1.8V AUC AUP LVCxT AUP1T AVCxT Introduction Growth Maturity Decline Obsolescence 10 ©Loberg INTRODUCTION TO DIGITAL CIRCUITS Basic Logic Circuits CMOS Families From book : Digital Design With CMOS load John F. Wakerly V = 4.5 − 5V CC HC AHC HCT AHCT VILmax 1.35V 1.35V 0.8V 0.8V IImax = ±1µA with any Vin VIH min 3.85V 3.85V 2.0V 2.0V IOLmax 0.02mA 0.05mA 0.02mA 0.05mA "Power-supply Standards" VOLmax 0.1V 0.1V 0.1V 0.1V 5V 3.3±0.3V I -20µA -50µA -20µA -50µA 2.5±0.2V OH max 1.8±0.15V V 4.4V 1.5±0.1V OH min 4.4V 4.4V 4.4V 1.2±0.1V An example of input- and output specifications for CMOS families : HC, AHC and AHCT. 11 ©Loberg INTRODUCTION TO DIGITAL CIRCUITS Basic Logic Circuits Bipolar Logic Diode logic Diode-transistor logic (DTL) Transistor-transistor logic (TTL) Emitter-coupled logic (ECL) BiCMOS logic 12 ©Loberg INTRODUCTION TO DIGITAL CIRCUITS Basic Logic Circuits Bipolar Logic Diode Logic AND gate + VCC Inputs Output 0 0 0 0 1 0 1 0 0 1 1 1 A Y Truth table : AND gate B If diode gates are cascaded, the gate needs transistor amplifier to restore logic levels. inverter GND 13 ©Loberg INTRODUCTION TO DIGITAL CIRCUITS Basic Logic Circuits Bipolar Logic Diode Logic OR gate A Y B GND 14 ©Loberg INTRODUCTION TO DIGITAL CIRCUITS Basic Logic Circuits Bipolar Logic Diode-Transistor Logic DTL NAND gate Assumptions : Cut-in voltages : Vγ = 0.5V for transistor Vγ = 0.6V for diode 5V + VCC RC Transistor voltages : R1 (5kΩ) (2.2kΩ) Y V = 0.7V A BE( on ) IB P D1 D2 IC = B VBE( sat ) 0.8V B C I1 I2 VCE( sat ) = 0.2V E R2 (5kΩ) V (0 ) = VCE( sat ) = 0.2V V (1) = VCC = 5.0V NO output load 15 ©Loberg INTRODUCTION TO DIGITAL CIRCUITS Basic Logic Circuits Bipolar Logic Diode-Transistor Logic DTL NAND gate One input, C, is V(0) Other : don't care ⇒ VP = VCE( sat ) + 0.7V = 0.9V + VCC 5V ⇒ RC R1 (5kΩ) 2.2kΩ) Y VP < 0.7V + 0.7V = 1.4V A IB P D1 D2 IC ⇒ B B C I1 I2 Diodes D1 and D2 are cutoff E 0.2V R2 VBE = 0V < Vγ = 0.5V (5kΩ) ⇒ Transistor is cutoff Y = V (1) = VCC = 5.0V 16 ©Loberg INTRODUCTION TO DIGITAL CIRCUITS Basic Logic Circuits Bipolar Logic Diode-Transistor Logic DTL NAND gate Inputs A, B and C are V(1) 5V + VCC RC ⇒ All three input diodes are cutoff R1 (5kΩ) 2.2kΩ) Y A IB ⇒ VP = 0.7V + 0.7V + VBE( sat ) = 2.2V P D1 D2 IC B B C I1 I2 ⇒ E 5.0V R2 (5kΩ) All three input diodes are reverse biased, VD = -2.8V VCC − VP 5V − 2.2V If current gain is high enough, the transistor I1 = = = 0.560mA is saturated. R1 5kΩ ⇒ Y = V (0 ) = VCE( sat ) = 0.2V V 0.8V BE( sat ) − I2 = = = 0.160mA VCC VCE( sat ) Ω IC( sat ) = = 2.182mA R2 5k 2.2kΩ I ⇒ I = I − I = 400µA C( sat ) B 1 2 β F (min) = = 5.46 ⇒ Transistor is saturated. 400µA 17 ©Loberg INTRODUCTION TO DIGITAL CIRCUITS Basic Logic Circuits Bipolar Logic Diode-Transistor Logic DTL NAND gate Assumption : Diode D1 is removed ⇒ Input C is V(0) = 0.2V + ⇒ VP = 0.2V + 0.7V = 0.9V 5V VCC RC R1 (5kΩ) 2.2kΩ) ⇒ VBE = 0.9V − 0.6V = 0.3V Y A IB P D2 IC VBE < Vγ = 0.5V B B C I1 I2 ⇒ Transistor is cutoff E 0.2V R2 (5kΩ) NO output load NM Vγ − VBE = 0.2V ⇒ Noise marginal L is low, because of missing diode D1 18 ©Loberg INTRODUCTION TO DIGITAL CIRCUITS Basic Logic Circuits Bipolar Logic Diode-Transistor Logic DTL NAND gate Ouput is loaded by the standard load. Inputs A, B and C are V(1) V (1) + 5V ⇒ Y = V (0) = VCE(sat) = 0.2V VCC 5V RC R1 (5kΩ) 0.2V (2.2kΩ) 5kΩ I Y P B A I B A 0.9V P D1 D2 IC B Input current I (Standard Load N=1) B C I1 I2 I E V − V 5V − 0.9V R2 I I = CC P = = 0.820mA (5kΩ) 5kΩ 5kΩ N=1 equal inputs DTL NAND gate If we assume that VCE(sat) is independent of collector current ⇒ IC = IC(sat) + NI = 2.182mA + N ×0.82mA 19 ©Loberg INTRODUCTION TO DIGITAL CIRCUITS Basic Logic Circuits Bipolar Logic Diode-Transistor Logic DTL NAND gate Output is loaded by the N standard load. Assumption : V (1) + VCC 5V 5V β F (min) = 30 RC R1 (5kΩ) 0.2V (2.2kΩ) 5kΩ I ⇒ Y P B A I B A P D1 D2 IC B IC = β F (min) I B = 30 × 400µA = 12mA B C I1 I2 I E R2 I IC = IC( sat ) + NI = 12mA (5kΩ) N equal inputs = 2.182mA + N ×0.82mA DTL NAND gate ⇒ N =11 Fan Out 20 ©Loberg INTRODUCTION TO DIGITAL CIRCUITS Basic Logic Circuits Bipolar Logic Schotky transistor Transition time Saturation mode forward active cut off mode Transition time of BJT is long because of storage time of minority-carriers The Schottky transistor is used in digital circuits to increase switching speed.
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