Logic Family
Total Page:16
File Type:pdf, Size:1020Kb
Load more
Recommended publications
-
Allgemeines Abkürzungsverzeichnis
Allgemeines Abkürzungsverzeichnis L. -
Lecture17 08 04 2010
EE40 Lecture 17 Josh Hug 8/04/2010 EE40 Summer 2010 Hug 1 Logistics • HW8 will be due Friday • Mini-midterm 3 next Wednesday – 80/160 points will be a take-home set of design problems which will utilize techniques we’ve covered in class • Handed out Friday • Due next Wednesday – Other 80/160 will be an in class midterm covering HW7 and HW8 • Final will include Friday and Monday lecture, Midterm won’t – Design problems will provide practice EE40 Summer 2010 Hug 2 Project 2 • Booster lab actually due next week – For Booster lab, ignore circuit simulation, though it may be instructive to try the Falstad simulator • Project 2 due next Wednesday – Presentation details to come [won’t be mandatory, but we will ask everyone about their circuits at some point] EE40 Summer 2010 Hug 3 Project 2 • For those of you who want to demo Project 2, we’ll be doing demos in lab on Wednesday at some point – Will schedule via online survey EE40 Summer 2010 Hug 4 CMOS/NMOS Design Correction • (Sent by email) • My on-the-fly explanation was correct, but not the most efficient way – If your FET circuit is implementing a logic function with a bar over it, i.e. • 푍 = 퐴 + 퐵퐶 + 퐷 + 퐸퐹 퐺 + 퐻 – Then don’t put an inverter at the output, it just makes things harder and less efficient • Sorry, on-the-fly-explanations can be dicey EE40 Summer 2010 Hug 5 CMOS • CMOS Summary: – No need for a pull-up or pull-down resistor • Though you can avoid this even with purely NMOS logic (see HW7) – Greatly reduced static power dissipation vs. -
A Vertical Resonant Tunneling Transistor for Application in Digital Logic Circuits
1028 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 6, JUNE 2001 A Vertical Resonant Tunneling Transistor for Application in Digital Logic Circuits Jürgen Stock, Jörg Malindretos, Klaus Michael Indlekofer, Michael Pöttgens, Arno Förster, and Hans Lüth Abstract—A vertical resonant tunneling transistor (VRTT) has In this paper, we report on the fabrication of a vertical res- been developed, its properties and its application in digital logic onant tunneling transistor (VRTT) with low peak voltage and circuits based on the monostable-bistable transition logic element good peak current control by means of a Schottky gate. The (MOBILE) principle are described. The device consists of a small mesa resonant tunneling diode (RTD) in the GaAs/AlAs material asymmetric behavior of the current-voltage ( ) character- system surrounded by a Schottky gate. We obtain low peak voltages istics is analyzed and the transistors are characterized with re- using InGaAs in the quantum well and the devices show an excel- spect to their peak voltage, peak-to-valley ratio (PVR), peak cur- lent peak current control by means of an applied gate voltage. A rent density, and gate function. We demonstrate the switching self latching inverter circuit has been fabricated using two VRTTs functionality of a self latching inverter circuit consisting of two and the switching functionality was demonstrated at low frequen- cies. VRTTs. Index Terms—Monostable-bistable transition logic element (MOBILE), monostable-to-bistable transition, resonant tunneling II. DEVICE FABRICATION diode (RTD), resonant tunneling transistor. A. Layer Structure The epitaxial structure used to fabricate the VRTT device was I. INTRODUCTION grown by molecular beam epitaxy (MBE) on semi-insulating N recent years, several new memory and logic circuits based (100)-orientated GaAs substrate. -
Reduced Swing Domino Techniques for Low Power and High Performance Arithmetic Circuits
Reduced Swing Domino Techniques for Low Power and High Performance Arithmetic Circuits by Shahrzad Naraghi A thesis presented to the University of Waterloo in ful¯llment of the thesis requirement for the degree of Master of Applied Science in Electrical and Computer Engineering Waterloo, Ontario, Canada 2004 °c Shahrzad Naraghi, 2004 I hereby declare that I am the sole author of this thesis. I authorize the University of Waterloo to lend this thesis to other institutions or individuals for the purpose of scholarly research. Shahrzad Naraghi I authorize the University of Waterloo to reproduce this thesis by photocopying or other means, in total or in part, at the request of other institutions or individuals for the purpose of scholarly research. Shahrzad Naraghi ii The University of Waterloo requires the signatures of all persons using or photocopying this thesis. Please sign below, and give address and date. iii Acknowledgements First, I would like to thank my supervisor Professor Manoj Sachdev for his great guidance, support and patience. His advice and support were always greatly appreciated. I also want to thank Dr. Opal and Dr. Anis, my thesis readers. I'd like to thank Bhaskar Chatterjee for his great help on my research; Phil Regier for his great help on computer problems; and my good friends for bringing me joy and laughter during these years that I was away from my family. Most importantly, I'd like to thank my family for their supporting and encouraging com- ments, their love and faith in me. iv Abstract The increasing frequency of operation and the larger number of transistors on the chip, along with slower decrease in supply voltage have led to more power dissipation and high chip power density which cause problems in chip thermal management and heat removal process. -
Diode Logic). • Explain the Need for Introducing Transistors in the Output (DTL and TTL
Lecture 02: Logic Families R.J. Harris & D.G. Bailey Objectives • Show how diodes can be used to form logic gates (Diode logic). • Explain the need for introducing transistors in the output (DTL and TTL). • Explain why Schottky transistors improve the speed of gates. • Describe the operating principles of CMOS logic gates. • Explain the definitions of noise margin, fanout, propagation delay, rise and fall time. Semester 2 - 2006 Digital Electronics Slide 2 Review of Previous Lecture • You can now: – Describe the important differences between analogue and digital signals. – Show how to represent more than two levels using digital signals. – Manipulate different codes for representing numbers and letters: • natural binary, signed binary, twos complement, offset binary, Gray codes, ASCII characters. – Show how to convert between binary and base 10. – Write down the logic symbols for • AND, OR, NOT, NAND and NOR gates. – Draw up a truth table to represent relationships between inputs and outputs of a logic circuit. Semester 2 - 2006 Digital Electronics Slide 3 Presentation Outline • Diode Transistor Logic • TTL • Schottky TTL • CMOS • Tristate logic outputs • Definitions: – Noise margin, fanout – Timing: rise and fall times, propagation delay – Power dissipation • Power supply decoupling Semester 2 - 2006 Digital Electronics Slide 4 Diode Logic – AND Gate • Recall that a diode behaves like a switch. – When the diode is forward biased, the switch is closed, allowing a current to flow through it. When reverse biased, it is like a switch that is turned off - no current flows. • First we shall look at an AND gate. – If either input A or input B goes low, it will forward bias the corresponding diode. -
Digital Logic and Design (Course Code: EE222) Ltlecture 6: Lliogic Famili Es
Indian Institute of Technology Jodhpur, Year 2018‐2019 Digital Logic and Design (Course Code: EE222) LtLecture 6: LiLogic Fam ilies Course Instructor: Shree Prakash Tiwari EilEmail: sptiwari@iitj .ac.i n Webpage: http://home.iitj.ac.in/~sptiwari/ Course related documents will be uploaded on http://home.iitj.ac.in/~sptiwari/DLD/ Note: The information provided in the slides are taken form text books Digital Electronics (including Mano & Ciletti), and various other resources from internet, for teaching/academic use only 1 Overview •Early families (DL, RTL) • TTL •Evolution of TTL family • CMOS family and its evolution 2 Logic families Diode Logic (DL) •simpp;lest; does not scale •NOT not possible (need = an active element) Resistor-Transistor Logic (RTL) • replace diode switch with a tittransistor switc h •can be cascaded = • large power draw 3 Logic families Diode-Transistor Logic (DTL) • essentially diode logic with transistor amplification • reduced power consumption •faster than RTL = DL AND gate Saturating inverter 4 Logic Families • The bipolar transistor as a logical switch TTL Bipolar Transistor-Transistor Logic (TTL) •First introduced by in 1964 (Texas Instruments) •TTL has shaped digital technology in many ways • Standard TTL family (e.g. 7400) is obsolete •Newer TTL families used (e.g. 74ALS00) 6 TTL Bipolar Transistor-Transistor Logic (TTL) Distinct features •Multi‐emitter transistors 7 TTL A Standard TTL NAND gate 8 TTL A standard TTL NAND gate with open collector output 9 TTL evolution Schottky series (74LS00) TTL •A major -
Chapter 6 PROBLEMS
1 Chapter 6 Problem Set Chapter 6 PROBLEMS 1. [E, None, 4.2] Implement the equation X = ((A + B) (C + D + E) + F) G using complemen- tary CMOS. Size the devices so that the output resistance is the same as that of an inverter with an NMOS W/L = 2 and PMOS W/L = 6. Which input pattern(s) would give the worst and best equivalent pull-up or pull-down resistance? Solution Rewriting the output expression in the form X = ((A + B) (C + D + E) + F) G = ((AB + CDE)F) + G allows us to build the pulldown network by inspection (parallel devices imple- ment an OR, and series devices implement an AND). The pullup network is the dual of the pulldown network. A B 24 24 F 12 C 24 D 24 E 24 G 12 X A 8 C 12 G 2 B 8 D 12 E 12 F 4 The plot shows sizes that meet the requirement - in the worst case, the output resistance of the circuit matches the output resistance of an inverter with NMOS W/L=2 and PMOS W/L=6. The worst case pull-up resistance occurs whenever a single path exists from the output node to Vdd. Examples of vectors for the worst case are ABCDEFG=1111100 and 0101110. The best case pull-up resistance occurs when ABCDEFG=0000000. The worst case pull-down resistance occurs whenever a single path exists from the out- put node to GND. Examples of vectors for the worst case are ABCDEFG=0000001 and 0011110. The best case pull-down resistance occurs when ABCDEFG=1111111. -
Logic Families – Characteristics and Types Table of Content
1 Module-1: Logic Families – Characteristics and Types Table of Content 1.1 Introduction 1.2 Logic families 1.3 Positive and Negative logic 1.4 Types of logic families 1.5 Characteristics of logic families 1.6 Evolution of logic families 1.7 Classification of logic families 1.8 Summary Learning Outcome: After completing this module, you will be able to 1. Understand need of logic digital ICs 2. Understand significance of logic families 3. Understand characteristics of logic families 4. Identify different types of logic families 5. Know about evolution of different logic families Digital Electronics Electronic Science 1. Logic families 2 1.1 Introduction The first logic circuit was developed using discrete circuit components. Using advance techniques, these complex circuits can be miniaturized and produced on a small piece of semiconductor material like silicon. Such a circuit is called integrated circuit (IC). Now-a-days, all the digital circuits are available in IC form. While producing digital ICs, different circuit configurations and manufacturing technologies are used. This results into a specific logic family. Each logic family designed in this way has identical electrical characteristics such as supply voltage range, speed of operation, power dissipation, noise margin etc. In this module, we discuss significance and types of logic families. The positive and negative logic and its significance are also discussed. In addition to this, different characteristics which are the key parameters in deciding the logic family for any circuit design are discussed in detail. The module is concluded with explanation of the brief history of the logic family in terms of discrete logic circuits. -
Famílias De Circuitos Lógicos
FAMÍLIAS DE CIRCUITOS LÓGICOS Famílias lógicas consistem de um conjunto de circuitos integrados implementados para cobrir um determinado grupo de funções lógicas que possuem características de fabricação e elétricas similares. O desenvolvimento das famílias lógicas é uma conseqüência da evolução das técnicas de fabricação e necessidades de aplicação (velocidade, potência, etc.). CLASSIFICAÇÃO PELO ELEMENTO CHAVEADOR: • Transistor Bipolar • Transistor MOS Tecnologias-Demantova 1 Transistor Bipolar: Tecnologias-Demantova 2 Transistor MOS: Tecnologias-Demantova 3 SUB FAMÍLIAS: • BIPOLAR: -DTL (Diode Transistor Logic, Lógica de Diodos e Transistores); -DCTL (Direct Coupled Transistor Logic, Lógica de Transistores diretamente acoplados); -RTL (Resistor Transistor Logic, Lógica de Transistores e Resistores); -RCTL (Resistor Capacitor Transistor Logic, RTL com Capacitores); -HTL (High Threshold Logic, Lógica de alto Limiar); -TTL (Transistor Transistor Logic, Lógica Transistor-transistor); -ECL (Emitter Coupled Logic, Lógica de Emissores Acoplados);. • MOS (Metal Oxide Semiconductor Logic, Lógica de MOSFETs): -pMOS (MOSFET canal P); -nMOS (MOSFET canal N); -CMOS (Complementary MOS Logic, Lógica MOS complementar) Tecnologias-Demantova 4 SUB FAMÍLIAS: • BICMOS: -É uma terceira tecnologia que ganha campo hoje em dia mesclando os dois elementos chaveadores em um mesmo componente. Tecnologias-Demantova 5 Volume x Tempo x Custo: Tecnologias-Demantova 6 PARÂMETROS ELÉTRICOS E NÍVEIS LÓGICOS: • IIH: corrente de entrada para nível alto; • IIL: corrente de entrada para nível baixo; • ioh: corrente de saída para nível alto; • IOL: corrente de saída para nível baixo; • VIH: tensão de entrada para nível alto; • VIL: tensão de entrada para nível baixo; • VOH: tensão de saída para nível alto; • VOL: tensão de saída para nível baixo; • TPD: tempo de propagação de uma transição da SAÍDA EM relação a entrada (TPHL, TPLH). -
Designing Combinational Logic Gates in Cmos
CHAPTER 6 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS In-depth discussion of logic families in CMOS—static and dynamic, pass-transistor, nonra- tioed and ratioed logic n Optimizing a logic gate for area, speed, energy, or robustness n Low-power and high-performance circuit-design techniques 6.1 Introduction 6.3.2 Speed and Power Dissipation of Dynamic Logic 6.2 Static CMOS Design 6.3.3 Issues in Dynamic Design 6.2.1 Complementary CMOS 6.3.4 Cascading Dynamic Gates 6.5 Leakage in Low Voltage Systems 6.2.2 Ratioed Logic 6.4 Perspective: How to Choose a Logic Style 6.2.3 Pass-Transistor Logic 6.6 Summary 6.3 Dynamic CMOS Design 6.7 To Probe Further 6.3.1 Dynamic Logic: Basic Principles 6.8 Exercises and Design Problems 197 198 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS Chapter 6 6.1Introduction The design considerations for a simple inverter circuit were presented in the previous chapter. In this chapter, the design of the inverter will be extended to address the synthesis of arbitrary digital gates such as NOR, NAND and XOR. The focus will be on combina- tional logic (or non-regenerative) circuits that have the property that at any point in time, the output of the circuit is related to its current input signals by some Boolean expression (assuming that the transients through the logic gates have settled). No intentional connec- tion between outputs and inputs is present. In another class of circuits, known as sequential or regenerative circuits —to be dis- cussed in a later chapter—, the output is not only a function of the current input data, but also of previous values of the input signals (Figure 6.1). -
EE 372 Digital Logic Families
EE 372 Digital Logic Families Deborah Won Department of Electrical and Computer Engineering California State University, Los Angeles Winter 2015 Outline Digital Logic Definition Digital IC Design Issues Bipolar Transistor Logic Families CMOS circuits e.g., the AND operation A B Y = A · B 0 0 0 0 1 0 1 0 0 1 1 1 Digital Logic Digital logic = Binary arithmetic performed by transistor circuits. The output represents whether a particular condition, or input state, is TRUE or FALSE. Digital Logic Digital logic = Binary arithmetic performed by transistor circuits. The output represents whether a particular condition, or input state, is TRUE or FALSE. e.g., the AND operation A B Y = A · B 0 0 0 0 1 0 1 0 0 1 1 1 ! acts like a transistor control voltage. Remember: We can get a transistor to act like an ON/OFF switch by forcing the transistor to operate either in its 1. saturation region 2. cutoff region Logic Gate These inputs A and B are actually the input voltage applied to the base of a transistor (or gate for MOS transistor) 2. cutoff region Logic Gate These inputs A and B are actually the input voltage applied to the base of a transistor (or gate for MOS transistor) ! acts like a transistor control voltage. Remember: We can get a transistor to act like an ON/OFF switch by forcing the transistor to operate either in its 1. saturation region Logic Gate These inputs A and B are actually the input voltage applied to the base of a transistor (or gate for MOS transistor) ! acts like a transistor control voltage. -
Comparision on Different Domino Logic Design for High- Performance and Leakage-Tolerant Wide OR Gate
Ajay Kumar Dadoria et al Int. Journal of Engineering Research and Applications www.ijera.com ISSN : 2248-9622, Vol. 3, Issue 6, Nov-Dec 2013, pp.2048-2052 RESEARCH ARTICLE OPEN ACCESS Comparision on Different Domino Logic Design for High- Performance and Leakage-Tolerant Wide OR Gate Uday Panwar*, Ajay Kumar Dadoria** (Department of Electronics and Communication Engineering MANIT Bhopal, M.P., India ABSTRACT - Dynamic logic circuits are used for high performance and high speed applications. Wide OR gates are used in Dynamic RAMs, Static RAMs, high speed processors and other high speed circuits. In spite of their high performance, dynamic logic circuit has high noise and extensive leakage which has caused problems for the circuits. To overcome these problems Domino logic circuits are used which reduce sub-threshold leakage current in standby mode and improve noise immunity for wide OR gates. In this paper we analyze and compare different domino logic design topologies for lowering the sub-threshold leakage current in standby mode, increasing the speed and increasing the noise immunity. We compare power, delay, and unit noise gain (UNG) of different topologies. The simulation results revealed that High Speed Clock Delay Domino (HSCD) circuit gives the better results in terms of reduction in delay and power consumption as compare to other circuits. Keywords - Wide domino circuit, sub-threshold leakage current, delay, noise immunity. I. INTRODUCTION VDD VDD In comparison to static CMOS circuits, dynamic PRECHARGE TRANSISTOR KEEPER TRANSISTOR CMOS circuits have a large number of advantages CLK MP MP2 such as lower number of transistors, low-power, 1 higher speed, short-circuit power free and glitch-free VDD operation.