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Design and Implementation of Novel High Performance Domino Logic

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DESIGN AND IMPLEMENTATION OF NOVEL HIGH PERFORMANCE DOMINO LOGIC A thesis submitted in partial fulfillment of the requirements for the award of the degree of Doctor of Philosophy in VLSI Design and Embedded Systems by SRINIVASA V S SARMA D Roll No: 510EC102 Under the Guidance of Prof. KAMALAKANTA MAHAPATRA Electronics and Communication Engineering Department National Institute of Technology Rourkela-769008 Odisha 2015 DESIGN AND IMPLEMENTATION OF NOVEL HIGH PERFORMANCE DOMINO LOGIC A thesis submitted in partial fulfillment of the requirements for the award of the degree of Doctor of Philosophy in VLSI Design and Embedded Systems by SRINIVASA V S SARMA D Roll No: 510EC102 Under the Guidance of Prof. KAMALAKANTA MAHAPATRA Electronics and Communication Engineering Department National Institute of Technology Rourkela-769008 Odisha 2015 CERTIFICATE This is to certify that the thesis report entitled “DESIGN AND IMPLEMENTATION OF NOVEL HIGH PERFORMANCE DOMINO LOGIC” submitted by Srinivasa V S Sarma D, Roll No: 510EC102, in partial fulfillment of the requirements for the award of the degree of Doctor of Philosophy with specialization in “VLSI Design and Embedded Systems” in Electronics and Communication Engineering at the National Institute of Technology, Rourkela is an authentic work under my supervision and guidance. To the best of my knowledge, the matter embodied in the thesis has not been submitted to any other University / Institute for the award of any Degree or Diploma. Place: NIT ROURKELA Date: Prof. K. K. Mahapatra Electronics & Communication Engineering Department, National Institute of Technology, Rourkela - 769008. Dedicated to My parents ACKNOWLEDGEMENTS This project is by far the most significant accomplishment in my life and it would be impossible without people (especially my family) who supported me and believed in me. I express my deep sense of gratitude to Dr. K. K. Mahapatra, Professor in the Department of Electronics and Communication Engineering, NIT Rourkela for giving me the opportunity to work under him and lending every support at every stage of this research work. I am indebted to his esteemed guidance, constant encouragement and fruitful suggestions from the beginning to the end of this thesis. His trust and support inspired me in the most important moments of making right decisions and I am really blessed to be student of him without whom this work would not have been possible. I am thankful to all my teachers Prof. S.K. Patra, Prof. S. Meher, Prof. D.P.Acharya, Prof.A.K.Swain and all other faculty members for providing a solid background for my studies and research thereafter. My sincere and heart full thanks to Dr. S. K. Sarangi, Director of NIT-Rourkela, for providing the working platform and required research equipment in the department laboratory at NIT. Also, I would like to thank all my classmates and friends (Bhaskar, Govind, Vijay, Preethi, Ramakrishna, Rajesh Patjoshi, Gokulanand and others) of VLSI lab who always encouraged me in the successful completion of my thesis work. I am indebted to the service provided by Ayas sir, sudi, Tom, Sauvagya, Venkat Ratnam and Jagannath who helped me in crucial stage of submission of my thesis. Finally, I thank GOD-Almighty for being with me forever end ever. SRINIVASA V S SARMA D Roll No: 510EC102 i ABSTRACT This dissertation presents design and implementation of novel high performance domino logic techniques with increased noise robustness and reduced leakages. The speed and overhead area became the primary parameters of choice for fabrication industry that led to invention of clocked logic styles named as Dynamic logic and Domino logic families. Most importantly, power consumption, noise immunity, speed of operation, area and cost are the predominant parameters for designing any kind of digital logic circuit technique with effective trade-off amongst these parameters depending on the situation and application of design. Because of its high speed and low overhead area domino logic became process of choice for designing of high speed application circuits. The concerning issues are large power consumption and high sensitivity towards noise. Hence, there is a need for designing new domino methodology to meet the requirements by overcoming above mentioned drawbacks which led to ample opportunities for diversified research in this field. Therefore, the outcome of research must be able to handle the primary design parameters efficiently. Besides this, the designed circuit must exhibit high degree of robustness towards noise. In this thesis, few domino logic circuit techniques are proposed to deal with noise and sub-threshold leakages. Effect of signal integrity issues on domino logic techniques is studied. Furthermore, having been subjected to process corner analysis and noise analysis, the overall performance of proposed domino techniques is found to be enhanced despite a few limitations that are mentioned in this work. Besides this, lector based domino and dynamic node stabilized techniques are also proposed and are investigated thoroughly. Simulations show that proposed circuits are showing superior performance. In addition to this, domino based Schmitt triggers with various hysteresis phenomena are designed and simulated. Pre-layout and post-layout simulation results are compared for proposed Schmitt trigger. Simulations reveal that proposed Schmitt trigger techniques are more noise tolerant than CMOS counterparts. Moreover, a test chip for domino based Schmitt trigger is done in UMC 180 nm technology for fabrication. ii Contents ACKNOWLEDGEMENTS ................................................................................................... i ABSTRACT .......................................................................................................................... ii LIST OF FIGURES ............................................................................................................. vi LIST OF TABLES ................................................................................................................. x ABBREVIATIONS ............................................................................................................ xii CHAPTER 1 .......................................................................................................................... 1 INTRODUCTION ................................................................................................................. 1 1.1 Introduction ............................................................................................................. 1 1.2 History ..................................................................................................................... 2 1.3 Motivation ............................................................................................................... 3 1.4 Objectives of the research work .............................................................................. 3 1.5 Thesis structure and over all contribution ............................................................... 3 1.6 Conclusion ............................................................................................................... 5 CHAPTER 2 .......................................................................................................................... 6 OVERVIEW OF LOGIC STYLES AND RELATED WORK ............................................. 6 2.1 CMOS AND NMOS ............................................................................................... 6 2.2 Different static logic styles .................................................................................... 12 2.2.1 Pseudo N-MOS .............................................................................................. 12 2.2.2 Differential Cascode Voltage Swing Logic (DCVSL) .................................. 13 2.2.3 Pass Transistor Logic ..................................................................................... 14 2.2.4 Differential / Complementary Pass Transistor Logic .................................... 15 2.3 Dynamic CMOS logic design ................................................................................ 17 2.4 Domino logic circuits ............................................................................................ 19 2.4.1 Impact on power consumption ....................................................................... 23 2.4.2 Technique to compensate charge lost, through PMOS keeper ...................... 26 2.5 Conclusion ............................................................................................................. 31 CHAPTER 3 ........................................................................................................................ 32 NOVEL DOMINO LOGIC TOPOLOGIES ........................................................................ 32 3.1 Introduction ........................................................................................................... 32 3.2 Different high-performance noise tolerant circuit techniques ............................... 34 3.2.1 Wide fan-in Domino OR gate-Footless and Footed schemes ........................ 34 iii 3.2.2 Wide fan-in Domino OR gate Diode footed scheme ..................................... 37 3.2.3 Wide fan-in Domino OR gate-Replicated evaluation scheme ....................... 40 3.2.4 Wide fan-in Domino OR gate-Dynamic node footed scheme ....................... 41 3.2.5 Wide fan-in Domino OR gate-Clock delayed single keeper scheme
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