Design and Implementation of Novel High Performance Domino Logic
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Allgemeines Abkürzungsverzeichnis
Allgemeines Abkürzungsverzeichnis L. -
Reduced Swing Domino Techniques for Low Power and High Performance Arithmetic Circuits
Reduced Swing Domino Techniques for Low Power and High Performance Arithmetic Circuits by Shahrzad Naraghi A thesis presented to the University of Waterloo in ful¯llment of the thesis requirement for the degree of Master of Applied Science in Electrical and Computer Engineering Waterloo, Ontario, Canada 2004 °c Shahrzad Naraghi, 2004 I hereby declare that I am the sole author of this thesis. I authorize the University of Waterloo to lend this thesis to other institutions or individuals for the purpose of scholarly research. Shahrzad Naraghi I authorize the University of Waterloo to reproduce this thesis by photocopying or other means, in total or in part, at the request of other institutions or individuals for the purpose of scholarly research. Shahrzad Naraghi ii The University of Waterloo requires the signatures of all persons using or photocopying this thesis. Please sign below, and give address and date. iii Acknowledgements First, I would like to thank my supervisor Professor Manoj Sachdev for his great guidance, support and patience. His advice and support were always greatly appreciated. I also want to thank Dr. Opal and Dr. Anis, my thesis readers. I'd like to thank Bhaskar Chatterjee for his great help on my research; Phil Regier for his great help on computer problems; and my good friends for bringing me joy and laughter during these years that I was away from my family. Most importantly, I'd like to thank my family for their supporting and encouraging com- ments, their love and faith in me. iv Abstract The increasing frequency of operation and the larger number of transistors on the chip, along with slower decrease in supply voltage have led to more power dissipation and high chip power density which cause problems in chip thermal management and heat removal process. -
SRAM Read/Write Margin Enhancements Using Finfets
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 6, JUNE 2010 887 SRAM Read/Write Margin Enhancements Using FinFETs Andrew Carlson, Member, IEEE, Zheng Guo, Student Member, IEEE, Sriram Balasubramanian, Member, IEEE, Radu Zlatanovici, Member, IEEE, Tsu-Jae King Liu, Fellow, IEEE, and Borivoje Nikolic´, Senior Member, IEEE Abstract—Process-induced variations and sub-threshold [1]. Accurate control is essential for high read stability. Sim- leakage in bulk-Si technology limit the scaling of SRAM into ilarly, variability and device leakage affect the writeability of the sub-32 nm nodes. New device architectures are being considered cell. To maintain both desired writeability and read stability of to improve control and reduce short channel effects. Among the SRAM arrays, several radical departures from the conven- the likely candidates, FinFETs are the most attractive option be- cause of their good scalability and possibilities for further SRAM tional design have been considered as follows. performance and yield enhancement through independent gating. 1) Scaling of the traditional six-transistor (6-T) SRAM cell The enhancements to read/write margins and yield are investi- at a slower pace, since a transistor with a larger area is gated in detail for two cell designs employing independently gated more immune to variations. This is a common approach FinFETs. It is shown that FinFET-based 6-T SRAM cells designed in 65- and 45-nm technology nodes; while it still might with pass-gate feedback (PGFB) achieve significant improvements in the cell read stability without area penalty. The write-ability of be applicable to small arrays in future, it fundamentally the cell can be improved through the use of pull-up write gating undermines the objective of technology scaling. -
Design and Implementation of 4 Bit Carry Skip Adder Using Nmos and Pmos Transmission Gate
EasyChair Preprint № 2561 Design and Implementation of 4 Bit Carry Skip Adder Using Nmos and Pmos Transmission Gate Ashutosh Pandey, Harshit Singh, Vivek Kumar Chaubey and Utkarsh Jaiswal EasyChair preprints are intended for rapid dissemination of research results and are integrated with the rest of EasyChair. February 5, 2020 CHAPTER-1 INTRODUCTION In the field of electronics, a digital circuit that performs addition of numbers is called an adder or summer. In various kinds of processors like computers, adders have many applications in the arithmetic logic units, as well as in other parts, where these are used to compute table indices, addresses and similar operations. Mostly, the common adders operate on binary numbers, but they can also be constructed for many other numerical representations, such as excess-3 or binary coded decimal (BCD). It is insignificant to customize the adder into an adder-subtractor unit in situations where negative numbers are represented by one's or two's complement. The usage of power efficient VLSI circuits is required to satiate the perennial need for mobile electronic devices. The calculations in these devices ought to be performed using area efficient and low power circuits working at higher speed. The most elementary arithmetic operation is addition; and the most basic arithmetic component of the processor is the adder. Depending upon the delay, area and power consumption requirements; certain adder implementations such as ripple carry, carry-skip, carry select and carry look ahead are available. When large bit numbers are used, the ripple carry adder (RCA) is not very efficient. With the bit length, there is a linear increase in delay. -
Chapter 6 PROBLEMS
1 Chapter 6 Problem Set Chapter 6 PROBLEMS 1. [E, None, 4.2] Implement the equation X = ((A + B) (C + D + E) + F) G using complemen- tary CMOS. Size the devices so that the output resistance is the same as that of an inverter with an NMOS W/L = 2 and PMOS W/L = 6. Which input pattern(s) would give the worst and best equivalent pull-up or pull-down resistance? Solution Rewriting the output expression in the form X = ((A + B) (C + D + E) + F) G = ((AB + CDE)F) + G allows us to build the pulldown network by inspection (parallel devices imple- ment an OR, and series devices implement an AND). The pullup network is the dual of the pulldown network. A B 24 24 F 12 C 24 D 24 E 24 G 12 X A 8 C 12 G 2 B 8 D 12 E 12 F 4 The plot shows sizes that meet the requirement - in the worst case, the output resistance of the circuit matches the output resistance of an inverter with NMOS W/L=2 and PMOS W/L=6. The worst case pull-up resistance occurs whenever a single path exists from the output node to Vdd. Examples of vectors for the worst case are ABCDEFG=1111100 and 0101110. The best case pull-up resistance occurs when ABCDEFG=0000000. The worst case pull-down resistance occurs whenever a single path exists from the out- put node to GND. Examples of vectors for the worst case are ABCDEFG=0000001 and 0011110. The best case pull-down resistance occurs when ABCDEFG=1111111. -
High Performance Ripple Carry Adder Using Domino
International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056 Volume: 02 Issue: 08 | Nov-2015 www.irjet.net p-ISSN: 2395-0072 HIGH PERFORMANCE RIPPLE CARRY ADDER USING DOMINO LOGIC Dr.J.Karpagam1 , A.Arunadevi2 1 Professor, Department of ECE, KPRIET, Coimbatore, Tamilnadu, India 2 PG Scholar, Department of ECE, KPRIET, Coimbatore, Tamilnadu, India ---------------------------------------------------------------------***--------------------------------------------------------------------- ABSTRACT excessively with a mixer of dynamic and static circuit styles, use of dual supply voltages and dual threshold The demand and popularity of portable electronics is voltages. driving designers to strive for small silicon area, higher speeds, low power dissipation and reliability. Domino logic Domino logic is a clocked logic family which means that circuits are important as it provides better speed and has every single logic gate has a clock signal present. When the lesser transistor requirement when compared to static clock signal turns low, node N0 goes high, causing the CMOS logic circuits. This project presents the design and output of the gate to go low. This represents the only performance of 8-bit Ripple Carry Adder using CMOS mechanism for the gate output to go low once it has been Domino logic targeting at full-custom high speed driven high. The operating period of the cell when its input applications. The constant delay characteristic of this logic clock and output are low is called the recharge phase or style regardless of the logic expression makes it suitable for cycle. The next phase, when the clock is high, is called the implementing complicated logic expression such as addition. evaluate phase or cycle. -
Advanced MOSFET Designs and Implications for SRAM Scaling
Advanced MOSFET Designs and Implications for SRAM Scaling By Changhwan Shin A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Engineering - Electrical Engineering and Computer Sciences in the Graduate Division of the University of California, Berkeley Committee in charge: Professor Tsu-Jae King Liu, Chair Professor Borivoje Nikolić Professor Eugene E. Haller Spring 2011 Advanced MOSFET Designs and Implications for SRAM Scaling Copyright © 2011 by Changhwan Shin Abstract Advanced MOSFET Designs and Implications for SRAM Scaling by Changhwan Shin Doctor of Philosophy in Engineering – Electrical Engineering and Computer Sciences University of California, Berkeley Professor Tsu-Jae King Liu, Chair Continued planar bulk MOSFET scaling is becoming increasingly difficult due to increased random variation in transistor performance with decreasing gate length, and thereby scaling of SRAM using minimum-size transistors is further challenging. This dissertation will discuss various advanced MOSFET designs and their benefits for extending density and voltage scaling of static memory (SRAM) arrays. Using three- dimensional (3-D) process and design simulations, transistor designs are optimized. Then, using an analytical compact model calibrated to the simulated transistor current-vs.-voltage characteristics, the performance and yield of six-transistor (6-T) SRAM cells are estimated. For a given cell area, fully depleted silicon-on-insulator (FD-SOI) MOSFET technology is projected to provide for significantly improved yield across a wide range of operating voltages, as compared with conventional planar bulk CMOS technology. Quasi-Planar (QP) bulk silicon MOSFETs are a lower-cost alternative and also can provide for improved SRAM yield. A more printable "notchless" QP bulk SRAM cell layout is proposed to reduce lithographic variations, and is projected to achieve six-sigma yield (required for terabit-scale SRAM arrays) with a minimum operating voltage below 1 Volt. -
Famílias De Circuitos Lógicos
FAMÍLIAS DE CIRCUITOS LÓGICOS Famílias lógicas consistem de um conjunto de circuitos integrados implementados para cobrir um determinado grupo de funções lógicas que possuem características de fabricação e elétricas similares. O desenvolvimento das famílias lógicas é uma conseqüência da evolução das técnicas de fabricação e necessidades de aplicação (velocidade, potência, etc.). CLASSIFICAÇÃO PELO ELEMENTO CHAVEADOR: • Transistor Bipolar • Transistor MOS Tecnologias-Demantova 1 Transistor Bipolar: Tecnologias-Demantova 2 Transistor MOS: Tecnologias-Demantova 3 SUB FAMÍLIAS: • BIPOLAR: -DTL (Diode Transistor Logic, Lógica de Diodos e Transistores); -DCTL (Direct Coupled Transistor Logic, Lógica de Transistores diretamente acoplados); -RTL (Resistor Transistor Logic, Lógica de Transistores e Resistores); -RCTL (Resistor Capacitor Transistor Logic, RTL com Capacitores); -HTL (High Threshold Logic, Lógica de alto Limiar); -TTL (Transistor Transistor Logic, Lógica Transistor-transistor); -ECL (Emitter Coupled Logic, Lógica de Emissores Acoplados);. • MOS (Metal Oxide Semiconductor Logic, Lógica de MOSFETs): -pMOS (MOSFET canal P); -nMOS (MOSFET canal N); -CMOS (Complementary MOS Logic, Lógica MOS complementar) Tecnologias-Demantova 4 SUB FAMÍLIAS: • BICMOS: -É uma terceira tecnologia que ganha campo hoje em dia mesclando os dois elementos chaveadores em um mesmo componente. Tecnologias-Demantova 5 Volume x Tempo x Custo: Tecnologias-Demantova 6 PARÂMETROS ELÉTRICOS E NÍVEIS LÓGICOS: • IIH: corrente de entrada para nível alto; • IIL: corrente de entrada para nível baixo; • ioh: corrente de saída para nível alto; • IOL: corrente de saída para nível baixo; • VIH: tensão de entrada para nível alto; • VIL: tensão de entrada para nível baixo; • VOH: tensão de saída para nível alto; • VOL: tensão de saída para nível baixo; • TPD: tempo de propagação de uma transição da SAÍDA EM relação a entrada (TPHL, TPLH). -
(12) United States Patent (1O) Patent No.: US 7,489,538 B2 Mari Et Al
mu uuuu ui iiui iiui mu mil uui uui lull uui uuii uu uii mi (12) United States Patent (1o) Patent No.: US 7,489,538 B2 Mari et al. (45) Date of Patent: Feb. 10, 2009 (54) RADIATION TOLERANT COMBINATIONAL 5,406,513 A * 4/1995 Canafis et al . .............. 365/181 LOGIC CELL (Continued) (75) Inventors: Gary R. Maki, Post Falls, ID (US); OTHER PUBLICATIONS Jody W. Gambles, Post Falls, ID (US); Sterling Whitaker, Albuquerque, NM "Ionizing Radiation Effects in MOS Devices and Circuits", Edited by (US) T.P. Ma., Department of Electrical Engineering, Yale University, New Haven Connecticut and Paul V. Dressendorfer, Sandia National (73) Assignee: University of Idaho, Moscow, ID (US) Laboratories, Albuquerque, NM, A Wiley-Interscience Publication, John Wiley & Sons, pp. 484-589. (*) Notice: Subject to any disclaimer, the term of this (Continued) patent is extended or adjusted under 35 U.S.C. 154(b) by 263 days. Primary Examiner Vu A Le (74) Attorney, Agent, or Firm Haverstock & Owens LLP (21) Appl. No.: 11/527,375 (57) ABSTRACT (22) Filed: Sep. 25, 2006 A system has a reduced sensitivity to Single Event Upset (65) Prior Publication Data and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system US 2007/0109865 Al May 17, 2007 includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The Related U.S. Application Data logic block is for implementing a logic function, receiving a (60) Provisional application No. 60/736,979, filed on Nov. -
Designing Combinational Logic Gates in Cmos
CHAPTER 6 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS In-depth discussion of logic families in CMOS—static and dynamic, pass-transistor, nonra- tioed and ratioed logic n Optimizing a logic gate for area, speed, energy, or robustness n Low-power and high-performance circuit-design techniques 6.1 Introduction 6.3.2 Speed and Power Dissipation of Dynamic Logic 6.2 Static CMOS Design 6.3.3 Issues in Dynamic Design 6.2.1 Complementary CMOS 6.3.4 Cascading Dynamic Gates 6.5 Leakage in Low Voltage Systems 6.2.2 Ratioed Logic 6.4 Perspective: How to Choose a Logic Style 6.2.3 Pass-Transistor Logic 6.6 Summary 6.3 Dynamic CMOS Design 6.7 To Probe Further 6.3.1 Dynamic Logic: Basic Principles 6.8 Exercises and Design Problems 197 198 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS Chapter 6 6.1Introduction The design considerations for a simple inverter circuit were presented in the previous chapter. In this chapter, the design of the inverter will be extended to address the synthesis of arbitrary digital gates such as NOR, NAND and XOR. The focus will be on combina- tional logic (or non-regenerative) circuits that have the property that at any point in time, the output of the circuit is related to its current input signals by some Boolean expression (assuming that the transients through the logic gates have settled). No intentional connec- tion between outputs and inputs is present. In another class of circuits, known as sequential or regenerative circuits —to be dis- cussed in a later chapter—, the output is not only a function of the current input data, but also of previous values of the input signals (Figure 6.1). -
EE 372 Digital Logic Families
EE 372 Digital Logic Families Deborah Won Department of Electrical and Computer Engineering California State University, Los Angeles Winter 2015 Outline Digital Logic Definition Digital IC Design Issues Bipolar Transistor Logic Families CMOS circuits e.g., the AND operation A B Y = A · B 0 0 0 0 1 0 1 0 0 1 1 1 Digital Logic Digital logic = Binary arithmetic performed by transistor circuits. The output represents whether a particular condition, or input state, is TRUE or FALSE. Digital Logic Digital logic = Binary arithmetic performed by transistor circuits. The output represents whether a particular condition, or input state, is TRUE or FALSE. e.g., the AND operation A B Y = A · B 0 0 0 0 1 0 1 0 0 1 1 1 ! acts like a transistor control voltage. Remember: We can get a transistor to act like an ON/OFF switch by forcing the transistor to operate either in its 1. saturation region 2. cutoff region Logic Gate These inputs A and B are actually the input voltage applied to the base of a transistor (or gate for MOS transistor) 2. cutoff region Logic Gate These inputs A and B are actually the input voltage applied to the base of a transistor (or gate for MOS transistor) ! acts like a transistor control voltage. Remember: We can get a transistor to act like an ON/OFF switch by forcing the transistor to operate either in its 1. saturation region Logic Gate These inputs A and B are actually the input voltage applied to the base of a transistor (or gate for MOS transistor) ! acts like a transistor control voltage. -
Comparision on Different Domino Logic Design for High- Performance and Leakage-Tolerant Wide OR Gate
Ajay Kumar Dadoria et al Int. Journal of Engineering Research and Applications www.ijera.com ISSN : 2248-9622, Vol. 3, Issue 6, Nov-Dec 2013, pp.2048-2052 RESEARCH ARTICLE OPEN ACCESS Comparision on Different Domino Logic Design for High- Performance and Leakage-Tolerant Wide OR Gate Uday Panwar*, Ajay Kumar Dadoria** (Department of Electronics and Communication Engineering MANIT Bhopal, M.P., India ABSTRACT - Dynamic logic circuits are used for high performance and high speed applications. Wide OR gates are used in Dynamic RAMs, Static RAMs, high speed processors and other high speed circuits. In spite of their high performance, dynamic logic circuit has high noise and extensive leakage which has caused problems for the circuits. To overcome these problems Domino logic circuits are used which reduce sub-threshold leakage current in standby mode and improve noise immunity for wide OR gates. In this paper we analyze and compare different domino logic design topologies for lowering the sub-threshold leakage current in standby mode, increasing the speed and increasing the noise immunity. We compare power, delay, and unit noise gain (UNG) of different topologies. The simulation results revealed that High Speed Clock Delay Domino (HSCD) circuit gives the better results in terms of reduction in delay and power consumption as compare to other circuits. Keywords - Wide domino circuit, sub-threshold leakage current, delay, noise immunity. I. INTRODUCTION VDD VDD In comparison to static CMOS circuits, dynamic PRECHARGE TRANSISTOR KEEPER TRANSISTOR CMOS circuits have a large number of advantages CLK MP MP2 such as lower number of transistors, low-power, 1 higher speed, short-circuit power free and glitch-free VDD operation.