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SRAM Read/Write Margin Enhancements Using Finfets

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SRAM Read/Write Margin Enhancements Using Finfets IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 6, JUNE 2010 887 SRAM Read/Write Margin Enhancements Using FinFETs Andrew Carlson, Member, IEEE, Zheng Guo, Student Member, IEEE, Sriram Balasubramanian, Member, IEEE, Radu Zlatanovici, Member, IEEE, Tsu-Jae King Liu, Fellow, IEEE, and Borivoje Nikolic´, Senior Member, IEEE Abstract—Process-induced variations and sub-threshold [1]. Accurate control is essential for high read stability. Sim- leakage in bulk-Si technology limit the scaling of SRAM into ilarly, variability and device leakage affect the writeability of the sub-32 nm nodes. New device architectures are being considered cell. To maintain both desired writeability and read stability of to improve control and reduce short channel effects. Among the SRAM arrays, several radical departures from the conven- the likely candidates, FinFETs are the most attractive option be- cause of their good scalability and possibilities for further SRAM tional design have been considered as follows. performance and yield enhancement through independent gating. 1) Scaling of the traditional six-transistor (6-T) SRAM cell The enhancements to read/write margins and yield are investi- at a slower pace, since a transistor with a larger area is gated in detail for two cell designs employing independently gated more immune to variations. This is a common approach FinFETs. It is shown that FinFET-based 6-T SRAM cells designed in 65- and 45-nm technology nodes; while it still might with pass-gate feedback (PGFB) achieve significant improvements in the cell read stability without area penalty. The write-ability of be applicable to small arrays in future, it fundamentally the cell can be improved through the use of pull-up write gating undermines the objective of technology scaling. (PUWG) with a separate write word line (WWL). The benefits of 2) Use of assist techniques to enhance read and write mar- these two approaches are complementary and additive, allowing gins. Examples of these techniques include the use of lower for simultaneous read and write yield enhancements when the column supply voltages during write, bitline and wordline PGFB and PUWG designs are used in combination. bias, pulsed bit lines, read-, and write-assist column cir- Index Terms—FinFET, SRAM, variation, pass-gate feedback, cuitry [2], [3]. These techniques aim to increase the array pull-up write gating. robustness with smaller cells, but necessarily lower array efficiency, resulting in larger area. 3) Departure from the conventional 6-T SRAM cell design. I. INTRODUCTION By using a 7- or 8-T cell structure the read and write re- quirements can be decoupled. There is a 20%–30% area RAM needs to track the scaling of digital logic to maintain penalty as compared to a similarly sized 6-T cell; however S the continued scaling of CMOS technology. With scaling this approach may yield smaller cell areas when transistor of linear dimensions by a factor of 0.7, SRAM cell area needs upsizing is needed to maintain stability of the 6-T cell. to scale with a factor of 0.5 with each new technology node. 4) The use of alternate device technologies to obtain robust Traditionally, overhead needed for decoding, column circuitry 6-T SRAM. The use of an alternate device structure that en- and redundancy represented 30% of the array area, usually ex- ables SRAM scaling at the traditional rate would result in pressed as an array efficiency of 70%. SRAM design in deeply the smallest die sizes, but possibly at the cost of increased scaled technologies faces major challenges in overcoming in- process complexity. creasing variability as device dimensions scale down. In partic- This paper focuses on the use of alternative device architec- ular, random dopant fluctuation is a significant cause of device tures for SRAM in which control can be achieved without the threshold voltage variation, especially for SRAM devices, use of channel dopants, thereby greatly reducing device suscep- because its magnitude is inversely proportional to channel area tibility to random dopant fluctuation. Such architectures include fully depleted silicon-on-insulator (FDSOI), FinFETs (vertical Manuscript received March 03, 2008; revised June 30, 2008 and November double gate), triple-gate, and gate-all-around devices [4]–[7]. 23, 2008; accepted January 04, 2009. First published September 01, 2009; cur- Although each of these device architectures provides improved rent version published May 26, 2010. A. Carlson was with the Department of Electrical Engineering and Com- scalability relative to current bulk-Si or partially depleted SOI puter Sciences, University of California, Berkeley, CA 94720 USA. He is now technologies, the transition to a new architecture has been con- with Advanced Micro Devices, Boxborough, MA 01719 USA (e-mail: andrew. tinually put off in favor of incremental enhancements such as [email protected]). the use of process-induced mechanical strain or, most recently, Z. Guo, T.-J. K. Liu, and B. Nikolic´ are with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA high-permittivity gate dielectrics. In part this reflects the enor- 94720 USA. mity of the investment and risk associated with the development S. Balasubramanian was with the Department of Electrical Engineering and of the design infrastructure necessary for a new device architec- Computer Sciences, University of California, Berkeley, CA 94720 USA. He is now with Globalfoundries, Sunnyvale, CA 94085 USA. ture. The ability to extend scaling SRAM at the traditional pace R. Zlatanovici was with the Department of Electrical Engineering and Com- may become a sufficient motivating factor for absorbing the in- puter Sciences, University of California, Berkeley, CA 94720 USA. He is now creased processing costs for reduced die sizes, however. This with Cadence Research Laboratories, Berkeley, CA 94704 USA. Color versions of one or more of the figures in this paper are available online transition would become attractive particularly if such a device at http://ieeexplore.ieee.org. architecture can be integrated with conventional planar CMOS Digital Object Identifier 10.1109/TVLSI.2009.2019279 devices. 1063-8210/$26.00 © 2009 IEEE Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on June 07,2010 at 18:50:09 UTC from IEEE Xplore. Restrictions apply. 888 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 6, JUNE 2010 In this work, the SRAM yield benefits associated with a new device architecture are analyzed. First, the aforementioned architecture candidates are compared, and an argument is made for FinFETs on the grounds of their scalability, ease of integration into current processes, and potential for further technological enhancements, such as independent gate control. Two possible, complementary SRAM designs exploiting in- dependent gate control are investigated in detail. It is shown that built-in feedback can be used to achieve dramatic im- provements in the cell read margin and offers a more favorable tradeoff with writeability than conventional gate work function tuning. Back-gating of the pull-up (PU) devices with a separate Fig. 1. Schematic of a conventional 6-T SRAM cell. WWL can be used to enhance writeability, allowing for simul- taneous read and write margin enhancements and further yield capacitances. It can be reduced by upsizing the PG transistors, improvements. Tradeoffs in cell read currents and architectural again at the cost of area and RSNM. In this work, the dc read constraints are also discussed. The improvements to SRAM current of the cell is used as a proxy for access time. yield which it offers make the FinFET a compelling choice for The above metrics are often quoted for a nominal cell design, a future device architecture. that is, one that does not consider parametric variations. It is also of interest to estimate the yield for these metrics. Yield is II. 6-T SRAM METRICS AND DESIGN TRADEOFFS determined not only by the nominal cell metric but also by the The yield and density of a memory array are its most impor- amount of variation in the metric, which is caused by device pa- tant properties. High yield is guaranteed for large memory ar- rameter variations in the cell. It is useful to compare amounts rays by providing sufficiently large design margins for each op- of variation between different device parameters (such as eration: reading a cell’s state without disturbing it, holding the or gate length, ) in terms of their respective standard devia- cell’s state, writing a new state into a cell, and achieving these tions (sigma), and to compute total variation vectorially. “Cell within a specified timeframe. sigma,” the yield figure of merit of the SRAM, is defined as the The read static noise margin (RSNM), measured from the minimum amount of total variation necessary to cause a failure voltage transfer characteristics [8], is typically used as a metric (RSNM or ). A higher cell sigma corresponds to for read stability. It is highly sensitive to the relative drive higher yield. strength of the pull-down (PD) and pass-gate (PG) transistors (the cell beta ratio), and it can be increased by upsizing the III. DEVICE ARCHITECTURES PD transistors, which results in an area penalty, and/or by Scaling the classical bulk-Si MOSFET structure down into increasing the gate length of the PG transistors, which increases the sub-20 nm regime presents several challenges. Suppres- the word line (WL) delay and decreases the writeability of the sion of short channel effects in bulk-Si requires heavy channel cell. doping ( cm ) or heavy super-halo implants to con- During a write operation, PG3 and PU5 form a resistive trol sub-surface leakage currents. As a result, carrier mobili- voltage divider for the falling BL and node CH (see Fig. 1). ties are severely degraded due to impurity scattering and a high If the voltage divider pulls below the trip point of the transverse electric field in the on state.
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