DOCSLIB.ORG

A Sige Bicmos LVDS Driver for Space-Borne Applications

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
A Sige Bicmos LVDS Driver for Space-Borne Applications University of Tennessee, Knoxville TRACE: Tennessee Research and Creative Exchange Masters Theses Graduate School 12-2013 A SiGe BiCMOS LVDS Driver for Space-Borne Applications Matthew Ian Laurence University of Tennessee - Knoxville, [email protected] Follow this and additional works at: https://trace.tennessee.edu/utk_gradthes Part of the Electrical and Electronics Commons, and the Electronic Devices and Semiconductor Manufacturing Commons Recommended Citation Laurence, Matthew Ian, "A SiGe BiCMOS LVDS Driver for Space-Borne Applications. " Master's Thesis, University of Tennessee, 2013. https://trace.tennessee.edu/utk_gradthes/2617 This Thesis is brought to you for free and open access by the Graduate School at TRACE: Tennessee Research and Creative Exchange. It has been accepted for inclusion in Masters Theses by an authorized administrator of TRACE: Tennessee Research and Creative Exchange. For more information, please contact [email protected]. To the Graduate Council: I am submitting herewith a thesis written by Matthew Ian Laurence entitled "A SiGe BiCMOS LVDS Driver for Space-Borne Applications." I have examined the final electronic copy of this thesis for form and content and recommend that it be accepted in partial fulfillment of the requirements for the degree of Master of Science, with a major in Electrical Engineering. Benjamin J. Blalock, Major Professor We have read this thesis and recommend its acceptance: Chuck Britton, Syed Islam Accepted for the Council: Carolyn R. Hodges Vice Provost and Dean of the Graduate School (Original signatures are on file with official studentecor r ds.) A SiGe BiCMOS LVDS Driver for Space-Borne Applications A Thesis Presented for the Master of Science Degree The University of Tennessee, Knoxville Matthew Ian Laurence December 2013 DEDICATION The following thesis is dedicated to my parents who always supported my childhood dreams of becoming a man of science. ii ACKNOWLEDGEMENTS I would first like to thank Dr. Blalock for giving me the wonderful opportunity to study integrated circuit design as a member of the ICASL group and for his role as my mentor. He has provided me with a great amount of support and knowledge throughout my studies at UT both as a professor and colleague. He is an inspiration and role model to better myself as an engineer. I would also like to thank Dr. Chuck Britton for taking the time to help in the design of my first integrated circuit and for all of the helpful knowledge he has imparted on me. In addition, I would like to thank Dr. Islam for being a member of my thesis committee and for being a truly great professor through my undergraduate and graduate studies. Finally, I would like to thank all of the members of ICASL for their support and friendship over the past two and a half years. iii ABSTRACT When designing an integrated circuit for use during an interstellar mission, certain precautions must be made. The electronics on any off-earth mission will be exposed to wide temperature swings and harmful radiation due to being outside of the Earth’s protective ionosphere. It is crucial that any data path present be immune to these detrimental effects. The introduction of galactic radiation can not only cause the onboard electronics to fail due to device degradation and single event latchup but can also lead to background radiation being coupled into the signal path as unwanted noise, degrading the signal to noise ratio. Unwanted noise can cause total failure by increasing the noise level thus decreasing the signal to noise ratio below one or by causing errors such as single event upsets. The wide temperature swing can cause device degradation and eventually failure. This issue is commonly mitigated by the introduction of an environment chamber but such an enclosure adds unnecessary mass and typically requires a large amount of current to effectively keep the electronics in an Earth-like temperature. The large current implies high power dissipation which is an unnecessary strain on the battery and can shorten the lifetime of a mission where every kilowatt-hour is crucial to success. The solution to these two non-trivial obstacles is to design an electronic circuit such that it can operate in a wide range of temperatures and can withstand the galactic radiation that it will inevitably encounter during its mission’s lifetime. The following thesis will document the design, simulation, and testing of a SiGe BiCMOS low voltage differential signal driver for space borne applications. iv TABLE OF CONTENTS CHAPTER 1: Introduction .............................................................................................. 1 1.1 Motivation ................................................................................................................. 1 1.2 Thesis Scope and Organization ................................................................................. 3 CHAPTER 2: Background............................................................................................... 5 2.1 Output Driver Technologies ..................................................................................... 5 2.1.1 Early Digital Logic ............................................................................................ 5 2.1.2 Transistor-Transistor Logic ............................................................................... 8 2.1.3 Emitter-Coupled Logic .................................................................................... 10 2.1.4 Complementary Metal-Oxide-Semiconductor ................................................. 13 2.1.5 Low Voltage Differential Signaling................................................................. 20 2.2 Radiation and Temperature Effects ........................................................................ 24 2.3 Literature Review.................................................................................................... 27 CHAPTER 3: Methodology ........................................................................................... 29 3.1 IBM 7WL PDK ....................................................................................................... 29 3.2 Circuit Design ......................................................................................................... 29 3.2.1 Basic Design .................................................................................................... 30 3.2.2 Radiation Tolerant Design ............................................................................... 35 3.2.3 Final Design ..................................................................................................... 38 3.3 Final Design Simulations ........................................................................................ 42 3.3.1 Frequency Sweep ............................................................................................. 42 3.3.2 Temperature Sweep ......................................................................................... 44 3.3.3 Voltage Sweep ................................................................................................. 46 CHAPTER 4: Results and Discussion ........................................................................... 49 4.1 Test Results ............................................................................................................. 51 4.1.1 Temperature and Frequency Sweep at 3.3 V Power Supply ........................... 51 4.1.2 Temperature and Frequency Sweep at 3.0 V Power Supply ........................... 55 4.1.3 Temperature and Frequency Sweep at 3.6 V Power Supply ........................... 60 CHAPTER 5: Conclusions and Recommendations ..................................................... 65 v LIST OF REFERENCES ............................................................................................... 67 Appendix .......................................................................................................................... 70 Vita ................................................................................................................................... 73 vi LIST OF TABLES Table 1 LVDS Parameters [6]........................................................................................... 23 vii LIST OF FIGURES Figure 1 WMAP Image [1] ................................................................................................. 2 Figure 2 RTL Inverter ......................................................................................................... 7 Figure 3 DTL OR Gate ....................................................................................................... 7 Figure 4 DTL NAND Gate ................................................................................................. 9 Figure 5 TTL NAND Gate with Totem Pole Output Stage ................................................ 9 Figure 6 Emitter-Coupled Pair .......................................................................................... 12 Figure 7 ECL OR-NOR Gate ............................................................................................ 12 Figure 8 CMOS Structure ................................................................................................. 14 Figure 9 BJT Structure ...................................................................................................... 14 Figure 10 NMOS Logic Inverter....................................................................................... 17 Figure 11 CMOS Inverter ................................................................................................
Load more

Recommended publications
  • Role of Mosfets Transconductance Parameters and Threshold Voltage in CMOS Inverter Behavior in DC Mode
    Preprints (www.preprints.org) | NOT PEER-REVIEWED | Posted: 28 July 2017 doi:10.20944/preprints201707.0084.v1 Article Role of MOSFETs Transconductance Parameters and Threshold Voltage in CMOS Inverter Behavior in DC Mode Milaim Zabeli1, Nebi Caka2, Myzafere Limani2 and Qamil Kabashi1,* 1 Department of Engineering Informatics, Faculty of Mechanical and Computer Engineering ([email protected]) 2 Department of Electronics, Faculty of Electrical and Computer Engineering ([email protected], [email protected]) * Correspondence: [email protected]; Tel.: +377-44-244-630 Abstract: The objective of this paper is to research the impact of electrical and physical parameters that characterize the complementary MOSFET transistors (NMOS and PMOS transistors) in the CMOS inverter for static mode of operation. In addition to this, the paper also aims at exploring the directives that are to be followed during the design phase of the CMOS inverters that enable designers to design the CMOS inverters with the best possible performance, depending on operation conditions. The CMOS inverter designed with the best possible features also enables the designing of the CMOS logic circuits with the best possible performance, according to the operation conditions and designers’ requirements. Keywords: CMOS inverter; NMOS transistor; PMOS transistor; voltage transfer characteristic (VTC), threshold voltage; voltage critical value; noise margins; NMOS transconductance parameter; PMOS transconductance parameter 1. Introduction CMOS logic circuits represent the family of logic circuits which are the most popular technology for the implementation of digital circuits, or digital systems. The small dimensions, low power of dissipation and ease of fabrication enable extremely high levels of integration (or circuits packing densities) in digital systems [1-5].
    [Show full text]
  • Logic Styles with Mosfets
    Logic Styles with MOSFETs NMOS Logic One way of using MOSFET transistors to produce logic circuits uses only n-type (n-p-n) transistors, and this style is called NMOS logic (N for n-type transistors). An inverter circuit in NMOS is shown in the figure with n-p-n transistors replacing both the switch and the resistor of the inverter circuit examined earlier. The lower transistor in the circuit operates as a switch exactly as the idealised switch in the original circuit: with 5V on the Gate input, the conducting channel is created in the transistor and the “switch” is closed; with 0V on the Gate there is no channel and the transistor is non-conducting - the “switch” is open. The depletion mode transistor is produced by adding a small amount of donor material to the The upper transistor, called a depletion mode channel region of a n-p-n transistor, so that there are a small number of free electrons in the channel transistor, operates as a resistor to limit current even when there is no electric field across the flow when the “switch” is closed. This transistor is insulator. This provides a connection through the a modified n-p-n transistor that always has a transistor for all Gate voltages. The conductivity of channel present and is always conducting, although the channel is lowest (Resistance is highest) when the conductivity is low when there is 0V on the the Gate is at 0V. When the Gate is at 5V and more Gate and higher when 5V is on the Gate: see Box.
    [Show full text]
  • Lecture17 08 04 2010
    EE40 Lecture 17 Josh Hug 8/04/2010 EE40 Summer 2010 Hug 1 Logistics • HW8 will be due Friday • Mini-midterm 3 next Wednesday – 80/160 points will be a take-home set of design problems which will utilize techniques we’ve covered in class • Handed out Friday • Due next Wednesday – Other 80/160 will be an in class midterm covering HW7 and HW8 • Final will include Friday and Monday lecture, Midterm won’t – Design problems will provide practice EE40 Summer 2010 Hug 2 Project 2 • Booster lab actually due next week – For Booster lab, ignore circuit simulation, though it may be instructive to try the Falstad simulator • Project 2 due next Wednesday – Presentation details to come [won’t be mandatory, but we will ask everyone about their circuits at some point] EE40 Summer 2010 Hug 3 Project 2 • For those of you who want to demo Project 2, we’ll be doing demos in lab on Wednesday at some point – Will schedule via online survey EE40 Summer 2010 Hug 4 CMOS/NMOS Design Correction • (Sent by email) • My on-the-fly explanation was correct, but not the most efficient way – If your FET circuit is implementing a logic function with a bar over it, i.e. • 푍 = 퐴 + 퐵퐶 + 퐷 + 퐸퐹 퐺 + 퐻 – Then don’t put an inverter at the output, it just makes things harder and less efficient • Sorry, on-the-fly-explanations can be dicey EE40 Summer 2010 Hug 5 CMOS • CMOS Summary: – No need for a pull-up or pull-down resistor • Though you can avoid this even with purely NMOS logic (see HW7) – Greatly reduced static power dissipation vs.
    [Show full text]
  • Understanding and Interpreting Standard-Logic Data Sheets
    Application Report SZZA036B - May 2003 Understanding and Interpreting Standard-Logic Data Sheets Stephen M. Nolan and Jose M. Soltero Standard Linear & Logic ABSTRACT Texas Instruments (TI) standard-logic products data sheets include descriptions of functionality and electrical specifications for the devices. Each specification includes acronyms, numerical limits, and test conditions that may be foreign to the user. The proper understanding and interpretation of the direct, and sometimes implied, meanings of these specifications is essential to correct product selection and associated circuit design. This application report explains each data-sheet parameter in detail, how it affects the device, and, more important, how it impacts the application. This will enable component and system-design engineers to derive the maximum benefit from TI logic devices. Contents Introduction . 6 Top-Level Look at the TI Logic Data Sheet. 6 Summary Device Description. 7 Absolute Maximum Ratings. 9 Recommended Operating Conditions. 9 Electrical Characteristics. 10 Live-Insertion Specifications. 11 Timing Requirements . 12 Switching Characteristics. 12 Noise Characteristics . 13 Operating Characteristics. 14 Parameter Measurement Information. 14 Dissecting the TI Logic Data Sheet. 16 Summary Device Description. 16 Title, Literature Number, and Dates of Origination and Revision. 16 Features Bullets . 22 Package Options and Pinouts. 23 Description . 23 BGA Packaging Top-View Illustrations and Pin-Assignments Table. 23 Ordering Information. 23 Function Table . 24 Logic Diagram . 26 Product Development Stage Note. 27 Absolute Maximum Ratings. 27 Supply Voltage, VCC . 27 Trademarks are the property of their respective owners. 1 SZZA036B Input Voltage, VI . 27 Output Voltage, VO . 28 Voltage Range Applied to Any Output in the High-Impedance or Power-Off State, VO .
    [Show full text]
  • MOSFET - Wikipedia, the Free Encyclopedia
    MOSFET - Wikipedia, the free encyclopedia http://en.wikipedia.org/wiki/MOSFET MOSFET From Wikipedia, the free encyclopedia The metal-oxide-semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET), is by far the most common field-effect transistor in both digital and analog circuits. The MOSFET is composed of a channel of n-type or p-type semiconductor material (see article on semiconductor devices), and is accordingly called an NMOSFET or a PMOSFET (also commonly nMOSFET, pMOSFET, NMOS FET, PMOS FET, nMOS FET, pMOS FET). The 'metal' in the name (for transistors upto the 65 nanometer technology node) is an anachronism from early chips in which the gates were metal; They use polysilicon gates. IGFET is a related, more general term meaning insulated-gate field-effect transistor, and is almost synonymous with "MOSFET", though it can refer to FETs with a gate insulator that is not oxide. Some prefer to use "IGFET" when referring to devices with polysilicon gates, but most still call them MOSFETs. With the new generation of high-k technology that Intel and IBM have announced [1] (http://www.intel.com/technology/silicon/45nm_technology.htm) , metal gates in conjunction with the a high-k dielectric material replacing the silicon dioxide are making a comeback replacing the polysilicon. Usually the semiconductor of choice is silicon, but some chip manufacturers, most notably IBM, have begun to use a mixture of silicon and germanium (SiGe) in MOSFET channels. Unfortunately, many semiconductors with better electrical properties than silicon, such as gallium arsenide, do not form good gate oxides and thus are not suitable for MOSFETs.
    [Show full text]
  • A Vertical Resonant Tunneling Transistor for Application in Digital Logic Circuits
    1028 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 6, JUNE 2001 A Vertical Resonant Tunneling Transistor for Application in Digital Logic Circuits Jürgen Stock, Jörg Malindretos, Klaus Michael Indlekofer, Michael Pöttgens, Arno Förster, and Hans Lüth Abstract—A vertical resonant tunneling transistor (VRTT) has In this paper, we report on the fabrication of a vertical res- been developed, its properties and its application in digital logic onant tunneling transistor (VRTT) with low peak voltage and circuits based on the monostable-bistable transition logic element good peak current control by means of a Schottky gate. The (MOBILE) principle are described. The device consists of a small mesa resonant tunneling diode (RTD) in the GaAs/AlAs material asymmetric behavior of the current-voltage ( ) character- system surrounded by a Schottky gate. We obtain low peak voltages istics is analyzed and the transistors are characterized with re- using InGaAs in the quantum well and the devices show an excel- spect to their peak voltage, peak-to-valley ratio (PVR), peak cur- lent peak current control by means of an applied gate voltage. A rent density, and gate function. We demonstrate the switching self latching inverter circuit has been fabricated using two VRTTs functionality of a self latching inverter circuit consisting of two and the switching functionality was demonstrated at low frequen- cies. VRTTs. Index Terms—Monostable-bistable transition logic element (MOBILE), monostable-to-bistable transition, resonant tunneling II. DEVICE FABRICATION diode (RTD), resonant tunneling transistor. A. Layer Structure The epitaxial structure used to fabricate the VRTT device was I. INTRODUCTION grown by molecular beam epitaxy (MBE) on semi-insulating N recent years, several new memory and logic circuits based (100)-orientated GaAs substrate.
    [Show full text]
  • SRAM Read/Write Margin Enhancements Using Finfets
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 6, JUNE 2010 887 SRAM Read/Write Margin Enhancements Using FinFETs Andrew Carlson, Member, IEEE, Zheng Guo, Student Member, IEEE, Sriram Balasubramanian, Member, IEEE, Radu Zlatanovici, Member, IEEE, Tsu-Jae King Liu, Fellow, IEEE, and Borivoje Nikolic´, Senior Member, IEEE Abstract—Process-induced variations and sub-threshold [1]. Accurate control is essential for high read stability. Sim- leakage in bulk-Si technology limit the scaling of SRAM into ilarly, variability and device leakage affect the writeability of the sub-32 nm nodes. New device architectures are being considered cell. To maintain both desired writeability and read stability of to improve control and reduce short channel effects. Among the SRAM arrays, several radical departures from the conven- the likely candidates, FinFETs are the most attractive option be- cause of their good scalability and possibilities for further SRAM tional design have been considered as follows. performance and yield enhancement through independent gating. 1) Scaling of the traditional six-transistor (6-T) SRAM cell The enhancements to read/write margins and yield are investi- at a slower pace, since a transistor with a larger area is gated in detail for two cell designs employing independently gated more immune to variations. This is a common approach FinFETs. It is shown that FinFET-based 6-T SRAM cells designed in 65- and 45-nm technology nodes; while it still might with pass-gate feedback (PGFB) achieve significant improvements in the cell read stability without area penalty. The write-ability of be applicable to small arrays in future, it fundamentally the cell can be improved through the use of pull-up write gating undermines the objective of technology scaling.
    [Show full text]
  • Diode Logic). • Explain the Need for Introducing Transistors in the Output (DTL and TTL
    Lecture 02: Logic Families R.J. Harris & D.G. Bailey Objectives • Show how diodes can be used to form logic gates (Diode logic). • Explain the need for introducing transistors in the output (DTL and TTL). • Explain why Schottky transistors improve the speed of gates. • Describe the operating principles of CMOS logic gates. • Explain the definitions of noise margin, fanout, propagation delay, rise and fall time. Semester 2 - 2006 Digital Electronics Slide 2 Review of Previous Lecture • You can now: – Describe the important differences between analogue and digital signals. – Show how to represent more than two levels using digital signals. – Manipulate different codes for representing numbers and letters: • natural binary, signed binary, twos complement, offset binary, Gray codes, ASCII characters. – Show how to convert between binary and base 10. – Write down the logic symbols for • AND, OR, NOT, NAND and NOR gates. – Draw up a truth table to represent relationships between inputs and outputs of a logic circuit. Semester 2 - 2006 Digital Electronics Slide 3 Presentation Outline • Diode Transistor Logic • TTL • Schottky TTL • CMOS • Tristate logic outputs • Definitions: – Noise margin, fanout – Timing: rise and fall times, propagation delay – Power dissipation • Power supply decoupling Semester 2 - 2006 Digital Electronics Slide 4 Diode Logic – AND Gate • Recall that a diode behaves like a switch. – When the diode is forward biased, the switch is closed, allowing a current to flow through it. When reverse biased, it is like a switch that is turned off - no current flows. • First we shall look at an AND gate. – If either input A or input B goes low, it will forward bias the corresponding diode.
    [Show full text]
  • Vlsi Design Lecture Notes B.Tech (Iv Year – I Sem) (2018-19)
    VLSI DESIGN LECTURE NOTES B.TECH (IV YEAR – I SEM) (2018-19) Prepared by Dr. V.M. Senthilkumar, Professor/ECE & Ms.M.Anusha, AP/ECE Department of Electronics and Communication Engineering MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY (Autonomous Institution – UGC, Govt. of India) Recognized under 2(f) and 12 (B) of UGC ACT 1956 (Affiliated to JNTUH, Hyderabad, Approved by AICTE - Accredited by NBA & NAAC – ‘A’ Grade - ISO 9001:2015 Certified) Maisammaguda, Dhulapally (Post Via. Kompally), Secunderabad – 500100, Telangana State, India Unit -1 IC Technologies, MOS & Bi CMOS Circuits Unit -1 IC Technologies, MOS & Bi CMOS Circuits UNIT-I IC Technologies Introduction Basic Electrical Properties of MOS and BiCMOS Circuits MOS I - V relationships DS DS PMOS MOS transistor Threshold Voltage - VT figure of NMOS merit-ω0 Transconductance-g , g ; CMOS m ds Pass transistor & NMOS Inverter, Various BiCMOS pull ups, CMOS Inverter Technologies analysis and design Bi-CMOS Inverters Unit -1 IC Technologies, MOS & Bi CMOS Circuits INTRODUCTION TO IC TECHNOLOGY The development of electronics endless with invention of vaccum tubes and associated electronic circuits. This activity termed as vaccum tube electronics, afterward the evolution of solid state devices and consequent development of integrated circuits are responsible for the present status of communication, computing and instrumentation. • The first vaccum tube diode was invented by john ambrase Fleming in 1904. • The vaccum triode was invented by lee de forest in 1906. Early developments of the Integrated Circuit (IC) go back to 1949. German engineer Werner Jacobi filed a patent for an IC like semiconductor amplifying device showing five transistors on a common substrate in a 2-stage amplifier arrangement.
    [Show full text]
  • Design and Implementation of 4 Bit Carry Skip Adder Using Nmos and Pmos Transmission Gate
    EasyChair Preprint № 2561 Design and Implementation of 4 Bit Carry Skip Adder Using Nmos and Pmos Transmission Gate Ashutosh Pandey, Harshit Singh, Vivek Kumar Chaubey and Utkarsh Jaiswal EasyChair preprints are intended for rapid dissemination of research results and are integrated with the rest of EasyChair. February 5, 2020 CHAPTER-1 INTRODUCTION In the field of electronics, a digital circuit that performs addition of numbers is called an adder or summer. In various kinds of processors like computers, adders have many applications in the arithmetic logic units, as well as in other parts, where these are used to compute table indices, addresses and similar operations. Mostly, the common adders operate on binary numbers, but they can also be constructed for many other numerical representations, such as excess-3 or binary coded decimal (BCD). It is insignificant to customize the adder into an adder-subtractor unit in situations where negative numbers are represented by one's or two's complement. The usage of power efficient VLSI circuits is required to satiate the perennial need for mobile electronic devices. The calculations in these devices ought to be performed using area efficient and low power circuits working at higher speed. The most elementary arithmetic operation is addition; and the most basic arithmetic component of the processor is the adder. Depending upon the delay, area and power consumption requirements; certain adder implementations such as ripple carry, carry-skip, carry select and carry look ahead are available. When large bit numbers are used, the ripple carry adder (RCA) is not very efficient. With the bit length, there is a linear increase in delay.
    [Show full text]
  • Digital Logic and Design (Course Code: EE222) Ltlecture 6: Lliogic Famili Es
    Indian Institute of Technology Jodhpur, Year 2018‐2019 Digital Logic and Design (Course Code: EE222) LtLecture 6: LiLogic Fam ilies Course Instructor: Shree Prakash Tiwari EilEmail: sptiwari@iitj .ac.i n Webpage: http://home.iitj.ac.in/~sptiwari/ Course related documents will be uploaded on http://home.iitj.ac.in/~sptiwari/DLD/ Note: The information provided in the slides are taken form text books Digital Electronics (including Mano & Ciletti), and various other resources from internet, for teaching/academic use only 1 Overview •Early families (DL, RTL) • TTL •Evolution of TTL family • CMOS family and its evolution 2 Logic families Diode Logic (DL) •simpp;lest; does not scale •NOT not possible (need = an active element) Resistor-Transistor Logic (RTL) • replace diode switch with a tittransistor switc h •can be cascaded = • large power draw 3 Logic families Diode-Transistor Logic (DTL) • essentially diode logic with transistor amplification • reduced power consumption •faster than RTL = DL AND gate Saturating inverter 4 Logic Families • The bipolar transistor as a logical switch TTL Bipolar Transistor-Transistor Logic (TTL) •First introduced by in 1964 (Texas Instruments) •TTL has shaped digital technology in many ways • Standard TTL family (e.g. 7400) is obsolete •Newer TTL families used (e.g. 74ALS00) 6 TTL Bipolar Transistor-Transistor Logic (TTL) Distinct features •Multi‐emitter transistors 7 TTL A Standard TTL NAND gate 8 TTL A standard TTL NAND gate with open collector output 9 TTL evolution Schottky series (74LS00) TTL •A major
    [Show full text]
  • High Performance Ripple Carry Adder Using Domino
    International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056 Volume: 02 Issue: 08 | Nov-2015 www.irjet.net p-ISSN: 2395-0072 HIGH PERFORMANCE RIPPLE CARRY ADDER USING DOMINO LOGIC Dr.J.Karpagam1 , A.Arunadevi2 1 Professor, Department of ECE, KPRIET, Coimbatore, Tamilnadu, India 2 PG Scholar, Department of ECE, KPRIET, Coimbatore, Tamilnadu, India ---------------------------------------------------------------------***--------------------------------------------------------------------- ABSTRACT excessively with a mixer of dynamic and static circuit styles, use of dual supply voltages and dual threshold The demand and popularity of portable electronics is voltages. driving designers to strive for small silicon area, higher speeds, low power dissipation and reliability. Domino logic Domino logic is a clocked logic family which means that circuits are important as it provides better speed and has every single logic gate has a clock signal present. When the lesser transistor requirement when compared to static clock signal turns low, node N0 goes high, causing the CMOS logic circuits. This project presents the design and output of the gate to go low. This represents the only performance of 8-bit Ripple Carry Adder using CMOS mechanism for the gate output to go low once it has been Domino logic targeting at full-custom high speed driven high. The operating period of the cell when its input applications. The constant delay characteristic of this logic clock and output are low is called the recharge phase or style regardless of the logic expression makes it suitable for cycle. The next phase, when the clock is high, is called the implementing complicated logic expression such as addition. evaluate phase or cycle.
    [Show full text]