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(12) United States Patent (1O) Patent No.: US 7,489,538 B2 Mari Et Al

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(12) United States Patent (1O) Patent No.: US 7,489,538 B2 Mari Et Al mu uuuu ui iiui iiui mu mil uui uui lull uui uuii uu uii mi (12) United States Patent (1o) Patent No.: US 7,489,538 B2 Mari et al. (45) Date of Patent: Feb. 10, 2009 (54) RADIATION TOLERANT COMBINATIONAL 5,406,513 A * 4/1995 Canafis et al . .............. 365/181 LOGIC CELL (Continued) (75) Inventors: Gary R. Maki, Post Falls, ID (US); OTHER PUBLICATIONS Jody W. Gambles, Post Falls, ID (US); Sterling Whitaker, Albuquerque, NM "Ionizing Radiation Effects in MOS Devices and Circuits", Edited by (US) T.P. Ma., Department of Electrical Engineering, Yale University, New Haven Connecticut and Paul V. Dressendorfer, Sandia National (73) Assignee: University of Idaho, Moscow, ID (US) Laboratories, Albuquerque, NM, A Wiley-Interscience Publication, John Wiley & Sons, pp. 484-589. (*) Notice: Subject to any disclaimer, the term of this (Continued) patent is extended or adjusted under 35 U.S.C. 154(b) by 263 days. Primary Examiner Vu A Le (74) Attorney, Agent, or Firm Haverstock & Owens LLP (21) Appl. No.: 11/527,375 (57) ABSTRACT (22) Filed: Sep. 25, 2006 A system has a reduced sensitivity to Single Event Upset (65) Prior Publication Data and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system US 2007/0109865 Al May 17, 2007 includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The Related U.S. Application Data logic block is for implementing a logic function, receiving a (60) Provisional application No. 60/736,979, filed on Nov. data set via the input, and generating a result f by applying the 14, 2005. data set to the logic function. The bias stage is coupled to the logic block. The bias stage is for receiving the result from the (51) Int. Cl. logic block and presenting it to the state machine. The state G11C 7/00 (2006.01) machine is coupled to the bias stage. The state machine is for (52) U.S. Cl . .................................. 365/154; 365/189.05 receiving, via the bias stage, the result generated by the logic (58) Field of Classification Search ................. 365/154, block. The state machine is configured to retain a state value 365/189.05; 327/200, 208 for the system. The state value is typically based on the result See application file for complete search history. generated by the logic block. The output is coupled to the state machine. The output is for providing the value stored by the (56) References Cited state machine. Some embodiments of the invention produce U.S. PATENT DOCUMENTS dual rail outputs Q and Q. The logic block typically contains combinational logic and is similar, in size and transistor con- 4,454,589 A 6/1984 Miller ........................ 364/716 figuration, to a conventional CMOS combinational logic 4,783,778 A 11/1988 Finch et al . ................... 370/60 design. However, only a very small portion of the circuits of 4,787,057 A 11/1988 Hammond .................. 364/754 these embodiments, is sensitive to Single Event Upset and/or 4,888,774 A 12/1989 Kosuge et al . ............. 371/38.1 Single Event Transients. 5,111,429 A 5/1992 Whitaker .................... 365/156 5,278,781 A 1/1994 Aono et al . ................. 364/736 5,398,322 A 3/1995 Marwood ................... 395/400 32 Claims, 9 Drawing Sheets /200 Vdd Vdd ^-260 t2262 264 284 Y2 Q' 242 244 ``-240 V,. Vss f f' Logic Block h-220 Primary-202 Inputs US 7,489,538 B2 Page 2 U.S. PATENT DOCUMENTS 7,162,684 132 1/2007 Hocevar ..................... 714/800 5,673,407 A 9/1997 Poland et al . ............... 395/375 OTHER PUBLICATIONS 5,867,414 A 2/1999 Kao ...................... 364/754.02 "Test Results for SELF and SEL Immune Memory Circuits", D. Wise- 6,326,809 B1 12/2001 Gambles et al ................ 326/46 man et al., 5' NASA Symposium on VLSI Design 1993, Nasa Space 6,487,134 132 * 11/2002 Thoma et al . ............... 365/205 Engineering Research Center for VLSI System Design, University of 6,573,773 132 6/2003 Maki et al ................... 327/200 New Mexico, 2650 Yale Suite # 101, Albuquerque, New Mexico 6,583,470 B1 * 6/2003 Maki et al ................... 257/349 87106, pp. 2.6.1-2.6.10. 6,597,745 B1 7/2003 Dowling ..................... 375/296 "Low Power SELF Immune CMOS Memory Circuits", IEEE Trans- 6,696,873 132 2/2004 Hazucha et al .............. 327/203 actions on Nuclear Science, vol. 39, No. 6, Dec. 1992, M. Norley Liu 6,725,411 B1 4/2004 Gerlach et al . .............. 714/755 and Sterling Whitaker, NASA Space Engineering Research Center 6,757,122 B1 6/2004 Kuznetsov et al . ............ 360/53 for VLSI System Design, University of Idaho, Moscow. Idaho 83843, 6,826,090 B1 11/2004 Chu et al . .............. 365/189.05 pages. 6,826,778 132 11/2004 Bopardikar et al. ......... 725/145 IAC-02-L8.08, Radiation Effects and Hardening Techniques for 6,895,547 132 5/2005 Eleftheriou et al. ......... 714/801 Spacecraft System Microelectronics, Jody Gambles and Gary Maki, 6,928,602 132 8/2005 Yamagishi et al. .......... 714/781 Center for Advanced Microelectric & Biomolecular Research, Uni- versity of Idaho Research Park, 721 Lochsa Street, Suite #8, Post 7,069,492 132 6/2006 Piret .......................... 714/762 Falls, Idaho 83854 USA, 11 pages. 7,111,221 132 9/2006 Birru et al ................... 714/755 7,127,653 B1 10/2006 Gorshe ....................... 714/746 * cited by examiner U.S. Patent Feb. 10, 2009 Sheet 1 of 9 US 7,489,538 B2 100 160 Qo--d State Machine Q' Bias Stage ^,, 140 f If' Logic Block x-120 Primary Inputs x..102 Fig. 1 U.S. Patent Feb. 10, 2009 Sheet 2 of 9 US 7,489,538 B2 200 --------------------------------------------- 1 Vdd Vdd 1 `- 260 I I 282 262 264 284 Q IYI Y2 Q1 1 1 1 I 1 242 244 ^- 240 VS Vs I I I I I ------------------ J ------- L ----------------- r----------------- ------- ------------------^ 1 1 1 I 1 I 1 I I 1 f f' I I 1 1 Logic Block 220 I I i I ^ I I I I I 1 I 1 I L-------------------- - - - - - - - - - - - - - - - - - - - - - - - - J Primary-202 Inputs Fig. 2 U.S. Patent Feb. 10, 2009 Sheet 3 of 9 US 7,489,538 B2 300 AB CD 00 of ii io 00 o i o i 01 i o i o 11 o i 1 o i 10 1 o i o Fig. 3 U.S. Patent Feb. 10, 2009 Sheet 4 of 9 US 7,489,538 B2 420 B B A A D D D D Fig. 4 Control Inputs 520 B B A A /` D } Data D Inputs D I D Fig. 5 U.S. Patent Feb. 10, 2009 Sheet 5 of 9 US 7,489,538 B2 600 -------------------------------------------------------- Vdd Vdd Lr r^ —660 68 2 vvz ""^ 684 r 8 8 Q YI I YI A Y2 Q ----------- -------- --------- ----------- r r r - r ^r 640 r I^ 1 r 642 644 r r r r r SS SS r r r -------------------- --------------------- --------------------- ------------ --------------------- r f f' ^- 620 r r r r r r I^ IC r r r r r r r -I I Iv IV r r r r _T7 r q IQ I q Q Iq q Q IQ r L J r 602 Fig. 6 U.S. Patent Feb. 10, 2009 Sheet 6 of 9 US 7,489,538 B2 f f' goo yly2 00 01 11 10 j X00 11 1X XX X1 01 Z 1 ZX OX 01 11 ZZ ZO 00 OZ 10 1 Z 10 XO XZ Fig. 7 800 f f' yly2 00 01 11 10 00 11 1X - X1 01 Z 1 ZX - 01 11 ZZ ZO - OZ 10 1 Z 1 10 1 - XZ Fig. 8 900 f f' yly2 00 01 11 10 00 11 10 - 01 01 Z1 ZO - 01 11 ZZ ZO - OZ 10 1Z 10 - OZ Fig. 9 U.S. Patent Feb. 10, 2009 Sheet 7 of 9 US 7,489,538 B2 1000 --------------------------------------------- Vdd Vdd 1060 1063 1065 1084 1082 10621064 Q! (-'i Y1 Y2 r^)- :Q' ---------------------------------------------'- --------- - - - - - - - - --------- -------- - - - - - - - - , rte. 1040 1042 1044 Vss ss ------------------ --------- ---------------- f f' Logic Block 1020 ------------------- - ------------------- Primary Inputs 1002 Fig. 10 U.S. Patent Feb. 10, 2009 Sheet 8 of 9 US 7,489,538 B2 1100 . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Vss Vss I 1 1 ^_ 1 160 1182 1162 1164 1184 Q l y l Y2 Q^ •-------- --------- 1 I I I -^ I 1 I 1142 1144 I ;-L 1140 I 1 1 1 Vdd Vdd I I 1 I 1 1 ----------------- r ----------------------------------- --------- I 1 I i 1 I I I I 1 1 f f' 1 I Logic Block z 1120 (PMOS ONLY) I I I I I I 1 1 1 1 1 L - - - - - -------------- - - - - -------------------- Primary Inputs-`" 1102 Fig. 11 U.S. Patent Feb. 10, 2009 Sheet 9 of 9 US 7,489,538 B2 1200 Start 1205 sl IMPLEMENT LOGIC FUNCTION 1210 sI RECEIVE DATA SET 1215 sl GENERATE RESULT 1220PRESENT RESULT TO —d STATE MACHINE 1225,A STORE STATE VALUE 1230 sl PROVIDE STABLE STATE 1235 1240 STORED STATE----- DIFFERENT Yes NEXT STATE THAN STABLESTATE? No Yes CONTINUE? 1245 No END Fig. 12 US 7,489,538 B2 1 2 RADIATION TOLERANT COMBINATIONAL Further, if a high energy charged particle passes through a LOGIC CELL semiconductor diffusion region of an electronic device, such as a transistor, particularly at a susceptible node within the RELATED APPLICATIONS electronic circuit, then the particle can undesirably alter the 5 contents of data stored within the electronic circuit.
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