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Circuit and Layout Techniques for Soft-Error-Resilient Digital Cmos Circuits

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CIRCUIT AND LAYOUT TECHNIQUES FOR SOFT-ERROR-RESILIENT DIGITAL CMOS CIRCUITS A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY Hsiao-Heng Kelin Lee August 2011 © 2011 by Hsiao-Heng Kelin Lee. All Rights Reserved. Re-distributed by Stanford University under license with the author. This work is licensed under a Creative Commons Attribution- Noncommercial 3.0 United States License. http://creativecommons.org/licenses/by-nc/3.0/us/ This dissertation is online at: http://purl.stanford.edu/dn086pk6955 ii I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. Umran Inan, Primary Adviser I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. Ivan Linscott, Co-Adviser I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. Christoforos Kozyrakis Approved for the Stanford University Committee on Graduate Studies. Patricia J. Gumport, Vice Provost Graduate Education This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file in University Archives. iii Abstract Radiation-induced soft errors are a major concern for modern digital circuits, espe- cially memory elements. Unlike large Random Access Memories (RAM) that can be protected using error-correcting codes and bit interleaving, soft error protection of sequential elements, i.e. latches and flip-flops, is challenging. Traditional techniques for designing soft-error-resilient sequential elements generally address single node er- rors, or Single Event Upsets (SEU). However, with technology scaling, the charge deposited by a single particle strike can be simultaneously collected and shared by multiple circuit nodes. The likelihood that a soft error caused by multiple circuit node disruptions, or Single Event Multiple Upset (SEMU), happens, increases ex- ponentially as separation between individual transistors decreases. Hence, soft error resilience techniques for sequential elements must focus on Single Event Multiple Upsets (SEMUs). In this dissertation, we address these concerns by presenting a design framework for soft-error-resilient sequential cell design with an overview of existing circuit and layout techniques for soft error mitigation. In order to address the growing concern over SEMUs, we introduce a new soft error resilience layout design principle called LEAP, or Layout Design through Error-Aware Transistor Positioning, which targets SEMUs by using circuit interactions and transistor placement to improve the soft error performance of a circuit without significant area cost. As an example of circuit and layout co-design for soft error resilience, we discuss our application of LEAP on the SEU-immune Dual Interlocked Storage Cell (DICE) by implementing a new sequential element layout called LEAP-DICE. LEAP-DICE retains the original DICE circuit topology, but employs a layout design efficient at using transistor interactions iv to reduce SEMUs. After comparing the soft error performance of SEU-immune flip- flops with the LEAP-DICE flip-flop with a test chip in 180nm CMOS under 200{MeV proton radiation, we conclude that • Our LEAP-DICE flip-flop achieved the best soft error performance among all SEU-immune flip-flop designs we investigated. LEAP-DICE encounters on av- erage 2,000X fewer errors compared to the reference D flip-flop. • Our LEAP-DICE flip-flop encounters 5X fewer errors compared to the DICE flip-flop, while both designs share identical circuit topology and transistor siz- ing. LEAP-DICE imposes negligible power and delay costs and 40% area cost compared to the DICE design. • In the evaluation of our design framework, we also discovered new soft error effects related to operating conditions such as voltage scaling, clock frequency setting and radiation dose. v Acknowledgement Throughout my graduate studies at Stanford, I have had the privilege of working with exceptional people, teachers and students alike. Although I am closing this chapter of my life and moving forward, I will always cherish the good times we had together. First, I would like to first thank my advisors, Prof. Umran Inan and Dr. Ivan Lin- scott, for offering me the unique opportunity of working on an independent research project, for giving me the freedom to explore various research ideas, for providing the support to continue my studies, and for always believing in me. I have not been the easiest student to mentor, but you have always been patient with me. T esekkur¨ ederim. I would also like to thank Prof. Christos Kozyrakis for chairing my oral defense committee and serving as the third reader for this dissertation. I am heavily indebted to Prof. Subhasish Mitra, who acted as a mentor and supporter for my work in soft errors, and who introduced me to the art of writing papers. Prof. Mitra was instrumental in helping me complete this work. Without Prof. Mitra, I would still be languishing in the abyss of graduate school (figuratively and literally speaking, given that I worked in the basement of the electrical engineering building for many unspeakable years). I would like to thank the various people who have given me technical guidance and support in the field of soft errors, notably Dr. Klas Lilja and Mounaim Bounasser of Robust Chip, and Norbert Seifert and Min Zhang of Intel. This work was heavily sponsored by Robust Chip and inspired by Dr. Lilja's vision of using layout as a design dimension for soft-error-resilient circuit design. I cannot forget the essential support of the administrative staff: Shaolan Min, vi Helen Niu, and Uma Mulukutla, who always made sure that students have sufficient funding support, and enough to get by from day to day. For two years, I had the chance to take part on the WIPER project, where I worked with Dr. Jack Doolittle, Robert Bumala and Clem Tillier from Lockheed Martin, and Dr. Dave Lauben from Stanford. Their collaboration was instrumental in contributing to my understanding of how to design satellite instrument. I also would thank Dr. Bennett Wilburn and Prof. Mark Horowitz for the op- portunity to be part of the Light Field Camera project during my first two years at Stanford. This experience gave me a peek at doing top notch independent research at Stanford. I am blessed to have a chance to work with exceptional peers at Stanford, namely Dr. Charles Wang and Dr. Benjamin Mossawir, former students of the Stanford VLF Group, who supported me at critical times in test chip tapeout, and offered helpful suggestions for radiation hardening ideas and radiation testing setup. I would also like to thank Prasanthi Relangi, Rakesh Gnana David Jeyasingh and Jumie Yuventi for helping me on my radiation experiments at New Mexico and Indiana. I would also thank other members of the VLF Group: Jeff Chang (whose board testing support was critical), Carsten Barth (whose late night company I enjoyed), former occupants of my Packard 037 basement office (including Dr. Robert Moore, Dr. Joe Payne, Dr. Ryan Said and Dr. Ben Cotts), and other fellow current and former members of the Stanford VLF Group and Stanford Robust Systems Group. Finally, I would like to thank my family, my father Eric, my mother Grace, and my brother Ben. No words can express the love and gratitude I feel for my family. At times I have almost given up, and without their support, I would not have had the courage and determination to find myself again. HSIAO-HENG \KELIN" LEE Stanford, California August 26, 2011 vii This work was sponsored by the following contracts and agencies: • NASA New Technology Initiatives Program, Grant No. NAG5-10822. • The Aerospace Corporation Subcontract No. 46000001624-9. • Air Force Research Laboratory, Contract No. AFRL FA8718-05-C0027. • Defense Threat Reduction Agency/Robust Chip Inc., Contract No. HDTRA1- 09-P0011. • National Science Foundation. This research was also made possible with generous fabrication support from National Semiconductor Corporation, as well as radiation testing support from Los Alamos National Laboratory and Indiana University Cyclotron Facility. viii Contents Abstract iv Acknowledgement vi 1 Introduction 1 1.1 A Brief Overview of Soft Errors . 2 1.2 Purpose . 3 1.3 Contributions . 4 1.4 Organization . 4 2 Radiation Effects in Electronics 6 2.1 Single-Event Effects . 6 2.1.1 Soft Errors . 8 2.1.2 Hard Errors . 8 2.2 Sources of Radiation . 9 2.2.1 Near-Earth Radiation Environment . 9 2.2.2 Terrestrial Radiation Environment . 10 2.3 Total Dose Effects . 15 2.4 Conclusion . 15 3 Circuit Soft Error Resilience Techniques 17 3.1 Soft Error Generation . 18 3.2 RC-Based Soft Error Resilience Techniques . 21 3.3 Triple Modular Redundancy . 25 ix 3.4 Dual Modular Redundancy . 27 3.4.1 C-Element Based Soft-Error-Resilient Latches . 27 3.4.2 Dual Interlocked Storage Cell (DICE) . 33 3.4.3 Differential Cascode Voltage Switch Logic (DCVSL) . 34 3.5 SEMU Vulnerability in SEU-Immune Techniques . 35 3.6 Conclusion . 38 4 Layout Soft Error Resilience Techniques 39 4.1 Charge Collection in CMOS Circuits . 40 4.2 Traditional Layout Techniques for Charge Collection Mitigation . 44 4.2.1 Guard Rings, Guard Contacts and Guard Drains . 45 4.2.2 Node Separation . 50 4.3 Layout Design through Error-Aware Transistor Positioning (LEAP) . 52 4.4 LEAP-DICE: A Case Study . 59 4.5 Conclusion .
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