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  • IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 3, SEPTEMBER 2005
  • 305

Radiation-Induced Soft Errors in Advanced
Semiconductor Technologies

Robert C. Baumann, Fellow, IEEE

Invited Paper

Abstract—The once-ephemeral radiation-induced soft error has bit upset (SBU). While MBUs are usually a small fraction of become a key threat to advanced commercial electronic compo- nents and systems. Left unchallenged, soft errors have the poten- tial for inducing the highest failure rate of all other reliability mechanisms combined. This article briefly reviews the types of failure modes for soft errors, the three dominant radiation mech-

the total observed SEU rate, their occurrence has implications for memory architecture in systems utilizing error correction [3], [4]. Another type of soft error occurs when the bit that is flipped is in a critical system control register such as that

anisms responsible for creating soft errors in terrestrial applica- found in field-programmable gate arrays (FPGAs) or dynamic tions, and how these soft errors are generated by the collection of radiation-induced charge. The soft error sensitivity as a function of technology scaling for various memory and logic components is then presented with a consideration of which applications are most likely to require soft error mitigation.

random access memory (DRAM) control circuitry, so that the error causes the product to malfunction [5]. This type of soft error, called a single event interrupt (SEFI), obviously impacts the product reliability since each SEFI leads to a direct product malfunction as opposed to typical memory soft errors that may or may not effect the final product operation depending on the algorithm, data sensitivity, etc. Radiation events occurring in combinational logic result in the generation of single event transients (SET) that, if propagated and latched into a memory element, will lead to a soft error [6]. The last mode in which an SEE can cause disruption of electrical systems is by turning on the complimentary metal–oxide–semiconductor (CMOS) parasitic bipolar transistors between well and substrate—inducing a latch-up [7], [8]. The only difference between single event latch-up (SEL) and electrical latch-up is that the current injection that turns on the parasitic bipolar elements is provided by the radiation instead of an electrical overvoltage. SEL can also be debilitating since its occurrence will necessitate a full chip power down to remove the condition, and in some cases can cause permanent damage.

Index Terms—Radiation effects, reliability, single-event effects,

soft errors.

I. INTRODUCTION

S the dimensions and operating voltages of computer electronics are reduced to satisfy the consumer’s in-

A

satiable demand for higher density, functionality, and lower power, their sensitivity to radiation increases dramatically. There are a plethora of radiation effects in semiconductor devices that vary in magnitude from data disruptions to permanent damage ranging from parametric shifts to complete device failure [1], [2]. Of primary concern for commercial terrestrial applications are the “soft” single-event effects (SEEs) as opposed to the “hard” SEEs and dose/dose-rate related radiation effects that are predominant in space and military environments. As the name implies, SEEs are device failures induced by a single radiation event. The author uses the term soft error throughout the text to encompass the key SEE that affects commercial semiconductor technologies. But it is useful to be aware of the different failure modes.

II. THE TERRESTRIAL RADIATION ENVIRONMENT

A. What   Radiation Does in Silicon

The terrestrial environment is dominated by three different mechanisms (described in the next section) that generate (either directly or as secondary reaction products) energetic ions that are responsible for inducing soft errors. The magnitude of the disturbance an ion causes depends on the linear energy transfer (LET) of that ion (typically reported in units of megaelectron volt square centimeter per milligram). In a silicon substrate, one electron hole pair is produced for every 3.6 eV of energy lost by the ion. With a simple conversion, the LET can be plotted in more convenient units of charge loss per distance as illustrated in Fig. 1. The LET is dependent on the mass and energy of the particle and the material in which it is traveling. Typically, more massive and energetic particles in denser materials have the highest LET. Note that the LET of a magnesium ion (one
A soft error occurs when a radiation event causes enough of a charge disturbance to reverse or flip the data state of a memory cell, register, latch, or flip-flop. The error is “soft” because the circuit/device itself is not permanently damaged by the radiation—if new data are written to the bit, the device will store it correctly. The soft error is also often referred to as a single event upset (SEU). If the radiation event is of a very high energy, more than a single bit maybe affected, creating a multibit upset (MBU) as opposed to the more likely single

Manuscript received February 14, 2005; revised April 6, 2005. The author is with Texas Instruments, Dallas, TX 75243 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/TDMR.2005.853449

1530-4388/$20.00 © 2005 IEEE

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of charge collected and the size and location of voltage/current glitches in the circuit.
The magnitude of Qcoll depends on a complex combination of factors including the size of the device, biasing of the various circuit nodes, substrate structure, device doping, the type of ion, its energy, its trajectory, the initial position of the event within the device, and the state of the device. However, Qcoll is only half the story, as the device’s sensitivity to this excess charge needs to be taken into account. This sensitivity is defined primarily by the node capacitance, operating voltage, and the strength of feedback transistors, all defining the amount of charge or critical charge (Qcrit) required to trigger a change in the data state. The response of the device to the charge injection is dynamic and dependent on the magnitude and the temporal characteristics of the pulse, and thus Qcrit is not

Fig. 1. LET converted into charge generation per linear distance for some ions in silicon (generated with IBM’s SRIM 2000) [9].

constant but depends on the radiation pulse characteristics and the dynamic response of the circuit itself, making the effect of the ions commonly produced when a high-energy neutron extremely difficult to model [11]. For simple isolated junctions reacts with a silicon nucleus) is significantly higher than that of (like DRAM cells in storage mode), a soft error will be induced alpha particles (helium ion emitted from radioactive impurities when a radiation event occurs close enough to a sensitive node in materials) or lithium ions (emitted from the reaction of low- such that Qcoll > Qcrit. Conversely, if the event results in a energy neutrons and 10Boron). Charge collection generally Qcoll < Qcrit, then the circuit will survive the event and no soft occurs within a few microns of the junction, thus the collected error will occur. In SRAM or other logic circuits where there is charge (Qcoll) for these events is from 1 to several 100 fC active feedback, there is an additional term to comprehend the depending on the type of ion, its trajectory, and its energy over speed with which the circuit can react—slower speeds allow the path through or near the junction.
The reverse-biased junction is the most charge-sensitive part value and thereby reduce the probability of a soft error. This of circuits, particularly if the junction is floating or weakly additional term tends to increase the effective Qcrit driven (with only a small drive transistor or high resistance load The rate at which soft errors occur is called the soft error rate more time for the feedback circuit to restore the corrupted node
.sourcing the current required to keep the node in its state). As (SER). The unit of measure commonly used with SER and other shown in Fig. 2, at the onset of an ionizing radiation event, hard reliability mechanisms is the failure in time (FIT). One FIT a cylindrical track of electron hole pairs with a submicron is equivalent to one failure in 109 device hours. Soft errors have radius and a very high carrier concentration is formed in the become a huge concern in advanced computer chips because, wake of the energetic ion’s passage (a). When the resultant uncorrected, they produce a failure rate that is higher than ionization track traverses or comes close to the depletion region, all the other reliability mechanisms combined! For example, carriers are rapidly collected by the electric field creating a a typical failure rate for a “hard” reliability mechanism (such large current/voltage transient at that node. A notable feature as gate oxide breakdown, metal electromigration, etc.) is about of the event is the concurrent distortion of the potential into a 1–50 FIT. There are a half-dozen critical reliability mechanisms funnel shape [10]. This funnel greatly enhances the efficiency degrading integrated circuit performance, but in general the of the drift collection by extending the high field depletion aggregate failure rate is typically in the 50–200 FIT range. In region deeper into the substrate (b). The size of the funnel is a stark contrast, without mitigation, the SER can easily exceed function of substrate doping—the funnel distortion increasing 50 000 FIT/chip! for decreased substrate doping. This “prompt” collection phase is completed within a nanosecond and followed by a phase where diffusion begins to dominate the collection process (c).

B. Alpha   Particles

  • Additional charge is collected as electrons diffuse into the de-
  • In the late 1970s, alpha particles emitted by trace uranium

pletion region on a longer time scale (hundreds of nanoseconds) and thorium impurities in packaging materials were shown until all excess carriers have been collected, recombined, or to be the dominant cause of soft errors in DRAM devices diffused away from the junction area. The corresponding cur- [12]. The alpha particle is composed of two neutrons and rent pulse resulting from these three phases is also shown in two protons—a doubly ionized helium atom emitted from the Fig. 2. In general, the farther away from the junction that the nuclear decay of unstable isotopes. The most common source event occurs, the smaller the amount of charge that will be of alpha particles are from the naturally occurring 238U, 235U, collected and the less likely it is that the event will cause a soft and 232Th. These impurities emit alpha particles at specific error. In actual circuits, a node is never isolated but is actually discrete energies over a range from 4 to 9 MeV. When an alpha part of a complex “sea of nodes” in close proximity to one particle travels through a material, it loses its kinetic energy another; thus, charge sharing among nodes and parasitic bipolar predominantly through interactions with the electrons of that action (the formation of an unintentional bipolar transistor material and thus leaves a trail of ionization in its wake. The between junctions and wells) can greatly influence the amount higher the energy of the alpha particle, the farther it travels

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Fig. 2. Charge generation and collection phases in a reverse-biased junction and the resultant current pulse caused by the passage of a high-energy ion.

nium and thorium impurities is a necessary requirement for low alpha emission but not sufficient. In nonequilibrium situations, higher activity daughters may be present that greatly increase the alpha emission rate. This situation was highlighted during investigations into eutectic lead solders (for flip-chip bumps) in which all radioactive impurities had been eliminated except the radioactive 210Pb that was chemically inseparable from the 206 208Pb. Since 210Pb does not emit an alpha particle when it decays, initial alpha counting measurements revealed the solder to be emitting alpha particles at extremely low levels. With the relatively short half-life of 210Pb, a regrowth of the alpha emitter 212Po (from the decay of 210Pb ⇒ 210Bi ⇒ 210Po) occurred and within a few months the solder alpha emission was 10× higher than initial measurements indicated.
There are two fundamental approaches to reducing the SER from alpha particles in ICs: purification of all production materials in close proximity to the IC, and methods that reduce the probability that alpha particles emitted from materials will reach the sensitive devices. Material and IC vendors are always scrutinizing their processes and raw materials to eliminate

Fig. 3. Alpha energy spectrum obtained from a thick foil of solid Th-232. Note that the discrete alpha particle emission energies are broadened due to energy lost in travelling different (random) distances before reaching the surface and being detected.

before being “stopped” by the material. The distance required to the major causes of contamination. As a result, most of the stop an alpha particle (its range) is both a function of its energy IC and packaging materials went from emitting alpha partiand the properties of the material (primarily the material’s cles at rates as high as 100 α/h cm2 down to levels below density) in which it is traveling. In silicon, the range for a 0.001 α/h cm2. As a prerequisite that a material be ultra low 10-MeV alpha particle is < 100 µm. Thus, alpha particles from alpha (ULA implies emission at or below 0.002 α/h cm2), the outside the packaged device are clearly not a concern—only 238U and 232Th impurity content must be below about one part alpha particles emitted by the device materials and packaging per 10 billion. Again, this is not a guarantee that the material materials need be considered. The energy spectrum of alpha will meet the ULA emission specification since higher activity particles emitted from the surface of a thick sample of 232Th daughters may regrow. To ensure that the alpha emission rate is (the spectrum from 238U is similar in that the bulk of the a low-enough measurement of the alpha particles emitted, direct emission is in the 4–6 MeV range) is shown in Fig. 3. This alpha counting techniques must be employed. In lead-based broad energy spectrum is characteristic of the alpha particle flux solders, this is especially true, where chemical separation will in packaged ICs as the discrete emission energies are “smeared- leave known radioactive daughter products, samples should be out” since alpha emitters are generally uniformly distributed in measured several times over several months to ensure that there

  • the different materials.
  • is no significant ingrowth of alpha-emitting daughter products

Since virtually all semiconductor materials are highly puri- that would increase the material’s alpha particle emission. One fied, the alpha emitting impurities will generally not be in equi- of the challenges of advanced technologies is verifying that librium. Alpha counting must be used to determine the alpha all materials meet or exceed the ULA specification. In the emission since the exact nature of parent/daughter distributions majority of CMOS devices, if semiconductor manufacturing is seldom known. In other words, a low concentration of ura- and packaging materials could be purified such that together

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  • TABLE
  • I

REACTION PRODUCTS AND THRESHOLD ENERGIES
FOR n + 28Si REACTIONS

Fig. 4. Cosmic ray differential neutron flux as a function of neutron energy at sea level. Adapted from [13].

they contributed < 0.001 α/h cm2, the fraction of soft errors from alpha particles would fall to less than 20% in most cases (based on accelerated testing and simulation results). At this point, further emission reduction becomes prohibitively expensive while providing diminishing returns since the SER is dominated by cosmic background radiation.

Fig. 5. Burst generation rate (per cubic micrometer hour) versus neutron energy for various burst energies. Note that the probability of a burst event drops as the burst energy increases—larger higher-energy bursts are rarer than smaller low-energy bursts. Adapted from [22].

C. High-Energy   Cosmic Rays

The second significant source of SER is related to cosmic ray events. Primary cosmic rays are thought to be of galactic origin. They react with the Earth’s atmosphere via the strong

  • interaction and produce complex cascades of secondary par-
  • Since neutrons themselves do not directly generate ionization

ticles. These in turn continue on deeper into the atmosphere, in silicon, the neutron flux alone does not define the cosmic creating tertiary particle cascades, and so on. At terrestrial component of SER. Neutrons interact with chip materials elastialtitudes (as opposed to flight or satellite altitudes), less than cally and inelastically. Inelastic reactions typically end with the 1% of the primary flux reaches the sea level where the flux excited nucleus breaking into lighter fragments. The reaction is isotropic and composed of muons, protons, neutrons, and cross sections for both elastic and inelastic reactions decrease pions [13]. Neutrons are one of the higher flux components, rapidly with increasing neutron energy (generally following a and since neutron reactions have higher LETs, they are the most 1/E dependence). Nuclear physics simulations have been used likely cosmic radiation to cause upsets in devices at terrestrial to calculate the distributions in energy of reaction products altitudes (assuming 10B and alpha emitting impurities have generated as a function of incident neutron energy [18], [19]. been minimized). The “accepted” cosmic differential neutron Table I summarizes some of the reactions that occur when a flux at sea level is shown in Fig. 4. This curve defines how neutron interacts with a silicon nucleus.

  • many neutrons over the given energy range are incident on a
  • When the silicon nucleus fragments in these inelastic reac-

device at sea level. Recent work has been published improving tions, the resultant products are a lighter ion with additional the accuracy of this data [14], [15]. The neutron flux is strongly particles (neutrons, protons, and/or alpha particles). Kinetic dependent on altitude with the intensity of the cosmic ray energy is shared among the particles and momentum is conneutron flux increasing with increasing altitude. For example, served so the particles tend to be emitted in opposing directions, in going from sea level to 10 000 ft, the cosmic ray flux such that only one reaction product will cause the soft error increases 10× (this trend starts to saturate at about 50 000 ft.). [20]. Note that as the energy of the incident neutron gets higher, Hence, altitude can have a significant impact on a customer’s the number of reaction pathways increases. Similar reactions perceived SER. Due to proton shielding effects induced by also occur with neutrons and oxygen, and since SiO2 is in interactions with the Earth’s magnetic field, the neutron flux close proximity to the active junction areas, these reactions is also dependent on magnetic rigidity—on geographical loca- can also contribute to the overall SER [21]. Some simulation (this effect is less pronounced than the variation due to tion results are shown in Fig. 5, illustrating the charge burst altitude). A clear and comprehensive assessment of terrestrial generation rate in silicon as a function of different neutron cosmic radiation as a function of altitude and location has been energies and burst energies [22]. The probability of higher

  • published [16], [17].
  • energy bursts increases with increasing neutron energy. More

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importantly, however, the burst generation rate drops rapidly as the recoil energy is increases. In fact, a 1-MeV burst is 100–3000 times more likely than a 15-MeV burst. The LET for silicon reaction products is significantly higher than that of alpha particles so when they occur cosmic events have a significantly higher potential to upset semiconductor devices as compared to alpha particle events. Additionally, certain soft error effects (described earlier) like MBU and SEL cannot generally be induced by alpha particles because the LET threshold for these types of 0.1 events is above 16 fC/µm. Thus, MBU and SEL are typically due to high-energy neutron effects.
Unlike alpha particles, the cosmic neutron flux cannot be reduced significantly at the chip level with shielding, keep-out zones, or high purity materials. Concrete has been shown to shield the cosmic radiation at a rate of approximately 1.4× per foot [23] of concrete thickness. Thus, while the SER due to cosmic neutrons of a system operating in a basement surrounded by many feet of concrete could be significantly reduced (a viable

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  • Soft Errors of Semiconductors Caused by Secondary Cosmic-Ray Neutrons

    Soft Errors of Semiconductors Caused by Secondary Cosmic-Ray Neutrons

    JP0350353 JAERI-Conf 2003-006 3.26 Soft Errors of Semiconductors Caused by Secondary Cosmic-ray Neutrons HidenoriSAWAMURA*11*2 TetsuoIGUCHI+2 TakanobuHANDA+1 *1 Computer Software Development Co., Ltd. Ton-iihisa-cho, Sinjyuku-ku, Tokyo, 162-0067 e-mail: sawamuracsd.co'p *2 Departinent of Nuclear Engineering, Nagoya University Furo-6110, Chigusa-ku, Nagoya-shi, AICHI, 464-01 e-mail: sawainuraavocet.nucl.nagoya-u.acjp Cosmic-ray spallations in the atmosphere produce high energy neutrons, and these neutrons wake up an upset of bits on memory devices. This phenomenon is called'soft error'or 'single-event upset. The neutron originated soft errors are mainly caused by nuclear reawtiODS between a silicon ncleus and a high energy neutrons, wich produce a-particles alld Mg, Al ad other fragments. A preliminary analysis have been made on the neutron iduced soft error by simulating behaviors on neutrons and a particles of their nuclear reaction product Si with MCNP-Xfl]qANL) and LAHET150(LANL) datasets. Key words: Semiconductor, Neutron, Cosmic-ray, Single-evey)t-upset, Soft error 1. Introduction Semiconductor soft errors on memory bits caused by secondary cosmic-ray neutrons were reported i 1979 by ZiegiarM[31. In those days, attention was oly paid to the soft error caused by a -particles[) fiom decay of a very small amount of radioactive impurities in semiconductors. The soft error by secondary cosmic-ray neutrons had not been remarked until 1999s. In 1994, however, 'Gormanet al. reported that the contribution of neutrons to the soft error was almost equal to that of a -particles from the radioactive ipurities for 288Ebit DRAM151 chips.
  • Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes

    Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes

    128 IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING, VOL. 1, NO. 2, APRIL-JUNE 2004 Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes Tanay Karnik, Senior Member, IEEE,PeterHazucha,Member, IEEE,andJagdishPatel Abstract—Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high- performance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given. Index Terms—High performance, error tolerance, reliability, soft error, single event upset. æ 1INTRODUCTION LECTRONIC circuits encode information in the form of a array with the original data. The memory was not damaged Echarge stored on a circuit node or as a current flowing and, if the same data were stored again, after some time the between two circuit nodes. For example, one bit of static errors would reappear at different locations. Due to their memory contains two nodes that store two complementary nonpermanent, nonrecurring nature, these errors were charges corresponding to logic “1” and logic “0.” The bit called soft errors. values “1” and “0” can be stored as node charges “10” and The failures were traced to alpha particles emitted from a “01,” respectively.
  • Circuit Design Methodologies for Soft Error Resilience in Nano-Scaled CMOS Technologies N

    Circuit Design Methodologies for Soft Error Resilience in Nano-Scaled CMOS Technologies N

    Circuit Design Methodologies for Soft Error Resilience in Nano-Scaled CMOS Technologies N. George and R.W.Mann ECE 632 – Fall 2008 University of Virginia [njg3v,rwm3p]@virginia.edu ABSTRACT The aggressive scaling of CMOS technologies continues in an attempt to stay on track with Moore’s Law. Methods that lower device sizes, operating voltages, and increase operating frequencies with each technology generation also increase susceptibility of these devices to soft errors. We analyze this trend in both SRAM and logic structures by evaluating the minimum charge required to cause an upset in these circuits. We explore methods to increase Qcrit in SRAM using novel topologies that increase node capacitance. We also extend bit interleaving, a well-known method for protecting memories against multi-bit errors, to combinational and sequential logic to Figure 1 Area covered by a 2 m radius with respect to the render immunity to multi-bit errors. µ area of two 3-bit registers at various technology nodes 1. INTRODUCTION particle is ionized, it interacts with the silicon lattice to produce As CMOS technologies continue to scale into the nanometer a column of electron-hole pairs along the trajectory path, which regime, the potential soft error rate (SER) impact to both SRAM can cause an upset of the sensitive circuit node. and logic circuits is increasing. The evolution of CMOS An additional consequence of scaling is the probability of multi- technologies has been characterized by aggressive device bit errors, which occur when single or multiple particle strike scaling in order to achieve higher performance with lower power induces errors on multiple bits or logic nodes.
  • Memory and Logic Soft Error Improvement Using Phase Transition

    Memory and Logic Soft Error Improvement Using Phase Transition

    Memory and Logic soft error improvement using phase transition material assisted transistors SS Teja Nibhanupudi, Amritesh Rai, Anupam Roy, Sanjay K.Banerjee and Jaydeep P. Kulkarni Department of ECE, University of Texas at Austin, USA Email: [email protected], [email protected] 1. We propose integration of phase transition material onto the Abstract— Phase transition Material (PTM) assisted logic and baseline CMOS for improved soft error tolerance. SRAM bitcells have been proposed with improved soft error 2. We evaluate the soft error performance of PTM assisted 6T tolerance. The large insulating resistance of PTM hinders the SRAM bit cell for single event upset (SEU) radiation strike propagation of glitches to subsequent stages thereby improving the and compare with other CMOS variants. immunity to radiation strikes. Also, the abrupt switching to metallic 3. We present a detailed analysis describing the influence of phase minimizes the delay penalty thereby offering an optimized PTM parameters and the impact of PTM switching time on solution. We present a detailed PTM parameter optimization for the soft error tolerance of circuits. optimum soft error performance. We also quantify the improvement 4. We propose PTM assisted logic circuits with enhanced in the Soft Error Tolerance of logic and 6T SRAM bit cell immunity to soft errors. configuration. Index Terms— Phase Transition Material (PTM), Soft Error II. PHASE TRANSITION MATERIAL Tolerance (SET), Critical Charge A. Phase Transition Material I. INTRODUCTION Transition metal oxides such as Vanadium dioxide (VO2) or The reducing feature size and operating voltages of modern day Niobium dioxide (NbO2) undergo phase transition under silicon circuits is dramatically increasing their vulnerability to soft application of external electric field [8-9].