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3.1 a 22Nm Soc Platform Technology Featuring 3-D Tri-Gate and High-K/Metal Gate, Optimized for Ultra Low Power, High Performan

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3.1 a 22Nm Soc Platform Technology Featuring 3-D Tri-Gate and High-K/Metal Gate, Optimized for Ultra Low Power, High Performan A 22nm SoC Platform Technology Featuring 3-D Tri-Gate and High-k/Metal Gate, Optimized for Ultra Low Power, High Performance and High Density SoC Applications C.-H. Jan, U. Bhattacharya, R. Brain, S .- J. Choi, G. Curello, G. Gupta, W. Hafez, M. Jang, M. Kang, K. Komeyli, T. Leo, N. Nidhi, L. Pan, J. Park, K. Phoa, A. Rahman, C. Staus, H. Tashiro, C. Tsai, P. Vandervoorn, L. Yang, J.-Y. Yeh, P. Bai Logic Technology Development, Intel Corporation, Hillsboro, Oregon, USA contact: [email protected] Abstract Transistor Architecture and Process Flow A leading edge 22nm 3-D tri-gate transistor technology This Tri-Gate-based 3-D SoC technology employs a has been optimized for low power SoC products for the first dual-gate oxide flow to support three main transistor families, time. Low standby power and high voltage transistors including high-speed logic (HP/SP), low-power logic exploiting the superior short channel control, < 65mV/dec (LP/ULP) and high-voltage I/O (TG) transistors, to subthreshold slope and <40mV DIBL, of the Tri-Gate simultaneously reduce the leakage floor to ~10 pA/um and to architecture have been fabricated concurrently with high extend the supportable voltage ceiling to > 5V. HP/SP and speed logic transistors in a single SoC chip to achieve LP/ULP transistors share the same low gate leakage high- industry leading drive currents at record low leakage levels. k/metal-gate dielectric stack, while the TG transistors employ NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um Ioff, a hybrid SiO /high-k high voltage tolerant gate stack as 0.75V, were used to build a low standby power 380Mb 2 shown in Figs. 1-2. Each transistor family supports individual SRAM capable of operating at 2.6GHz with 10pA/cell electro-static tuning mechanisms to achieve the necessary standby leakages. This technology offers mix-and-match device and reliability targets, and is fabricated with an overall flexibility of transistor types, high-density interconnect process sequence similar to the 32nm planar SoC technology, stacks, and RF/mixed-signal features for leadership in with the exception of the addition of fin-related diffusion mobile, handheld, wireless and embedded SoC products. fabrication [3]. Introduction As CMOS technology scales down to 22nm, traditional Table I. 22nm modular SoC transistor options and device characteristics planar transistor architectures [1-3] have reached a Transistor fundamental limit for the required short channel control Type High Speed Logic Low Power Logic High Voltage necessary to continue scaling at the rate dictated by Moore’s High Standard Low Ultra Low Options Performance Perf./ Power Power Power 1.8 V 3.3 V Law. Recently, novel 3-D Tri-Gate transistors have been (HP) (SP) (LP) (ULP) proven to be capable of high volume manufacturing for high Vdd 0.75 / 1 0.75 / 1 0.75 / 1 0.75/1.2 1.5/1.8/3.3 3.3 / >5 performance CPU products [4]. This paper reports, for the (Volt) Gate Pitch first time, a leading edge 22nm SoC process technology 90 90 90 108 min. 180 min. 450 featuring 3-D Tri-Gate transistors which employs high speed (nm) logic transistors, low standby power transistors and high- Lgate (nm) 30 34 34 40 min. 80 min. 280 voltage tolerant transistors simultaneously in a single SoC N/PMOS 1.08/ 0.91 0.71 / 0.59 0.41 / 0.37 0.35 / 0.33 0.92 / 0.8 1.0 / 0.85 Idsat/Ioff @ 0.75 V, @ 0.75 V, @ 0.75 V @ 0.75 V @ 1.8 V @ 3.3 V chip to support a wide range of products, including premium (mA/um) smart phones, tablets, netbooks, embedded systems, wireless 100 nA/um 1 nA/um 30 pA/um 15 pA/um 10 pA/um 10 pA/um communications, and ASIC products. Logic -High Speed (HP/SP) -Low Power (LP/ULP) (a) High Speed (HP/SP) and (b) High Voltage (TG) High Voltage Low Power Logic (LP/ULP) Fig. 1. 22 nm SoC Tri-Gate transistor families, including high speed logic (HP/SP), low power logic (LP/ULP) and high voltage (TG) Fig. 2. Fin cut TEM, gate cut TEM, and tilted SEM of logic thin gate (top) and high-voltage thick-gate (bottom) transistors 978-1-4673-4871-3/12/$31.00 ©2012 IEEE 3.1.1 IEDM12-44 The device characteristics of these transistors are planar transistors require high channel doping and VT to summarized in Table I. 193nm immersion lithography is control subthreshold leakages; such processes are not scalable widely used at design rule sensitive process steps. Self- and result in severe mobility and drive current degradation, aligned contacts (SAC) are developed for aggressive and high junction leakages. The Tri-Gate architecture transistor pitch scaling. High Ge-embedded epitaxial SiGe alleviates these challenges with superb short channel control technology is used for PMOS, raised S/D technology is used at minimal channel doping levels, reducing subthreshold in NMOS, and fifth-generation strained silicon technology is currents and resulting in significant mobility and drive used to provide compressive and tensile stress on P-ch and N- current gains over an equivalent planar architecture. Further ch devices. junction leakage reduction is realized through the use of a fully depleted fin and optimized source/drain and junction Logic Transistor–High Performance (HP)/Standard (SP) engineering to minimize parasitic leakages. Figures 3 and 4 The high speed logic transistor family includes two show that LP NMOS/PMOS drive currents can achieve device types – HP (High Performance) and SP (Standard 0.41/0.37mA/um at 30pA and 0.75V, respectively. This Performance/Power). This family of devices is constructed represents a 50% performance increase when compared to the on a 90nm pitch with a 30nm and 34nm gate length, and previously reported 32nm SOC planar process, and achieves achieves subthreshold leakages ranging from 100nA/um to the highest reported performance to date at the given 1nA/um for HP and SP transistors, respectively. Both device operating conditions. The ULP transistors use the same types can be simultaneously employed with the low power junction engineering optimizations as the LP devices, but logic and high voltage transistor families in a single SoC increase the gate pitch from 90nm to 108nm and the gate chip. The device characteristics of the high speed logic family length from 34nm to 40nm. The longer channel of the ULP are similar to previously reported state-of-the-art 22nm Tri- transistor enables a lower total leakage floor and supports Gate technology for high performance microprocessors higher operating voltages. Figures 5 and 6 show that an already in HVM production, and exhibit ~70mV/dec. outstanding subthreshold slope of < 65mV/dec. and 30-40 subthreshold slopes and low DIBL (~50mV/V) on both mV/V DIBL are achieved. A 100 mV VT reduction has been NMOS and PMOS transistors [4]. realized in the 22nm low power transistors vs. 32nm planar Low Power Logic Transistor – LP and ULP devices across a wide range of transistor gate lengths as shown in Fig. 7. The junction profile has been optimized to Low leakage (< 50pA/um) logic transistors are crucial mitigate the GIDL effect, which is the dominating source of for low standby power and always-on-always-connected junction leakages as shown in Fig. 8. circuitries in battery-powered SoC products. Traditional 1.E-02 NMOS @ 0.75V PMOS @0.75V Vds = -.75 V PMOS NMOS Vds = .75V Logic 100 100 nA 100 100 nA 1.E-03 HP Logic (HP) 32 nm [3] (HP) 32 nm [3] 1.E-04 SP 10 10 1.E-05 Vds = -.0 5 V Vds = .05 V Logic Logic 1.E-06 1 1 nA 1 1 nA LP (SP) (SP) 1.E-07 Ioff (nA/um) Ioff (nA/um) Ioff 0.1 0.1 (A/um)Ids 32 nm [3] Low Power 32 nm [3] Low Power 1.E-08 30 pA 30 pA (LP) 30 pA 30 pA (LP) 15 pA 15 pA 1.E-09 HP: S.S. = 72 mV/dec HP: S.S. = 71 mV/dec 0.01 Low Power 0.01 Low Power SP: S.S. = 66 mV/dec SP: S.S. = 66 mV/dec (ULP) (ULP) 1.E-10 LP: S.S. = 63 mV/dec LP: S.S. = 64 mV/dec DIBL = 35 mV/V DIBL = 30 mV/V 0.001 0.001 1.E-11 00.51 00.51 -1 0 1 IDNsat (mA/um) IDPsat (mA/ um) Vgs (V) Fig. 3. NMOS Ion vs. Ioff at 0.75V showing Fig. 4. PMOS Ion vs. Ioff at 0.75V showing Fig. 5. Id-vs.-Vg characteristics showing steep improvements of 21%, 42% and 64% at improvements of 26%, 44% and 68% at 100nA/ subthreshold and low DIBL, especially for LP 100nA/um (HP), 1nA/um (SP) and 30pA/um um (HP), 1 nA/um (SP) and 30pA/um (LP), transistors (< 65mV/dec S.S. and < 40mV DIBL) (LP), respectively respectively 120 1 0.6 22 nm Tri-gate NMOS Logic 1.8 V HV @ 0.05 V 32 nm - Low Power [3] 110 0.5 22 nm Tri-gate PMOS Transistor Transistor 32 nm - Logic [3] 0.4 NMOS 32 nm planar [3] 100 0.3 32 nm 22 nm Low Power 0.1 Vt n (V) 0.2 Planar 90 0.1 22 nm Logic (LP/ULP) (HP/SP) 32 nm 0 80 22 nm Logic Planar -0.1 (HP/SP) 22 nm Low Power 0.01 -0.2 Ioff (nA/um) 32 nm planar [3] 70 22 nm (LP/ULP) -0.3 3-D Tri-gate Vt p (V) -0.4 PMOS 60 22 nm S.S.
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