A 22nm SoC Platform Technology Featuring 3-D Tri-Gate and High-k/, Optimized for Ultra Low Power, High Performance and High Density SoC Applications

C.-H. Jan, U. Bhattacharya, R. Brain, S .- J. Choi, G. Curello, G. Gupta, W. Hafez, M. Jang, M. Kang, K. Komeyli, T. Leo, N. Nidhi, L. Pan, J. Park, K. Phoa, A. Rahman, C. Staus, H. Tashiro, C. Tsai, P. Vandervoorn, L. Yang, J.-Y. Yeh, P. Bai

Logic Technology Development, Corporation, Hillsboro, Oregon, USA contact: [email protected]

Abstract Architecture and Process Flow A leading edge 22nm 3-D tri-gate transistor technology This Tri-Gate-based 3-D SoC technology employs a has been optimized for low power SoC products for the first dual-gate oxide flow to support three main transistor families, time. Low standby power and high voltage including high-speed logic (HP/SP), low-power logic exploiting the superior short channel control, < 65mV/dec (LP/ULP) and high-voltage I/O (TG) transistors, to subthreshold slope and <40mV DIBL, of the Tri-Gate simultaneously reduce the leakage floor to ~10 pA/um and to architecture have been fabricated concurrently with high extend the supportable voltage ceiling to > 5V. HP/SP and speed logic transistors in a single SoC chip to achieve LP/ULP transistors share the same low gate leakage high- industry leading drive currents at record low leakage levels. k/metal-gate dielectric stack, while the TG transistors employ NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um Ioff, a hybrid SiO /high-k high voltage tolerant gate stack as 0.75V, were used to build a low standby power 380Mb 2 shown in Figs. 1-2. Each transistor family supports individual SRAM capable of operating at 2.6GHz with 10pA/cell electro-static tuning mechanisms to achieve the necessary standby leakages. This technology offers mix-and-match device and reliability targets, and is fabricated with an overall flexibility of transistor types, high-density interconnect process sequence similar to the 32nm planar SoC technology, stacks, and RF/mixed-signal features for leadership in with the exception of the addition of fin-related diffusion mobile, handheld, wireless and embedded SoC products. fabrication [3]. Introduction As CMOS technology scales down to 22nm, traditional Table I. 22nm modular SoC transistor options and device characteristics planar transistor architectures [1-3] have reached a Transistor fundamental limit for the required short channel control Type High Speed Logic Low Power Logic High Voltage necessary to continue scaling at the rate dictated by Moore’s High Standard Low Ultra Low Options Performance Perf./ Power Power Power 1.8 V 3.3 V Law. Recently, novel 3-D Tri-Gate transistors have been (HP) (SP) (LP) (ULP) proven to be capable of high volume manufacturing for high Vdd 0.75 / 1 0.75 / 1 0.75 / 1 0.75/1.2 1.5/1.8/3.3 3.3 / >5 performance CPU products [4]. This paper reports, for the (Volt) Gate Pitch first time, a leading edge 22nm SoC process technology 90 90 90 108 min. 180 min. 450 featuring 3-D Tri-Gate transistors which employs high speed (nm) logic transistors, low standby power transistors and high- Lgate (nm) 30 34 34 40 min. 80 min. 280 voltage tolerant transistors simultaneously in a single SoC N/PMOS 1.08/ 0.91 0.71 / 0.59 0.41 / 0.37 0.35 / 0.33 0.92 / 0.8 1.0 / 0.85 Idsat/Ioff @ 0.75 V, @ 0.75 V, @ 0.75 V @ 0.75 V @ 1.8 V @ 3.3 V chip to support a wide range of products, including premium (mA/um) smart phones, tablets, netbooks, embedded systems, wireless 100 nA/um 1 nA/um 30 pA/um 15 pA/um 10 pA/um 10 pA/um communications, and ASIC products.

Logic -High Speed (HP/SP) -Low Power (LP/ULP)

(a) High Speed (HP/SP) and (b) High Voltage (TG) High Voltage Low Power Logic (LP/ULP) Fig. 1. 22 nm SoC Tri-Gate transistor families, including high speed logic (HP/SP), low power logic (LP/ULP) and high voltage (TG) Fig. 2. Fin cut TEM, gate cut TEM, and tilted SEM of logic thin gate (top) and high-voltage thick-gate (bottom) transistors

978-1-4673-4871-3/12/$31.00 ©2012 IEEE 3.1.1 IEDM12-44 The device characteristics of these transistors are planar transistors require high channel doping and VT to summarized in Table I. 193nm immersion lithography is control subthreshold leakages; such processes are not scalable widely used at design rule sensitive process steps. Self- and result in severe mobility and drive current degradation, aligned contacts (SAC) are developed for aggressive and high junction leakages. The Tri-Gate architecture transistor pitch scaling. High Ge-embedded epitaxial SiGe alleviates these challenges with superb short channel control technology is used for PMOS, raised S/D technology is used at minimal channel doping levels, reducing subthreshold in NMOS, and fifth-generation strained silicon technology is currents and resulting in significant mobility and drive used to provide compressive and tensile stress on P-ch and N- current gains over an equivalent planar architecture. Further ch devices. junction leakage reduction is realized through the use of a fully depleted fin and optimized source/drain and junction Logic Transistor–High Performance (HP)/Standard (SP) engineering to minimize parasitic leakages. Figures 3 and 4 The high speed logic transistor family includes two show that LP NMOS/PMOS drive currents can achieve device types – HP (High Performance) and SP (Standard 0.41/0.37mA/um at 30pA and 0.75V, respectively. This Performance/Power). This family of devices is constructed represents a 50% performance increase when compared to the on a 90nm pitch with a 30nm and 34nm gate length, and previously reported 32nm SOC planar process, and achieves achieves subthreshold leakages ranging from 100nA/um to the highest reported performance to date at the given 1nA/um for HP and SP transistors, respectively. Both device operating conditions. The ULP transistors use the same types can be simultaneously employed with the low power junction engineering optimizations as the LP devices, but logic and high voltage transistor families in a single SoC increase the gate pitch from 90nm to 108nm and the gate chip. The device characteristics of the high speed length from 34nm to 40nm. The longer channel of the ULP are similar to previously reported state-of-the-art 22nm Tri- transistor enables a lower total leakage floor and supports Gate technology for high performance higher operating voltages. Figures 5 and 6 show that an already in HVM production, and exhibit ~70mV/dec. outstanding subthreshold slope of < 65mV/dec. and 30-40 subthreshold slopes and low DIBL (~50mV/V) on both mV/V DIBL are achieved. A 100 mV VT reduction has been NMOS and PMOS transistors [4]. realized in the 22nm low power transistors vs. 32nm planar Low Power Logic Transistor – LP and ULP devices across a wide range of transistor gate lengths as shown in Fig. 7. The junction profile has been optimized to Low leakage (< 50pA/um) logic transistors are crucial mitigate the GIDL effect, which is the dominating source of for low standby power and always-on-always-connected junction leakages as shown in Fig. 8. circuitries in battery-powered SoC products. Traditional

1.E-02 NMOS @ 0.75V PMOS @0.75V Vds = -.75 V PMOS NMOS Vds = .75V Logic 100 100 nA 100 100 nA 1.E-03 HP Logic (HP) 32 nm [3] (HP) 32 nm [3] 1.E-04 SP 10 10 1.E-05 Vds = -.0 5 V Vds = .05 V

Logic Logic 1.E-06 1 1 nA 1 1 nA LP (SP) (SP) 1.E-07 Ioff (nA/um) Ioff (nA/um) Ioff 0.1 0.1 (A/um)Ids 32 nm [3] Low Power 32 nm [3] Low Power 1.E-08 30 pA 30 pA (LP) 30 pA 30 pA (LP) 15 pA 15 pA 1.E-09 HP: S.S. = 72 mV/dec HP: S.S. = 71 mV/dec 0.01 Low Power 0.01 Low Power SP: S.S. = 66 mV/dec SP: S.S. = 66 mV/dec (ULP) (ULP) 1.E-10 LP: S.S. = 63 mV/dec LP: S.S. = 64 mV/dec DIBL = 35 mV/V DIBL = 30 mV/V 0.001 0.001 1.E-11 00.51 00.51 -1 0 1 IDNsat (mA/um) IDPsat (mA/ um) Vgs (V) Fig. 3. NMOS Ion vs. Ioff at 0.75V showing Fig. 4. PMOS Ion vs. Ioff at 0.75V showing Fig. 5. Id-vs.-Vg characteristics showing steep improvements of 21%, 42% and 64% at improvements of 26%, 44% and 68% at 100nA/ subthreshold and low DIBL, especially for LP 100nA/um (HP), 1nA/um (SP) and 30pA/um um (HP), 1 nA/um (SP) and 30pA/um (LP), transistors (< 65mV/dec S.S. and < 40mV DIBL) (LP), respectively respectively 120 1 0.6 22 nm Tri-gate NMOS Logic 1.8 V HV @ 0.05 V 32 nm - Low Power [3] 110 0.5 22 nm Tri-gate PMOS Transistor Transistor 32 nm - Logic [3] 0.4 NMOS 32 nm planar [3] 100 0.3 32 nm 22 nm Low Power 0.1

Vt n (V) 0.2 Planar 90 0.1 22 nm Logic (LP/ULP) (HP/SP) 32 nm 0 80 22 nm Logic Planar -0.1 (HP/SP) 22 nm Low Power 0.01 -0.2 Ioff (nA/um) 32 nm planar [3] 70 22 nm (LP/ULP) -0.3 3-D Tri-gate

Vt p (V) -0.4 PMOS 60 22 nm S.S. = 60 mV/dec -0.5 3-D Tri-gate 32 nm - Logic [2] 22 nm tri-gate Sub-threshold Slope (mV/decade) Slope Sub-threshold 32 nm - Low Power [2] 50 -0.6 0.001 0 100 200 300 25 30 35 40 45 50 0.001 0.01 0.1 1 Poly CD (nm) Lgat e (nm) Ijunction (nA/um) Fig. 6. Subthreshold slope comparison of 32nm Fig. 7. Vt-vs.-L characteristics of 22nm high speed Fig. 8. Ioff vs. GIDL/Ijunction trade-off and planar vs. 22nm Tri-Gate for logic and 1.8V HV logic (HP/SP) and low power logic (LP/ULP) optimization for 22nm Tri-Gate process compared to the 32nm planar IEDM12-45transistors 3.1.2 High Voltage I/O Transistors Interconnects High voltage transistors are required in an SoC process This technology offers the flexibility of mixing-and- technology to support legacy high voltage I/Os, analog matching eight to eleven layers of low-k (LK) and ultra low-k circuits, voltage regulation and communication designs. This (ULK) carbon-doped oxide (CDO) ILD stacks, as shown in technology offers native 1.8V or 3.3V transistors constructed Fig. 14, for different SoC product segments. M1 employs using a composite high-k/oxide gate dielectric. The short double patterning to enable tight pitch and complex layouts. channel control benefits of the Tri-Gate architecture also All other metal layers are fabricated with cost effective single pertain to these high-voltage transistors, resulting in >50% patterning lithography. The tightest pitch layers are patterned drive current improvements and great I/O scaling over the with the self-aligned via (SAV) process with a sacrificial hard 32nm planar counterparts (Figs. 9/10). NMOS/PMOS I/O mask [5]. A 6um thick top metal layer is used for on-die transistor drive currents are 0.92/0.8 mA/um at 1.8 V and 10 power distribution and spiral (Fig. 15). Density pA/um Ioff (Table 1) - the highest reported performance for focused products employ up to six layers of minimum pitch an SoC technology. The primary integration challenges for (80nm) metal layers, while RC driven products are optimized high voltage transistors are the many inward and outward for more relaxed pitcher layers (Table 2 and Fig. 16). edges and corners existing in the non-planar technology, but extensive integration optimizations have resolved these issues to achieve the good TDDB, hot carrier, and BTI reliability results shown in Figs. 11-13.

1.E-09 1E-09 1.E+09 65 nm 45 nm 65 nm 45 nm Ox / Pol y Hi-k/ MG Ox / Pol y Hi-k/ MG 32 nm 1.E+08 32nm Planar 32 nm 22 nm Hi-k/ MG 22nm Tri-gate Hi-k/ MG Tri-gate 1.E+07 100 pA/um Hi-k/ MG 32nm Planar TG 100 pA/um 1.E+06 1.E-10 1E-10 22nm Tri-gate TG 1.E+05

1.E+04 + 51% 10 pA/um + 56% Ioff (A/um) 10 pA/um 1.E+03 1.E-11 Ioff (A/um) 1E-11 22 nm 1.E+02 Timet o Fail [sec] PMOS Tri-gat e NMOS Hi-k/ MG 1.E+01 @ 1.8 V @ 1.8 V 1.E+00 1.E-12 1E-12 51015 00.51 0.0 0.5 1.0 IDsat (mA/um) IDsat (mA/ um) VG/EOT [MV/cm] Fig. 9. NMOS high voltage transistor drive current Fig. 10. PMOS high voltage transistor drive Fig. 11. PMOS logic and HV I/O gate dielectrics trend showing 51% performance improvement current trend showing 56% performance TDDB comparison – 32 nm vs. 22 nm over 32nm improvement over 32 nm 10 10 32nm Planar 32 nm Planar 8 22nm FinFET 8 22nm Tri-gate

Int rinsic 6 Improvement 6

4 4 %ID_Vcc %ID_Vcc Int rinsic BTI Top Metal mat ched or bett er 2 2 Fig. 14. Ultra low k (ULK) carbon-doped 0 0 oxide (CDO) employed Fig. 15. Thick top metal, copper bump and solder joint developed for the 22 nm node 0.05 0.10 0.15 012345 in the tight pitch process VDS/L_drawn [MV/cm] VG/EOT [MV/cm] interconnect layers of Fig. 12. NMOS HV I/O transistor Fig. 13. PMOS HV I/O transistor this technology hot carrier effect – 32 nm vs. 22 nm NBTI comparison – 32 nm vs. 22 nm

Table 2. 22 nm interconnect pitches

Layer Pitch Process Dielectric CPU SoC 4 x pitch (nm) Materials Fin 60 - - Fin Fin Contact 90 SAC - Contact Contact 4 x pitch 3 x pitch M1 90 SAV ULK CDO M1 M1

MT - 1X 80 SAV ULK CDO M2/M3 2-6 layers 3 x pitch MT – 1.4x 112 SAV ULK CDO M4 Semi-global 2 x pitch 2 x pitch MT – 2x 160 SAV ULK CDO M5 Semi-global 1.4 x pitch 1.4 x pitch Fig.16. MT – 3x 240 SAV ULK CDO M6 Global Routing 1 x pitch Interconnect 1 x pitch 320 Via First LK CDO ( 2- 6 layers) architecture MT – 4x M7/8 Global Routing 360 comparison of MT - TOP 14 um Plate Up Polymer M9 Top Metal 22 nm CPU High Perf High Density and SoC CPU SoC technologies

3.1.3 IEDM12-46 low voltage (0.108um2. LVC) and high performance Analog/Mixed Signals and Passives 2 (0.130um , HPC) bit cells [6]. Dual-port SRAM options A full suite of analog and mixed signal features are include synchronous and asynchronous cell types. Exploiting offered in this technology to meet the divergent SoC product the supreme short channel control of the Tri-Gate technology, needs. Gm-Rout metrics are significantly improved due to a > 4 x improvement has achieved at 1 V standby benchmark improved channel control as shown in Fig. 17, and is critical conditions for HDC LP SRAM, as shown in Fig. 22. The for enabling analog features to maintain the pace of CMOS SRAM operating frequencies have improved to 4.6, 3.5 and digital technology scaling. Precision achieve < 15% 2.6 GHz at 1V for HP, SP and LP processes as shown in Fig. variation for a large population of sites (Fig. 18). In addition 23. Low Vccmin and high SRAM yields have been achieved to the standard device and metal finger offerings, a on 380 Mb SRAM, equivalent to the CPU technology. new MIMCAP architecture is supported in this technology to provide an additional high density capacitance source (Fig. References 19). Spiral inductors are constructed on a thick metal (TM) 1. T. Ghani et al, IEDM Tech. Dig., pp. 978-980, 2003 layer to support inductive SoC circuitries (Fig. 20). 2. K. Mistry et al, IEDM Tech Dig., pp. 247-250, 2007 3. C.-H. Jan et al, IEDM Tech. Dig., pp. 647-650, 2009 Low Voltage and Low Standby Power SRAM 4. C. Auth et al, VLSI Symp. Tech., pp 131-132, 2012 A rich collection of single and dual-port SRAMs are 5. D. Ingerly et al, IITC, 2012 offered in this technology, Fig. 21. Single-port SRAM 6. E. Karl et al, ISSCC Tech Dig., p.230-232, 2012 options include high density/ low leakage (0.092um2, HDC),

15 -15% + 15%

10

GM * Ro u t 5

GM*Rout@Vgs=peak GM, Vds=1.1 V, NMOS 0 65nm 45nm 32nm 22nm 10090 110 Planar Planar Planar Tri-gat e Normalized Resistance Fig. 20. A full collection of Fig. 17. Analog device Fig. 18. A precision is offered Fig. 19. MIMCAP developed for high quality factor spiral characteristics gm*Rout trend inductors are offered for mixed- showing significant improvement with well-controlled resistance 22nm Tri-Gate process [4] from planar (65nm- 32nm) to Tri- distribution signal and communication Gate (22nm) applications

1000 800 MHz 1.8 GHz 2.6 GHz 3.5 GHz 4.6 GHz 1.0 6T SRAM 65nm LP Planar 32 nm LP HDC [3] 22 nm LP (0.092 um2) 0.9 Planar [4] 100 Tri-gate 22 nm SP Tri-gate 22 nm HP 6T SRAM Tri-gate [6] 0.8 Pass LVC (0.108 um2) 10 0.7 6T SRAM Supply Volt age (V) 150 mV Fai l

HPC Bit Leakage (pA/cell)Cell @ Vcc = 1 V, Standby 0.6 (0.130 um2) 1 0.0 1.0 2.0 3.0 4.0 5.0 32nm LP 22nm LP Fig. 21. Selected SRAM options Operat ing Frequency (GHz) provided in this SoC technology, Fig. 22. HDC SRAM bit cell standby leakages including high density /low leakage Fig. 23. SRAM operating frequency Schmoo plot of comparison at 1 V showing 4-5x improvement LVC cells showing 40% frequency (2.6GHz vs. (HDC), low voltage (LVC), high ver 32 nm planar LP SRAM [3] via low standby performance (HPC) and dual port 1.8GHz at 1V) or 150mV Vmin reduction over power Tri-Gate process 32nm planar LP SRAM

IEDM12-47 3.1.4