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Two Phase Clocked Adiabatic Static CMOS Logic and Its Logic Family JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.10, NO.1, MARCH, 2010 1 Two Phase Clocked Adiabatic Static CMOS Logic and its Logic Family Nazrul Anuar, Yasuhiro Takahashi, and Toshikazu Sekine Abstract—This paper proposes a two-phase clocked that help achieve high energy efficiency. The power adiabatic static CMOS logic (2PASCL) circuit that consumption in digital circuits, which mostly use utilizes the principles of adiabatic switching and complementary metal-oxide semiconductor (CMOS) energy recovery. The low-power 2PASCL circuit uses devices, is proportional to the square of the power supply two complementary split-level sinusoidal power voltage; therefore, voltage scaling is one of the important supply clocks whose height is equal to Vdd. It can be methods used to reduce power consumption. To achieve directly derived from static CMOS circuits. By a high transistor drive current and thereby improve the removing the diode from the charging path, higher circuit performance, the transistor threshold voltage must output amplitude is achieved and the power consumption be scaled down in proportion to the supply voltage. of the diode is eliminated. 2PASCL has switching However, scaling down of the transistor threshold activity that is lower than dynamic logic. We also voltage Vt results in significant increase in the design and simulate NOT, NAND, NOR, and XOR subthreshold leakage current [1]. logic gates on the basis of the 2PASCL topology. Recently, adiabatic computing has been applied to From the simulation results, we find that 2PASCL 4- low-power systems, and several early adiabatic logic inverter chain logic can save up to 79% of dissipated families have been proposed [2-5] emphasizing on the energy as compared to that with a static CMOS logic energy recovery principle. Then, several other papers on at transition frequencies of 1 to 100 MHz. The results adiabatic logics have been published [6-15] for low- indicate that 2PASCL technology can be advantageously power logic applications. The energy dissipated in applied to low power digital devices operated at low adiabatic circuits is considerably less than that in static frequencies, such as radio-frequency identifications CMOS circuits; hence, adiabatic circuits are promising (RFIDs), smart cards, and sensors. candidates for low-power circuits that can be operated in the frequency range in which signals are digitally Index Terms—Adiabatic logic, low-power, two phase processed. However, diode-based logic families [3, 4, 6, clocked, energy recovery, split-level, power clock 9, 11, 14, 15] have several disadvantages such as output generator amplitude degradation and power dissipation across the diodes in the charging path. I. INTRODUCTION In this paper, we propose a two-phase clocked adiabatic static CMOS logic (2PASCL) [16] circuit to In recent times, researchers have focused on achieve low power consumption; we also compare its increasing clock and logic speeds in order to enhance the power consumption with that of a conventional CMOS performance of mobile and wireless devices; hence, it circuit. has become important to design integrated circuits (ICs) A novel method for reducing the power dissipation in a 2PASCL circuit involves the design of a charging path Manuscript received Sep. 26, 2009; revised Jan. 16, 2010. without diodes. In such a case, current flows only Graduate School of Electronical Information & System Engineering, through the transistor during the charging. Thus, a Gifu University, Japan E-mail : [email protected] 2PASCL circuit is different from other diode-based 2 NAZRUL ANUAR et al : TWO PHASE CLOCKED ADIABATIC STATIC CMOS LOGIC AND ITS LOGIC FAMILY adiabatic circuits in which current flows through both the supplied to CL, the energy stored in CL becomes one-half 2 diode and transistor. By using the aforementioned the supplied energy, i.e., Estored=0.5CLV dd. 2PASCL circuit, we can achieve high output amplitudes The remaining energy is dissipated in R. The same and reduce power dissipation. In addition, in order to amount of energy is dissipated during discharging in the minimize the dynamic power consumption in this circuit, nMOS pull-down network when the logic level in the we apply a split-level sinusoidal driving voltage. system is “0.” Therefore, the total amount of energy The remainder of this paper is divided into five dissipated as heat during charging and discharging is sections. Section II describes the differences between CMOS and adiabatic logic circuits. In Section III, the E total = Echarge + Edischarge structure and operation of a 2PASCL circuit are 2 2 2 (1) = 0.5CLV + 0.5CLV = CLV explained. Section IV describes the simulation of a dd dd dd 2PASCL inverter and other logic gates and also provides a comparison between the power dissipations in 2PASCL From the above equation, it is apparent that the energy and CMOS circuits. In Section V, the power clock consumption in a conventional CMOS circuit can be generator circuit is introduced. Section VI discusses the reduced by reducing Vdd. By decreasing the switching advantages and disadvantages of 2PASCL, while Section activity in the circuit, the power consumption (P= dE/dt) VII includes concluding remarks. can also be proportionally suppressed. 2. Adiabatic Logic Circuits II. CMOS CIRCUITS VIS-A-VIS ADIABATIC LOGIC CIRCUITS A. Adiabatic Logic Principle Adiabatic switching is commonly used to minimize 1. CMOS Circuits energy loss during charging/discharging. The word “adiabatic” (Greek adiabatos, which means impassable) Power dissipation in conventional CMOS circuits indicates a state change that occurs without heat loss or primarily occurs during device switching. As shown in gain. During adiabatic switching, all the nodes are Fig. 1, both pMOS and nMOS transistors can be charged or discharged at a constant current in order to modeled by including an ideal switch in series with a minimize power dissipation. This is accomplished by resistor in order to represent the effective channel using AC power supplies to initially charge the circuit resistance of the switch and the interconnect resistance. during specific adiabatic phases and then discharge the The pull-up and pull-down networks are connected to circuit to recover the supplied charge. The principle of the node capacitance CL, which is referred to as the load adiabatic switching can be best explained by contrasting capacitance in this paper. it with the conventional dissipative switching technique. When the logic level in the system is “1,” there is a Fig. 2 shows the manner in which energy is dissipated sudden flow of current through R. Q=CLVdd is the charge during a switching transition in adiabatic logic circuits. supplied by the positive power supply rail for charging In contrast to conventional charging, the rate of CL to Vdd. Hence, the energy drawn from the power 2 switching transition in adiabatic circuits is decreased supply is Q ·Vdd=CLV dd [10]. If it is assumed that the because of the use of a time-varying voltage source energy drawn from the power supply is equal to that Fig. 2. (a) Model of adiabatic logic showing an ideal switch in Fig. 1. (a) A CMOS model showing an ideal switch in series series with resistance and two complementary voltage supply with resistor. (b) Charging. (c) Discharging. clocks. (b) Charging. (c) Discharging. JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.10, NO.1, MARCH, 2010 3 instead of a fixed voltage supply. Each voltage changes 1 X 0 with time, as demonstrated in Fig. 3. -1 1 Vφ, Vdd/2 The peak current in adiabatic circuits can be signi- 0 Vφ- -Vdd/2 -1 ficantly reduced by ensuring uniform charge transfers 1 0 over the entire available time. Hence, if Iˆ is considered V1 -1 1 as the average of the current flowing to CL, the overall V2 0 energy dissipation during the transition phase can be -1 1 reduced in proportion as follows [2]: V3 0 -1 1 2 V4 0 ⎛ C V ⎞ ⎛ RC ⎞ -1 ˆ 2 L dd L 2 (2) 0 1 2 3 4 5 E = I RT = ⎜ ⎟ RT = ⎜ ⎟C V . -8 diss p ⎜ ⎟ p ⎜ ⎟ L dd t [s] [×10 ] ⎝ T p ⎠ ⎝ T p ⎠ Fig. 4. (a) 1n1p split-level pulse adiabatic logic and (b) waveforms from the simulation of 4-inverter chain. Theoretically, during adiabatic charging, when the time for the driving voltage φ to change from 0 V to Vdd, conventional CMOS gate with two complementary split- Tp is long, power dissipation is nearly zero. level pulse voltage drivers. The peak voltage of each clock supplies Vdd/2 to the gates. When φ changes from HIGH to LOW in the pull- The two major drawbacks of this asymptotically down network, discharging via the nMOS transistor adiabatic logic are as follows: first, it cannot provide occurs. From Eq. (2), it is apparent that when power pipelining, and second, it is difficult to design the dissipation is minimized by decreasing the rate of voltage driver of this circuit [12]. switching transition, the system draws some of the Although constructing logic with asymptotically zero energy that is stored in the capacitors during a given energy loss [8] is feasible, schemes with partial (quasi) computation step and uses it in subsequent computations. energy recovery [7, 9, 11, 14] are preferred because The signal energy may be recycled instead of dissipated implementation becomes much simpler and area-efficient. as heat [2]. It must be noted that systems based on the By implementing 1n1p quasi adiabatic [7] logic, it is abovementioned theory of charge recovery are not possible to achieve quasi-adiabatic operations with necessarily reversible. conventional static CMOS gates under one-phase driving, as shown in the 1n1p quasi logic illustrated in Fig. 5. If the driver is varied sufficiently slowly, dissipation occurs only during the charging and discharging of the load capacitor. The power dissipation is minimum when the threshold voltages of nMOS and pMOS are equal in 2 Fig.
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