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Leakage Models for High Level Power Estimation

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Leakage Models for High Level Power Estimation Fakult¨at II – Informatik, Wirtschafts- und Rechtswissenschaften Department f¨urInformatik Leakage Models for High Level Power Estimation Dissertation zur Erlangung des Grades eines Doktors der Ingenieurwissenschaften von Dipl.-Phys. Domenik Helms Gutachter: Prof. Dr. Wolfgang Nebel Prof. Dr. Christian Piguet Tag der Disputation: 26.11.2009 ii Contents Preface v Abstract vii 1 Introduction 1 1.1 State of the art leakage modelling . 3 1.1.1 Motivation of my work . 3 1.1.2 Other groups . 4 1.1.3 Empirical RT bottom-up model . 5 1.1.4 Analytical RT top-down model . 6 1.2 Leakage sources in MOS transistors . 7 1.2.1 Drain-source leakage . 7 1.2.2 Gate leakage . 10 1.2.3 Junction leakage . 14 1.3 Leakage factors . 15 1.3.1 Variation parameters . 16 1.3.2 Variation dependence . 20 1.3.3 Thermal dependence . 21 1.3.4 Voltage dependence . 22 1.3.5 Data dependence . 24 1.4 Leakage optimisation methodologies . 25 1.4.1 Device level . 25 1.4.2 Gate level . 27 1.4.3 Techniques above gate level . 28 1.4.4 Leakage management . 30 1.4.5 Memory techniques . 35 2 Description of the model 39 2.1 Problem statement . 39 2.2 Parameter selection . 41 2.2.1 Global deterministic die-to-die variation . 41 2.2.2 Local statistical within-die variation . 42 iii Contents 2.2.3 Local deterministic within-die variation . 43 2.3 Simulation of reference transistors . 43 2.3.1 The initial model . 43 2.3.2 Introduction of the semi-analytical model . 45 2.3.3 Choice of the reference transistors . 47 2.4 Gate models . 49 2.4.1 Motivation . 49 2.4.2 Definition of the leakage of a gate . 52 2.4.3 Improved regression . 54 2.4.4 Conclusion . 56 2.5 RT level model . 57 2.5.1 Hard model generation . 57 2.5.2 Data and bitwidth abstraction . 59 2.5.3 Limitations and potential extensions . 61 2.6 Delay modelling . 63 2.6.1 Bottom up delay modelling . 63 2.6.2 Temperature dependent critical paths . 64 2.6.3 Statistical statical timing analysis . 65 2.7 Model splitting . 65 3 Parameter determination 69 3.1 Framework overview . 69 3.2 Variation engine . 70 3.2.1 Requirement specification . 71 3.2.2 Engine description . 71 3.2.3 Remarks . 73 3.3 Thermal model . 73 3.3.1 Electro-thermal coupling . 73 3.3.2 Related work . 74 3.3.3 Choice of a thermal model . 75 3.3.4 Final adaptations to the model . 76 3.4 VDD variation model . 77 3.4.1 IR drop modelling . 78 3.4.2 Iterative computation of leakage, temperature, and supply voltage . 80 3.5 Body and supply voltage optimisation . 80 3.5.1 Optimisation schemes . 82 3.5.2 Application examples . 86 3.6 Conclusion . 88 4 Simulation environment 91 iv Contents 4.1 Commercial transistor simulators . 91 4.1.1 Phillips PSP . 91 4.1.2 Synopsys Discovery AMS . 92 4.2 SPICE & BSIM . 93 4.2.1 Simulating in SPICE . 93 4.2.2 BSIM computation flow, version differences & capabilities . 95 4.2.3 Modelcards . 95 4.3 Gate construction by property analysis . 96 4.3.1 Transistor description . 96 4.3.2 Standard gate description . 97 4.4 Generation of RT components in SPICE . 100 5 Experimental assessment 103 5.1 Experimental set-up . 103 5.1.1 Reference transistor characterisation . 103 5.1.2 Gate model characterisation . 106 5.1.3 RT level model characterisation . 107 5.1.4 Conclusion . 107 5.2 Model representation and interface . 110 5.2.1 Transistor level . 110 5.2.2 Gate level . 112 5.2.3 RT level . 113 5.2.4 Overview . 113 5.3 Evaluation . 116 5.3.1 Transistor models . 116 5.3.2 Gate models . 117 5.3.3 RT component models . 124 5.3.4 RT level evaluation against SPICE . 126 5.3.5 Thermal model . 131 5.3.6 IR-drop model . 133 6 Conclusion 137 6.1 Outlook . 138 A Market overview 141 B Modelcard conversion 143 C Transistor model visualisation 145 v Contents vi Preface When working in the well established field of register transfer (RT) level modelling, one will soon find out, that doing RT level leakage estimation is by no means a simple modification of timing, area or dynamic power modelling. There are several factors, making leakage macro modelling a unique and completely new challenge: Leakage is barely state dependent from an RT level view. Instead, dynamic parameters highly influencing leakage are temperature ϑ (dominating subthreshold leakage) and supply voltage VDD (having highest influence on gate and pn-junction leakage). Process variations also are a new challenge for RT models. All leakage currents are highly dependent on variation of certain process parameters [1, 2]. Especially the high sensibility to magnitude and distribution of lowest level technological para- meters prohibits a simple function-like ’parameters-in estimation-out’ model interface. When being used for design space exploration, in-depth information like spread of.
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