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Digital Simulation of Superconductive Memory System Based on Hardware Description Language Modeling Hindawi Advances in Condensed Matter Physics Volume 2018, Article ID 2683723, 5 pages https://doi.org/10.1155/2018/2683723 Research Article Digital Simulation of Superconductive Memory System Based on Hardware Description Language Modeling S. Narendran and J. Selvakumar Department of Electronics & Communication Engineering, SRM Institute of Science and Technology, Chennai, India Correspondence should be addressed to S. Narendran; [email protected] Received 11 February 2018; Accepted 24 April 2018; Published 27 May 2018 Academic Editor: Sergei Sergeenkov Copyright © 2018 S. Narendran and J. Selvakumar. Tis is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. We have modeled a memory system using Josephson Junction to attain low power consumption using low input voltage compared to conventional Complementary Metal Oxide Semiconductor-Static Random Access Memory (CMOS-SRAM). We attained the low power by connecting a shared/common bit line and using a 1-bit memory cell. Trough our design we may attain 2.5–3.5 microwatts of power using lower input voltage of 0.6 millivolts. Comparative study has been made to fnd which memory system will attain low power consumption. Conventional SRAM techniques consume power in the range of milliwatts with the supply input in the range of 0-10 volts. Using HDL language, we made a memory logic design of RAM cells using Josephson Junction in FreeHDL sofware which is dedicated only for Josephson Junction based design. With use of XILINX, we have calculated the power consumption and equivalent Register Transfer Level (RTL) schematic is drawn. 1. Introduction evolved using SFQ and RSFQ (Rapid Single Flux Quantum) logic. For low power consumption and high performance com- In this paper, we developed a RAM using Reciprocal puting,SinglefuxQuantum(SFQ)iswidelyused,which Quantum Logic at cryogenic temperature. Te proposed is an alternate principle for Complementary Metal Oxide memory system is of static nature which is composed of Semiconductor (CMOS) technology. Many SFQ techniques decoder and sense amplifcation circuit. In Section 2, we are devolved to attain high speed and low power consump- have discussed convention SRAM using 6T and 8T transistor. tion. Various approaches have been developed on Josephson, We have designed a RAM using RQL which is discussed in CMOS hybrid memory cell, which is high density CMOS Section 3. Comparative study and results are discussed in memory array and low power Single fux Quantum (SFQ) Section 4 and we have concluded our remarks in Section 5. logic [1–4]. In addition, the hybrid model must work at cryogenic temperature. Te 64kb hybrid static CMOS RAM has been discussed in [5]; the estimated power consumption 2. Conventional CMOS Memory Cell Design of this hybrid logic is 20 mW for read and 53.7 mW for write operation. In [6], further reduction on power consumption Te most commonly used control signals in CMOS RAM is achieved by introducing a binary tree decoder and with cell are Write Enable (WE), Output Enable (OE), and Chip help of data driver, they attain 54% and 8% of write and read Select (CS). Conventional 6T CMOS memory cell consists operation. We attain large scale high speed memory using of four NMOS and two PMOS counts with separate bit line cryogenic experience to match the ultra-speed processor andwordline.Teaveragepowerconsumptionof6TSRAM 2 in the same cryogenic temperature. Many developments cell is 46mW and area required is 5�m . For 8T transistor, and demonstrations of hybrid memory logic have been the dynamic power consumption will be 0.035�W. Fo r b o t h 2 Advances in Condensed Matter Physics Figure 1: Conventional 6T CMOS-SRAM cell [7]. Figure 2: Conventional 8T SRAM CMOS cell. SRAM memory cell, the voltage at both bit lines is precharged excessive access of capacitance buses, low-voltage low power before the read operation starts. Consider logic 0 at transistor cell designs are developed in CMOS families. With the help M3 and logic 1 at M4; the particular memory can be selected of shared bit line cell confguration of SRAM cell libraries, using word line and bit line correspondingly according to we can achieve ultra-low power dissipation. MUX based dischargeofcurrentfowsfromthesupplyvoltage.Forwrite charged sense amplifers are used for read operation. For operation, the bit line (BL) will complement its signal from write operation, a bit line precharged technique is used to logic 0 to logic 1 and vice versa. Te cross coupled inverter attain high speed write operation [8]. structure will generate high gain to interchange the voltages With the help of low-voltage low power (LVLP) tech- passing through the transistor. nique, the normalized form of RAM cell design is made By use of NMOS and PMOS logic, corresponding 6T and by replacing MOS technology with Josephson Junction (JJ) 8T SRAM cells are formed in Figures 1 and 2. For 6T SRAM technology.Below,Figure3showsthestructureofRAM cell, there are four NMOS and two PMOS are used. And, for architecture by replacing CMOS cell libraries with Reciprocal 8T SRAM CMOS cell it requires six NMOS and two PMOS Quantum Logic structure. logic structures. Furthermore, diferent SRAM architectures Reciprocal Quantum Logic (RQL) is one of the high speed have been developed using 7T and 9T CMOS cells. low power consumption superconductive logics. RQL circuits are designed using alternating current phenomena rather all 3. Superconductive Memory Cell CMOS or any digital circuits designed using direct current as input. In [9–11], RQL circuits are designed using the basic In SRAM cell design, they are incorporable in terms of gates of RQL as ANDOR, ANOTB, Latch circuit, and XOR power dissipation due to high capacitance buses. Due to logic gates. In our design we also used the basic gates to form Advances in Condensed Matter Physics 3 Table 1: Comparison of power consumption. Technology RQL based RAM 6T 8T Hybrid JJ- CMOS Starc JJ – CMOS Hybrid Power for Write (W) 3.45 �W46�W37.1�W 27.62mW 11.43mW Power for Read (W) 2.6 �W 44.26�W39.9�W 21.25mW 9.18mW B – Address inputs Decoder Memory Array BL BL WL X Data A – Address X inputs Output Circuit Decoder Sense amplifer Sense amplifer WL Cell Array X X Figure 3: Structure of a memory system. RAM logic to consume less power comparative to the older 5. Conclusion techniques. Other superconducting logics include RSFQ, AQFP, and eSFQ, which are successor of convention CMOS We have designed a RAM cell using RQL superconducting � logic design. Tose logics have their own pros and cons. By logic. We achieved the power consumption of 2.6 Wfor � using RSFQ [12–14], many articles have been published for read operation and 3.45 W for write operation, which is very thedesignofRAMandprocessorswhichcanwork25%to much less compared to other technologies. We designed the 35% more in performance comparative to the CMOS RAM RAM using HDL language and analysed the power using cells. XILINXsofware.SincewehaveusedtheReciprocalQuan- tum Logic (RQL), we can further implement this technique 4. Simulation Results of RQL Based RAM in real time application for high speed processor to support high speed applications. Our future work will be designing With the help of Very High Speed Integrated Circuit (VHSIC) aprocessorbasedonRQLandimplementingthisRAM Hardware Description Language (VHDL), the coding of technique to that processor. RAM cell is designed and corresponding results are found out. By using XILINX sofware and FreeHDL sofware, we Data Availability have generated the RTL schematic view of our RAM design. Figure 4 shows the Register Transfer Level (RTL) schematic Tedatausedtosupportthefndingsofthisstudyare view of RAM cell using RQL. available from the corresponding author upon request. We have compared our result with previously developed RAMcelllike6T,8T,HybridJosephsonJunction-(JJ-)CMOS Conflicts of Interest for 64Kb, and hybrid binary decoder of JJ-CMOS. We have presenteditinTable1.FortheresultsobtainedinTable1,we Te authors declare that there are no conficts of interest made a chart comparison and it is shown in Figure 5. regarding the publication of this paper 4 Advances in Condensed Matter Physics rql_logic:1 and4b4 and2b1 or2b1 inv fdce Mram_rom_data1 Mmux_BUS_0001_GND_4_o_mux_57_OUT1 Mmux_Data_Out1 I3 I1 I1 O O IO Result(7:0) I2 I0 I0 DQ addrA(3:0) doA(7:0) Data0(7:0) Result(7:0) Data0(7:0) Data_Out(7:0) O _n0198_inv1 CE diA(7:0) Data1(7:0) Data1(7:0) I1 _n01971 _n01981 A(7:0) I0 C weA Sel(0) Sel(0) GND_4_o_Decoder_3_OUT<0><3>1 CLR Mram_rom_data1 Mmux_BUS_0001_GND_4_o_mux_57_OUT1 Mmux_Data_Out1 Data_In(7:0) CLK RESET Mcompar_A[7]_GND_4_o_LessTan_2_o1 and3 or2b1 inv fdce Mmux_GND_4_o_ram_data[15][7]_wide_mux_55_OUT1 Mcompar_GND_4_o_A[7]_LessTan_53_o1 gnd I2 I1 G O IO DataA(7:0) AGB I1 O I0 DQ Data0(7:0) Result(7:0) DataA(7:0) AGB DataB(7:0) I0 CE Data1(7:0) DataB(7:0) XST_GND Write_EN_A[7]_AND_3_o1 C Data2(7:0) Mcompar_A[7]_GND_4_o_LessTan_2_o1 Data3(7:0) Mcompar_GND_4_o_A[7]_LessTan_53_o1 CLR Data4(7:0) inv or2b1 Data5(7:0) I1 IO O Data6(7:0) I0 and2b1 _n0146_inv1 Data7(7:0) I1 _n01461 Data8(7:0) O fdce I0 Data9(7:0) DQ Data10(7:0) CE Data11(7:0) C inv Data12(7:0) or2b1 IO CLR Data13(7:0) and2b1 I1 Data14(7:0) I1 O O I0 _n0154_inv1 Data15(7:0) I0 _n01541 Sel(0:3) _n01451 Mmux_GND_4_o_ram_data[15][7]_wide_mux_55_OUT1 Write_EN and4b3 and2b1 or2b1 inv fdce I3 Mcompar_GND_4_o_A[7]_LessTan_54_o1 I1 I1 IO I2 O O DQ DataA(7:0) AGB O
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