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VLSI – Design of Integrated Circuits Prof. Dr. Dr. H.C. Mult. M. Glesner 9 VLSI { Design of Integrated Circuits Prof. Dr. Dr. h.c. mult. M. Glesner Dipl.-Ing. M.-D. Doan Dipl.-Inf. M. Gasteier Dipl.-Ing. H. Genther Dipl.-Ing. T. Hollstein Dipl.-Ing. P. P¨ochm¨uller Dr.-Ing. N. Wehn Dipl.-Ing. P. Windirsch Darmstadt University of Technology Contents Contents List of Figures 0-12 List of Tables 0-29 1 Basics of CMOS Circuit Design 1-1 1.1 pn Junction Properties . 1-1 1.1.1 pn Junction Space Charge Area and Electric Field . 1-1 1.1.2 pn Junction Built-in Potential . 1-2 1.1.3 pn Junction Depletion Width . 1-3 1.1.4 pn Junction with External Voltage . 1-4 1.1.5 pn Junction Capacitance . 1-5 1.1.6 pn Junction Current Flow . 1-5 1.2 MOS Transistor Theory . 1-6 1.2.1 MOSFET Structure . 1-6 1.2.2 MOS Capacitor and Threshold Voltage . 1-7 1.2.3 MOSFET Operation Modes . 1-13 1.2.4 MOSFET current characteristic . 1-16 1.2.5 Biased MOSFET Current Equations . 1-21 1.2.6 Measurement of device parameters . 1-22 1.2.7 The Complete MOSFET GCA Analysis . 1-23 1.2.8 Depletion mode n{channel MOSFET . 1-24 1.2.9 p{channel MOSFET . 1-28 1.2.10 Conclusions . 1-29 1.2.11 Modelling the MOS Transistor for Circuit simulation . 1-30 1.3 DC Characteristics of MOS Inverters . 1-32 1.3.1 Basic Inverter characteristics . 1-33 1.3.2 Inverter with Linear Resistor Load . 1-38 Design Darmstadt University of Technology VLSI Course 0-1 Institute of Microelectronic Systems 0 Contents 1.3.3 Inverter Design: Resistor Model . 1-42 1.3.4 Inverter with Saturated Enhancement Load . 1-44 1.3.5 Inverter with Nonsaturated Enhancement Load . 1-45 1.3.6 Inverter with Depletion mode MOSFET Load . 1-46 1.3.7 CMOS inverter . 1-51 1.4 Switching of MOS Inverters . 1-54 1.4.1 The output High-to-Low Time tHL . 1-54 1.4.2 Rise Time tLH . 1-54 1.4.3 NMOS Propagation Delay Time . 1-56 1.4.4 CMOS Inverter Transient Response . 1-57 1.4.5 Propagation Delay Time tp of CMOS Inverters . 1-57 1.4.6 Power-Delay-Product (PDP) . 1-65 1.4.7 MOSFET Capacitances . 1-70 1.4.8 Inverter Output Capacitance . 1-75 1.4.9 Scaled Inverter Performance . 1-78 1.5 CMOS Technology . 1-79 1.5.1 CMOS Process Flow . 1-79 1.5.2 The Latch-Up Effect . 1-80 2 Static CMOS Logic Design and Combinational Circuits 2-1 2.1 Overview: Combinational Logic . 2-1 2.2 Complex nMOS Logic . 2-5 2.2.1 nMOS NOR Gates . 2-5 2.2.2 nMOS NAND Gates . 2-6 2.2.3 nMOS Complex Gates . 2-7 2.3 Complex Static CMOS Logic . 2-10 2.3.1 CMOS NAND and NOR Gates . 2-10 2.3.2 Static CMOS Logic Design . 2-13 2.3.3 Pseudo nMOS Logic . 2-23 2.4 Passtransistor and Transmission Gate Logic . 2-24 2.4.1 Passtransistor Charging Characteristics . 2-25 2.4.2 Passtransistor Discharging Characteristics . 2-26 2.4.3 CMOS Transmission Gates . 2-28 3 Synchronous MOS Logic 3-1 3.1 Clocking . 3-1 Design Darmstadt University of Technology VLSI Course 0-2 Institute of Microelectronic Systems 0 Contents 3.1.1 Single and Multiple Clock Signals . 3-2 3.2 Clocked Static Logic . 3-5 3.3 Charge Sharing . 3-10 3.4 Dynamic Logic . 3-12 3.4.1 Dynamic nMOS Inverter . 3-12 3.4.2 Dynamic pMOS Inverter . 3-15 3.4.3 Dynamic CMOS Properties and Conditions . 3-15 3.4.4 Complex Logic . 3-16 3.4.5 Dynamic Cascades . 3-17 3.5 Domino CMOS Logic . 3-18 3.5.1 Domino Logic Properties . 3-22 3.5.2 Analysis . 3-23 3.5.3 Charge Leakage and Charge Sharing . 3-24 3.6 NORA Logic . 3-26 3.6.1 NORA Properties . 3-26 3.6.2 The Signal Race Problem . 3-26 3.6.3 NORA Structuring . 3-28 3.7 Memory Structures . 3-31 3.7.1 Principle of CMOS Information Storage . 3-31 3.7.2 Dynamic Flip-Flops: Pseudo 2-Phase Clocking . 3-33 3.7.3 Pseudo 2-Phase Memory Structures . 3-34 3.7.4 Dynamic Flip-Flop with reduced Transistor Count and Clock Connection 3-37 3.7.5 Dynamic D-Latches . 3-38 3.7.6 Pseudo 2-Phase Logic Structures . 3-39 3.7.7 Pseudo 2-Phase Logic Structures: Domino Logic . 3-40 3.7.8 2-Phase Memory Structures: Skew Reduction . 3-41 3.7.9 2-Phase Memory Structures: Chain Latch . 3-42 3.7.10 2-Phase Memory Structures: Static Flip-Flops . 3-43 3.7.11 2-Phase Memory Structures: Static D Flip-Flops . 3-44 3.7.12 Static D Flip-Flop with Set and Reset . 3-47 4 Performance 4-1 4.1 Signaldelay . 4-1 4.1.1 Resistance Estimation . 4-1 4.1.2 Capacitance Estimation . 4-2 Design Darmstadt University of Technology VLSI Course 0-3 Institute of Microelectronic Systems 0 Contents 4.1.3 RC-line model . 4-6 4.2 CMOS Gate Transistor Sizing . 4-8 4.3 Power Dissipation . 4-8 4.3.1 Static power dissipation . 4-9 4.3.2 Dynamic power dissipation: . 4-10 4.3.3 Power delay product . 4-11 4.4 Scaling . 4-15 4.4.1 Scaling principles . 4-15 4.4.2 Interconnect layer scaling . 4-17 4.5 Power and Clock Distribution . 4-18 4.5.1 Power distribution . 4-18 4.5.2 Clock distribution . 4-19 4.5.3 Clock and Timing Circles . 4-20 4.5.4 Clock Generation Circuits . 4-21 4.5.5 Clock Drivers and Distribution Techniques . 4-22 4.6 Input Protection Circuits . 4-23 4.7 Static Gate Sizing . 4-25 4.8 Off-Chip Driver Circuits . 4-29 4.8.1 Basic Off-Chip Driver Design . 4-29 4.8.2 Tri-State and Bidirectional I/O . 4-30 5 CMOS Process and Layout Design of Integrated Circuits 5-1 5.1 Processing Steps . 5-1 5.1.1 Wafer Processing . 5-1 5.1.2 The n-Well CMOS Process . 5-1 5.1.3 The p-Well CMOS Process . 5-7 5.1.4 The Twin-Tub Process . 5-7 5.1.5 Isolation . ..
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