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Stuck-At Fault As a Logic Fault

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Stuck-At Fault As a Logic Fault Stuck-At Fault: Stuck-At Fault A Fault Model for the next Millennium? “I tell you, I get no respect!” -Rodney Dangerfield, Comedian Janak H. Patel Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign “The news of my death are highly exaggerated” -Mark Twain, Author © 2005 Janak H. Patel 2 Stuck-At Fault a Defect Model? Stuck-At Fault as a Logic Fault You can call it - z Stuck-at Fault is a Functional Fault on a Boolean Abstract (Logic) Function Implementation Logical z It is not a Physical Defect Model Boolean Stuck-at 1 does not mean line is shorted to VDD Functional Stuck-at 0 does not mean line is grounded! Symbolic z It is an abstract fault model or Behavioral …... Fault Model A logic stuck-at 1 means when the line is applied a logic 0, it produces a logical error But don’t call it a Defect Model! A logic error means 0 becomes 1 or vice versa 3 4 Propagate Error To Fault Excitation Primary Output Y 1 1 G ERROR A G s - a - 0 A 0 1 x X 1/0 D 1 D F ERROR F 0 Y 0 C 1/0 C Y 0 0 0 E E B H B H Test Vector A,B,C = 1,0,0 detects fault G s-a-0 Activates the fault s-a-0 on line G by applying a logic value 1 in line G 5 6 Unmodeled Defect Detection Defect Sites z Internal to a Logic Gate or Cell Other Logic Transistor Defects – Stuck-On, Stuck-Open, Leakage, Shorts between treminals ERROR Defect G ERROR z External to a Gate or Cell Interconnect Defects – Shorts and Opens D 1 F 0 Y ERROR C 0 0 0 E B H G I 7 8 Defects in Physical Cells Fault Modeling z Physical z Electrical Physical Cells such as NAND, NOR, XNOR, AOI, OAI, MUX2, etc. A B For primitive gates such as NOT, NAND and NOR, VDD stuck-at tests are derived for faults on the pins. B For complex cells such as XOR, XNOR, AOI, OAI, Z A Z and MUX2 etc, Stuck-at Tests are assumed to be derived on faults on gate equivalent models. GND How good are these test vectors for a variety of z Logical defects? z Do we need additional vectors? Z is Stuck-At-0 A z Do we need transistor level details? B X Z 9 10 Non-Logical Values Non-Logical Values 1 open B 1 B ? 0 Floating Node - Z A Indeterminate Value - N 0 A open 11 12 Defect Detection in a NAND Gate Two-Input NAND Gate z For a 2-input NAND gate, the complete stuck-at A test set is: AB = 01, 10 and 11 F z With a defect in the NAND cell, the gate may B produce any combinations of 0, 1, N, Z N is an indeterminate logic value (active, driven) AB F a/0 b/0 a/1 b/1 F5 F6 F7 F8 F9 … F256 Z is a floating node with unknown charge (passive) 00 1 1 1 1 1 1 1 Z … 0 … Z z Each of 4 possible input vectors can produce any of the 4 possible output values 01 1 1 1 0 1 Z 1 0 1 Z 256 possible defective behaviors for 2-input NAND 10 1 1 1 1 0 1 1 Z 1 Z Infinitely many delay and current behaviors 11 0 1 1 1 1 0 N 0 0 Z z Is the stuck-at test set 01, 10 and 11 sufficient? Fault Dictionary 13 14 Defect Characterization Vector 00 and 2-input NAND z Inductive Contamination Analysis (ICA) Pseudo Theorem: J. Khare, W. Malay and N. Tiday, VLSI Test Symp. In a 2-input NAND CMOS cell, there does not exist a 1996, pp. 407-413 real physical defect that requires test vector 00 for “Inductive Fault Analysis (IFA) is inadequate for three its exposure. dimensional defects in multi-layer cells” Proof: Experiment on 2-input NAND cell with 1000 If such a defect existed, it would make the gate particle contamination simulations. Assumed 84 “more functional than a NAND gate.” major process steps, 2-metal C-MOS. Reported 22 different fault behaviors in the paper z Stuck-at test set (01,10,11) was “sufficient” for all behaviors (my interpretation not theirs) 15 16 Two-Input NAND Gate Stuck-at tests for other Cells A z It can be shown that for all simple gates and F complex gates with fan-out free logic, stuck-at B test for pin faults is sufficient to expose any defect inside the Cell A⊕B Simple Gates, NAND, NOR, NOT AB F a/0 b/0 a/1 b/1 F5 F6 F7 F8 F9 Complex fan-out free Gates, AOI, OAI 00 1 1 1 1 1 1 1 Z … 0 Even functions such as: [(A+B)(C+D)+E]INVERT 01 1 1 1 0 1 Z 1 0 1 z Pin fault stuck-at tests are not adequate for 10 1 1 1 1 0 1 1 Z 1 complex gates with internal fanout-reconvergence 11 0 1 1 1 1 0 N 0 0 XOR, XNOR, MUX Fault Dictionary 17 18 Multiplexer Expansion What about N and Z values? z Some of the defects within a cell produce A 0 2-to-1 Y indeterminate logic N or floating node Z values for 1 MUX B Testing for Pin Faults some of the stuck-at vectors. on A,B,C and Y will not If a clean logic error (0-to-1, or 1-to-0) is possible, C guarantee detection of internal faults on a stuck-at test vector will expose it. D,E,F,G and H. That means N and Z values cannot be avoided by A G using test vectors other than stuck-at vectors. F D Y If a clean logic error is not possible, Stuck-at E vectors are sufficient to “expose” the defect by C H B changing a correct logic value to either N or Z. 19 20 Defects External to a Gate Shorts z Opens All opens external to a gate are detected by a stuck-at fault test set Input to Input Short z Shorts Input to Output Short Input-to-Input Shorts on the same Gate Input-to-Output Shorts on the same Gate Output-to-Output Shorts on different Gates Output to Output Short 21 22 Input to Output Short Input-to-Output Bridging Faults z Validation of Stuck-at Fault Test Set Coverage z In a simple CMOS gate, if the short causes an Circuits with Complex Gates Error then Input value is forced upon the output - Vierhaus, Meyer and Glaser, ITC-93 All Bridging Faults on the Input and Output on z This is also true for complex CMOS gates such as the same Gate And-Or-Invert (AOI) and Or-And-Invert (OAI) - Fault Simulation with E-PROOFS Cusey, M.S. Thesis, Illinois 1993 Total % Faults Detected z Test Vectors for Input and Output Stuck-at Faults Circuit Vectors Faults 0k Ω 1k Ω 2k Ω cover Input-to-Output Shorts Experiments Confirm this C432 100 371 100% 100% 43% 0 C499 190 274 100% 100% 97% 1 0 C880 128 336 94% 90% 70% 23 24 Logic Model for a Short Shorts and Stuck-at Tests 0 A A 1 Test for G stuck-at 0 0 G G B B 1 C C H H D 1 D ? FAULT-FREE FAULTY FAULT MODEL z Assume H dominates G with the Bridge present G,H = 0,1 G,H = 0,0 or H s-a-0 when G=0 z Test for G stuck-at 0 has no control over node H G,H = 1,1 G s-a-1 when H=1 z Probability that H has the correct logic value to excite G,H = 1,0 G,H = 0,0 or G s-a-0 when H=0 the Bridge is 0.5 G,H = 1,1 H s-a-1 when G=1 25 26 Probability of Detection Repeated Detections z The four stuck-at faults on nodes G and H require z Example - ISCAS89 fullscan circuit S38417 a minimum of two test vectors 99 test vectors, 31,015 faults detected z Each test vector has a probability of Bridge Number of Number of Excitation of 1/2 Repetitions Faults Probability that two test vectors miss the excitation 1 3,411 of the bridge is 1/4 2 1,710 3 1,262 Lower bound on expected bridge coverage is 75% 4 1,043 For most stuck-at test sets, a node gets tested 5 861 many more times than 2 6 925 7 821 8 834 9 808 >10 19,340 27 28 Probability of Bridge Detection Bridge Coverage with SSF Test Set z Assume the stuck-at test set detects each node n Simulation of extracted bridges with Stuck-at Test times Sets using very accurate electrical level simulator Probability of Bridge being detected is (1 - 1/2n) (EPROOFS, Greenstein, Patel, ICCAD 1992) z For example, let us say each stuck-at fault gets shows a very high coverage in ISCAS circuits. detected 5 times. Output to Output Bridges have comparable That means each node gets detected 10 times. coverage to a stuck-at fault coverage The probability of Bridge detection is 99.9% Input to Input Bridges have lower coverage z Caveat: The Bridge must cause a Detectable error.
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