University of Tennessee, Knoxville TRACE: Tennessee Research and Creative Exchange Masters Theses Graduate School 12-2013 A SiGe BiCMOS LVDS Driver for Space-Borne Applications Matthew Ian Laurence University of Tennessee - Knoxville, [email protected] Follow this and additional works at: https://trace.tennessee.edu/utk_gradthes Part of the Electrical and Electronics Commons, and the Electronic Devices and Semiconductor Manufacturing Commons Recommended Citation Laurence, Matthew Ian, "A SiGe BiCMOS LVDS Driver for Space-Borne Applications. " Master's Thesis, University of Tennessee, 2013. https://trace.tennessee.edu/utk_gradthes/2617 This Thesis is brought to you for free and open access by the Graduate School at TRACE: Tennessee Research and Creative Exchange. It has been accepted for inclusion in Masters Theses by an authorized administrator of TRACE: Tennessee Research and Creative Exchange. For more information, please contact [email protected]. To the Graduate Council: I am submitting herewith a thesis written by Matthew Ian Laurence entitled "A SiGe BiCMOS LVDS Driver for Space-Borne Applications." I have examined the final electronic copy of this thesis for form and content and recommend that it be accepted in partial fulfillment of the requirements for the degree of Master of Science, with a major in Electrical Engineering. Benjamin J. Blalock, Major Professor We have read this thesis and recommend its acceptance: Chuck Britton, Syed Islam Accepted for the Council: Carolyn R. Hodges Vice Provost and Dean of the Graduate School (Original signatures are on file with official studentecor r ds.) A SiGe BiCMOS LVDS Driver for Space-Borne Applications A Thesis Presented for the Master of Science Degree The University of Tennessee, Knoxville Matthew Ian Laurence December 2013 DEDICATION The following thesis is dedicated to my parents who always supported my childhood dreams of becoming a man of science. ii ACKNOWLEDGEMENTS I would first like to thank Dr. Blalock for giving me the wonderful opportunity to study integrated circuit design as a member of the ICASL group and for his role as my mentor. He has provided me with a great amount of support and knowledge throughout my studies at UT both as a professor and colleague. He is an inspiration and role model to better myself as an engineer. I would also like to thank Dr. Chuck Britton for taking the time to help in the design of my first integrated circuit and for all of the helpful knowledge he has imparted on me. In addition, I would like to thank Dr. Islam for being a member of my thesis committee and for being a truly great professor through my undergraduate and graduate studies. Finally, I would like to thank all of the members of ICASL for their support and friendship over the past two and a half years. iii ABSTRACT When designing an integrated circuit for use during an interstellar mission, certain precautions must be made. The electronics on any off-earth mission will be exposed to wide temperature swings and harmful radiation due to being outside of the Earth’s protective ionosphere. It is crucial that any data path present be immune to these detrimental effects. The introduction of galactic radiation can not only cause the onboard electronics to fail due to device degradation and single event latchup but can also lead to background radiation being coupled into the signal path as unwanted noise, degrading the signal to noise ratio. Unwanted noise can cause total failure by increasing the noise level thus decreasing the signal to noise ratio below one or by causing errors such as single event upsets. The wide temperature swing can cause device degradation and eventually failure. This issue is commonly mitigated by the introduction of an environment chamber but such an enclosure adds unnecessary mass and typically requires a large amount of current to effectively keep the electronics in an Earth-like temperature. The large current implies high power dissipation which is an unnecessary strain on the battery and can shorten the lifetime of a mission where every kilowatt-hour is crucial to success. The solution to these two non-trivial obstacles is to design an electronic circuit such that it can operate in a wide range of temperatures and can withstand the galactic radiation that it will inevitably encounter during its mission’s lifetime. The following thesis will document the design, simulation, and testing of a SiGe BiCMOS low voltage differential signal driver for space borne applications. iv TABLE OF CONTENTS CHAPTER 1: Introduction .............................................................................................. 1 1.1 Motivation ................................................................................................................. 1 1.2 Thesis Scope and Organization ................................................................................. 3 CHAPTER 2: Background............................................................................................... 5 2.1 Output Driver Technologies ..................................................................................... 5 2.1.1 Early Digital Logic ............................................................................................ 5 2.1.2 Transistor-Transistor Logic ............................................................................... 8 2.1.3 Emitter-Coupled Logic .................................................................................... 10 2.1.4 Complementary Metal-Oxide-Semiconductor ................................................. 13 2.1.5 Low Voltage Differential Signaling................................................................. 20 2.2 Radiation and Temperature Effects ........................................................................ 24 2.3 Literature Review.................................................................................................... 27 CHAPTER 3: Methodology ........................................................................................... 29 3.1 IBM 7WL PDK ....................................................................................................... 29 3.2 Circuit Design ......................................................................................................... 29 3.2.1 Basic Design .................................................................................................... 30 3.2.2 Radiation Tolerant Design ............................................................................... 35 3.2.3 Final Design ..................................................................................................... 38 3.3 Final Design Simulations ........................................................................................ 42 3.3.1 Frequency Sweep ............................................................................................. 42 3.3.2 Temperature Sweep ......................................................................................... 44 3.3.3 Voltage Sweep ................................................................................................. 46 CHAPTER 4: Results and Discussion ........................................................................... 49 4.1 Test Results ............................................................................................................. 51 4.1.1 Temperature and Frequency Sweep at 3.3 V Power Supply ........................... 51 4.1.2 Temperature and Frequency Sweep at 3.0 V Power Supply ........................... 55 4.1.3 Temperature and Frequency Sweep at 3.6 V Power Supply ........................... 60 CHAPTER 5: Conclusions and Recommendations ..................................................... 65 v LIST OF REFERENCES ............................................................................................... 67 Appendix .......................................................................................................................... 70 Vita ................................................................................................................................... 73 vi LIST OF TABLES Table 1 LVDS Parameters [6]........................................................................................... 23 vii LIST OF FIGURES Figure 1 WMAP Image [1] ................................................................................................. 2 Figure 2 RTL Inverter ......................................................................................................... 7 Figure 3 DTL OR Gate ....................................................................................................... 7 Figure 4 DTL NAND Gate ................................................................................................. 9 Figure 5 TTL NAND Gate with Totem Pole Output Stage ................................................ 9 Figure 6 Emitter-Coupled Pair .......................................................................................... 12 Figure 7 ECL OR-NOR Gate ............................................................................................ 12 Figure 8 CMOS Structure ................................................................................................. 14 Figure 9 BJT Structure ...................................................................................................... 14 Figure 10 NMOS Logic Inverter....................................................................................... 17 Figure 11 CMOS Inverter ................................................................................................