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ECE4740: Digital VLSI Design
Lecture 15: Dynamic logic
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Recap Pseudo NMOS and pass -transistor logic
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Ratio’ed logic
VDD VDD VDD
Resistive Depletion V PMOS Load RL Load T < 0 Load VSS F F F In 1 In 1 In 1 In 2 PDN In 2 PDN In 2 PDN In 3 In 3 In 3
VSS VSS VSS (a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
• Goal: Reduce # of transistors over CMOS • Ratio’ed = functionality depends on ratios! • Static power When exactly? 544 Image taken from: CMOS VLSI Design: A Circuits and Systems Perspective by Weste, Harris
Improving loads is critical
VDD VDD
M1 M2
Out Out
!A A B PDN1 PDN2 !B
VSS VSS • Differential cascode voltage switch logic (DCVSL) • No static power consumption but more routing • Gates keep state why could this be useful? 545 Image taken from: CMOS VLSI Design: A Circuits and Systems Perspective by Weste, Harris
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Pass transistor logic: AND gate
B A B F=A* B A B 0 0 0 F=A*B 0 1 0 0 1 0 0 1 1 1
• Requires 4 logic gates (needs an inverter) • CMOS logic would require 6 logic gates • The gate has no rail-to-rail swing
• Non-inverting logic 546
Key issue: static power
In = V DD
M2 Vx = V DD -VTn A = V DD
M1
• Pass transistor suffers from body effect
• M2 may be weakly conducting forming a path from V DD to GND • Can fix with level-restorer transistor
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We can go faster Dynamic logic
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Do not confuse with sequential logic
combinational sequential
In sequential or Out Combinationalsequential Combinational In Out static CMOS logicLogic circuit Logic Circuit logicCircuit circuit
stateState CLK CLK • Sequential logic circuit considers input history • Dynamic logic may also have a clock input!
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What is dynamic CMOS?
• Static CMOS circuits: – Output is (except during switching) connected
to GND or V DD via low-resistance path – N-input gate requires at least 2N transistors • Dynamic circuits: – Circuits rely on temporary storage of signal values on capacitance of high impedance nodes – N-input gate requires (at least) N+2 transistors
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Principle of dynamic gate
precharge transistor CLK Mp CLK M on Out p 1 Out In 1 CL
In 2 PDN A In 3 C CLK Me evaluation B transistor CLK M off • Two-phase operation: e – Precharge CLK=0 precharge – Evaluation CLK=1
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Principle of dynamic gate (cont’d)
CLK Mp
Out CLK Mp off In C Out 1 L !(AB+C) In 2 PDN A In 3 C CLK Me B
CLK M on • Two-phase operation: e – Precharge CLK=0 evaluation – Evaluation CLK=1
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Conditions on output
• Once output of dynamic gate is discharged, it cannot be charged again until next cycle • Inputs to gate can make at most one transition during evaluation: no glitches • Output can be in high-impedance state during and after evaluation (PDN off)
– State is temporarily stored on C L
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Why not this?
• Clock signal needs to have higher voltage to
enable evaluation CLK Mp transistor slower Out CLK Me CL • Body effect increases V T In even further 1 In 2 PDN • Worse clock feed- In 3 through I will talk about that today
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Properties of dynamic gates
• Logic function implemented by PDN only – # of transistors is N+2 (vs. 2N for CMOS) – Smaller area than static CMOS
• Full swing outputs (V OL =GND, V OH =V DD ) • Unratio’ed*: sizing only for performance • No cross-over current: all current provided
by PDN goes into discharging C L
*ignoring parasitic effects 555
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Properties of dynamic gates (cont’d)
• Faster switching speeds – Reduced load capacitance due to lower number of transistors per gate lower logical effort
– Reduced C L due to smaller fan-out • Power dissipation should be better? – Consumes only dynamic power, no cross-over (or short circuit power)
– Lower C L: Cint and Cext FREE LUNCH!? – No glitching
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What are the disadvantages?
• Power usually much higher than CMOS – Higher transition probabilities (due to precharge) – Extra load on clock signal – Clock signal switches every cycle – Every gate needs a clock input • PDN starts to work as soon as input signals
exceed VTn : V M=V IH =V IL =VTn
– Low noise margin (NM L) • Needs a precharge/evaluate clock
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Dynamic behavior
CLK M p 2.5 Out evaluate In 1 1.5 precharge time In 2 determined by
width of Mp In 3 0.5 In & CLK In 4 Out precharge CLK -0.5 0 0.5 1 Time, ns
#Trns VOH VOL VM NM H NM L tpHL tpLH tpre
6 2.5V 0V VTn 2.5-VTn VTn 110ps 0ns 83ps
558 Image taken from: Digital Integrated Circuits (2nd Edition) by Rabaey, Chandrakasan, Nikolic
Gate parameters are time dependent
• Amount of output voltage drop depends on – Input voltage – Available evaluation time (short is better)
CLK 2.5
Vout (V G=0.45) 1.5 Vout (V G=0.55) Vout (V G=0.5)
Voltage (V) Voltage 0.5 VG
-0.5 could be an 0 20 40 60 80 100 input glitch Time (ns) 559
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Power consumption
• Power only dissipated when previous Out=0 CLK Mp Out
CL In 1 • Switching activity can be PDN In 2 higher than static CMOS In 3 – Activity does not depend CLK Me on previous state – Activity depends on signal probabilities only
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Dynamic logic Issues and solutions
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Issue 1: charge leakage
PMOS leakage mitigates issue a bit CLK evaluate
Clk Mp Out
A CL VOut
Clk Me precharge
load capacitance • Reverse-biased diode discharges • Subthreshold current (dominant) • Limits minimum clock frequency 562 Image taken from: Digital Integrated Circuits (2nd Edition) by Rabaey, Chandrakasan, Nikolic
Issue 1: charge leakage (cont’d)
• Output settles at voltage determined by resistive divider of PMOS & NMOS
2.5 intermediate Out voltage 1.5 Voltage Voltage (V) 0.5 CLK leakage limits min. clock rate -0.5 to a few kHz 0 20 40 Time (ms) 563
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Solution to charge leakage
keeper • During precharge
Clk M Mkp p 0 – Out=V DD and !Out=GND A 1 Out CL B • During evaluation off requires inverter Clk Me – PDN off: keeper helps to retain charge
– PDN on: if Mkp is similar idea as for weak, PDN wins pass-transistor logic ratio’ed logic! 564
Issue 2: charge sharing
• Charge stored originally on
CLK Mp CL is redistributed (shared) Out over C L and C A A CL • Leads to static power B=0 CA consumption by CLK M e CB downstream gates and possible malfunction • When Vout = -VDD (C A/(C A+C L)) drop in Vout is below the threshold of driving gate malfunction “capacitive voltage divider” 565
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Charge sharing example: XOR3
• What is worst-case voltage drop on node y?
CLK y = A B C
A !A a CL=50fF
B b CA=15fF !B B !B C =15fF c d B
!C C CD=10fF CC=15fF
CLK
Assume all inputs are low during precharge & caps = 0V 566 Image taken from: Digital Integrated Circuits (2nd Edition) by Rabaey, Chandrakasan, Nikolic
Worst-case charge sharing • Expose maximum amount of internal capacitance! CLK y = A B C
!A*B*C=[011] A !A a CL=50fF
B b CA=15fF !B B !B C =15fF c d B
!C C CD=10fF CC=15fF
CLK Vout = -VDD ((C A+C C)/(C A+C C+C L)) 567
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Worst-case charge sharing (cont’d)
• 2nd solution: A*!B*C=[101] CLK y = A B C
A !A a CL=50fF
B b CA=15fF !B B !B C =15fF c d B
!C C CD=10fF CC=15fF
CLK Vout = -VDD ((C B+C C)/(C B+C C+C L))=-VDD (30/80) 568
(“Solution” to charge sharing)
precharge transistor • Precharge all internal (and critical) nodes M CLK Mp pt CLK using PMOS Out A – Increases area – Increases power (larger B capacitance)
CLK Me – Reduces speed (larger capacitance)
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Issue 3: capacitive & backgate coupling • Susceptible to crosstalk – High-impedance output node – Capacitive coupling from neighboring node • Backgate coupling:
CLK M M6 M5 p Out1 =1 Out2 0 M4 A=0 M1 CL1 CL2
M3 In B=0 M2 off voltage
CLK Me reduces output goes low
dynamic NAND static NAND 570
Backgate coupling effect
overshoots due to 3 clock feed-through
2 Out1 voltage drops due 1 Clk to backgate effect
0 In Out2 never fully goes to zero (coupling) -1 0 2Time, ns 4 6 If Out1 drops too much incorrect behavior careful with layout! 571 Image taken from: Digital Integrated Circuits (2nd Edition) by Rabaey, Chandrakasan, Nikolic
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Issue 4: Clock feedthrough
• Capacitive coupling between CLK input of precharge transistor and dynamic node
• Coupling between Out and CLK Mp CLK input of precharge Out A device due to C GD CL • Voltage of Out can rise B above V DD CLK M e • Fast rising (falling edges) of clock couple to Out
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Remember? dynamic behavior
clock or signal feedthrough!
CLK Mp 2.5 Out evaluate In 1 1.5 In 2
In 3 0.5 In & CLK In 4 Out precharge CLK -0.5 0 0.5 1 Time, ns clock or signal feedthrough!
Does not only happen for dynamic circuits 573
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It’s not that easy Problem with cascading dynamic gates
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Cascading causes problems
Two inverters: V
Clk Clk Clk Mp Mp Out2 In Out1 In V Out1 Tn Clk Me Clk Me V Out2
also discharges, t because Out1 is initially at VDD
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Cascading causes problems (cont’d)
• As nodes are charged Clk to 1, they may cause Clk Mp Mp Out2 unwanted discharge Out1 In • Setting all inputs to 0 Clk M Clk e Me during precharge would fix the problem
• Only a single 0 1 transition allowed at inputs during the evaluation period! 576
Cascading causes problems (cont’d)
• As nodes are charged Clk to 1, they may cause Clk Mp Mp Out2 unwanted discharge Out1 In • Setting all inputs to 0 Clk M Clk e Me during precharge would fix the problem
• Only a single 0 1 transition allowed at inputs during the evaluation period! 577
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Solution: domino logic
static CMOS inverter
Mp CLK Mp CLK 1 Out1 Out2 0 In 1 In PDN In 2 PDN 4 at end of In In 5 3 precharge M CLK Me CLK e
• Inputs to domino gate are set to 0 at end of precharge period
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Solution: domino logic (cont’d)
Mp CLK Mp CLK 11 Out1 Out2 00 In 1 In PDN In 2 PDN 4 during In In 5 3 evaluation M CLK Me CLK e
• Inputs to domino gate are set to 0 at end of precharge period
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Solution: domino logic (cont’d)
Mp CLK Mp CLK 10 Out1 Out2 01 In 1 In PDN In 2 PDN 4 during In In 5 3 evaluation M CLK Me CLK e
• Only possible transition is 0 1, which guarantees signal integrity
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