Lecture 10: MOS Circuit Styles Pseudo Nmos and Precharged Logic Overview
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Reduced Swing Domino Techniques for Low Power and High Performance Arithmetic Circuits
Reduced Swing Domino Techniques for Low Power and High Performance Arithmetic Circuits by Shahrzad Naraghi A thesis presented to the University of Waterloo in ful¯llment of the thesis requirement for the degree of Master of Applied Science in Electrical and Computer Engineering Waterloo, Ontario, Canada 2004 °c Shahrzad Naraghi, 2004 I hereby declare that I am the sole author of this thesis. I authorize the University of Waterloo to lend this thesis to other institutions or individuals for the purpose of scholarly research. Shahrzad Naraghi I authorize the University of Waterloo to reproduce this thesis by photocopying or other means, in total or in part, at the request of other institutions or individuals for the purpose of scholarly research. Shahrzad Naraghi ii The University of Waterloo requires the signatures of all persons using or photocopying this thesis. Please sign below, and give address and date. iii Acknowledgements First, I would like to thank my supervisor Professor Manoj Sachdev for his great guidance, support and patience. His advice and support were always greatly appreciated. I also want to thank Dr. Opal and Dr. Anis, my thesis readers. I'd like to thank Bhaskar Chatterjee for his great help on my research; Phil Regier for his great help on computer problems; and my good friends for bringing me joy and laughter during these years that I was away from my family. Most importantly, I'd like to thank my family for their supporting and encouraging com- ments, their love and faith in me. iv Abstract The increasing frequency of operation and the larger number of transistors on the chip, along with slower decrease in supply voltage have led to more power dissipation and high chip power density which cause problems in chip thermal management and heat removal process. -
EE 434 Lecture 2
EE 330 Lecture 6 • PU and PD Networks • Complex Logic Gates • Pass Transistor Logic • Improved Switch-Level Model • Propagation Delay Review from Last Time MOS Transistor Qualitative Discussion of n-channel Operation Source Gate Drain Drain Bulk Gate n-channel MOSFET Source Equivalent Circuit for n-channel MOSFET D D • Source assumed connected to (or close to) ground • VGS=0 denoted as Boolean gate voltage G=0 G = 0 G = 1 • VGS=VDD denoted as Boolean gate voltage G=1 • Boolean G is relative to ground potential S S This is the first model we have for the n-channel MOSFET ! Ideal switch-level model Review from Last Time MOS Transistor Qualitative Discussion of p-channel Operation Source Gate Drain Drain Bulk Gate Source p-channel MOSFET Equivalent Circuit for p-channel MOSFET D D • Source assumed connected to (or close to) positive G = 0 G = 1 VDD • VGS=0 denoted as Boolean gate voltage G=1 • VGS= -VDD denoted as Boolean gate voltage G=0 S S • Boolean G is relative to ground potential This is the first model we have for the p-channel MOSFET ! Review from Last Time Logic Circuits VDD Truth Table A B A B 0 1 1 0 Inverter Review from Last Time Logic Circuits VDD Truth Table A B C 0 0 1 0 1 0 A C 1 0 0 B 1 1 0 NOR Gate Review from Last Time Logic Circuits VDD Truth Table A B C A C 0 0 1 B 0 1 1 1 0 1 1 1 0 NAND Gate Logic Circuits Approach can be extended to arbitrary number of inputs n-input NOR n-input NAND gate gate VDD VDD A1 A1 A2 An A2 F A1 An F A2 A1 A2 An An A1 A 1 A2 F A2 F An An Complete Logic Family Family of n-input NOR gates forms -
CSCE 5730 Digital CMOS VLSI Design
Lecture 2: Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides are borrowed from various books, websites, authors pages, and other sources for academic purpose only. The instructor does not claim any originality. CSCE 5730: Digital CMOS VLSI Design 1 Lecture Outline • Historical development of computers • Introduction to a basic digital computer • Five classic components of a computer • Microprocessor • IC design abstraction level • Intel processor family • Developmental trends of ICs • Moore’s Law CSCE 5730: Digital CMOS VLSI Design 2 Introduction to Digital Circuits CSCE 5730: Digital CMOS VLSI Design 3 What is a digital Computer ? A fast electronic machine that accepts digitized input information, processes it according to a list of internally stored instruction, and produces the resulting output information. List of instructions Æ Computer program Internal storage Æ Memory CSCE 5730: Digital CMOS VLSI Design 4 Different Types and Forms of Computer • Personal Computers (Desktop PCs) • Notebook computers (Laptop computers) • Handheld PCs • Pocket PCs • Workstations (SGI, HP, IBM, SUN) • ATM (Embedded systems) • Supercomputers CSCE 5730: Digital CMOS VLSI Design 5 Five classic components of a Computer Computer Processor Memory Devices Control Input Datapath Output (1) Input, (2) Output, (3) Datapath, (4) Controller, and (5) Memory CSCE 5730: Digital CMOS VLSI Design 6 What is a microprocessor ? • A microprocessor is an integrated circuit (IC) built on a tiny piece of silicon. It contains thousands, or even millions, of transistors, which are interconnected via superfine traces of aluminum. The transistors work together to store and manipulate data so that the microprocessor can perform a wide variety of useful functions. -
Digital Logic and Design (Course Code: EE222) Ltlecture 6: Lliogic Famili Es
Indian Institute of Technology Jodhpur, Year 2018‐2019 Digital Logic and Design (Course Code: EE222) LtLecture 6: LiLogic Fam ilies Course Instructor: Shree Prakash Tiwari EilEmail: sptiwari@iitj .ac.i n Webpage: http://home.iitj.ac.in/~sptiwari/ Course related documents will be uploaded on http://home.iitj.ac.in/~sptiwari/DLD/ Note: The information provided in the slides are taken form text books Digital Electronics (including Mano & Ciletti), and various other resources from internet, for teaching/academic use only 1 Overview •Early families (DL, RTL) • TTL •Evolution of TTL family • CMOS family and its evolution 2 Logic families Diode Logic (DL) •simpp;lest; does not scale •NOT not possible (need = an active element) Resistor-Transistor Logic (RTL) • replace diode switch with a tittransistor switc h •can be cascaded = • large power draw 3 Logic families Diode-Transistor Logic (DTL) • essentially diode logic with transistor amplification • reduced power consumption •faster than RTL = DL AND gate Saturating inverter 4 Logic Families • The bipolar transistor as a logical switch TTL Bipolar Transistor-Transistor Logic (TTL) •First introduced by in 1964 (Texas Instruments) •TTL has shaped digital technology in many ways • Standard TTL family (e.g. 7400) is obsolete •Newer TTL families used (e.g. 74ALS00) 6 TTL Bipolar Transistor-Transistor Logic (TTL) Distinct features •Multi‐emitter transistors 7 TTL A Standard TTL NAND gate 8 TTL A standard TTL NAND gate with open collector output 9 TTL evolution Schottky series (74LS00) TTL •A major -
Chapter 6 PROBLEMS
1 Chapter 6 Problem Set Chapter 6 PROBLEMS 1. [E, None, 4.2] Implement the equation X = ((A + B) (C + D + E) + F) G using complemen- tary CMOS. Size the devices so that the output resistance is the same as that of an inverter with an NMOS W/L = 2 and PMOS W/L = 6. Which input pattern(s) would give the worst and best equivalent pull-up or pull-down resistance? Solution Rewriting the output expression in the form X = ((A + B) (C + D + E) + F) G = ((AB + CDE)F) + G allows us to build the pulldown network by inspection (parallel devices imple- ment an OR, and series devices implement an AND). The pullup network is the dual of the pulldown network. A B 24 24 F 12 C 24 D 24 E 24 G 12 X A 8 C 12 G 2 B 8 D 12 E 12 F 4 The plot shows sizes that meet the requirement - in the worst case, the output resistance of the circuit matches the output resistance of an inverter with NMOS W/L=2 and PMOS W/L=6. The worst case pull-up resistance occurs whenever a single path exists from the output node to Vdd. Examples of vectors for the worst case are ABCDEFG=1111100 and 0101110. The best case pull-up resistance occurs when ABCDEFG=0000000. The worst case pull-down resistance occurs whenever a single path exists from the out- put node to GND. Examples of vectors for the worst case are ABCDEFG=0000001 and 0011110. The best case pull-down resistance occurs when ABCDEFG=1111111. -
Chapter6-6.Pdf
MEMS1082 Chapter 6 Digital Circuit 6-6 Department of Mechanical Engineering TTL and CMOS ICs , TTL and CMOS output circuit totem pole configuration When the upper transistor is forward biased and the bottom When input is high, the p- transistor is off, the output is type transistor (top) is off, high. The resistor, transistor, n-type is on. So the and diode drop the actual output is pulled low. The output voltage to a value device sinks current typically about 3.4 V. When the lower transistor is forward When input is low, the n- biased and the top transistor is type transistor (bottom) is off, the output is low. off, p-type is on. So the The TTL device sources current output is pulled high. The when there is a high output and device sources current. sinks current when the output is low. TTL device dissipates power continuously regardless of whether the output is high or low. Department of Mechanical Engineering The MOSFET and MOSFET switching states There are presently two general types of MOSFETs: depletion and enhancement. MOS digital ICs use enhancement MOSFETs exclusively The direction of the arrow indicates either P- or N-channel. The symbols show a broken line between the source and drain to indicate that there is normally no conducting channel between these electrodes. Symbol also shows a separation between the gate and the other terminals to indicate the very high resistance (typically around 1012 Ω ) between the gate and channel. Department of Mechanical Engineering The MOSFET and MOSFET switching states Department of Mechanical Engineering N-MOS Inverter Department of Mechanical Engineering N-MOS NAND Gate Department of Mechanical Engineering N-MOS NOR Gate Department of Mechanical Engineering CMOS Logic The complementary MOS (CMOS) logic family uses both P- and N- channel MOSFETs in the same circuit to realize several advantages over the P-MOS and N- MOS families. -
VLSI Overview
Lecture 1: VLSI Overview Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides are borrowed from various books, websites, authors pages, and other sources for academic purpose only. The instructor does not claim any origgyinality. Digital CMOS VLSI Design 1 Lecture Outline • Historical development of computers • ItIntro duc tion toabibasic dig ita l computer • Five classic components of a computer • Microprocessor • IC design abstraction level • Processor Trend • DlDevelopmen tltal tdtrendsof ICs • Moore’s Law Digital CMOS VLSI Design 2 Introduction to Digital Circuits Digital CMOS VLSI Design 3 What is a digital Computer ? A fast electronic machine that accepts digitized input information, processes it according to a list of internally stored instruction, and produces the resulting output information. List of instructions Computer program Internal storage Memory Digital CMOS VLSI Design 4 Different Types and Forms of Computer • Personal Computers (Desktop PCs) • Notebook computers (Laptop computers) • Handheld PCs • Pocket PCs • WkttiWorkstations (SGI, HP, IBM, SUN) • ATM (Embedded systems) • Supercomputers Digital CMOS VLSI Design 5 Five classic components of a Computer Computer Processor Memory Devices Control Input Datapath Output (1) Input, (2) Output, (3) Datapath, (4) Controller, and (5) Memory Digital CMOS VLSI Design 6 What is a microprocessor ? • A microprocessor is an integrated circuit (IC) built on a tiny piece of silicon. It contains thousands, or even millions, of transistors, which are interconnected via superfine traces of aluminum. The transistors work together to store and manipulate data so that the microprocessor can perform a wide variety of useful functions. The particular functions a microprocessor performs are dictated by software. -
Logic Families/Objectives
Logic Families/Objectives – Digital Logic Voltage and Current Parameters • Fan-out, Noise Margin, Propagation Delay – TTL Logic Family – Supply current spikes and ground bounce – TTL Logic Family Evolution –ECL – CMOS Logic Families and Evolution – Logic Family Overview 29/09/2005 EE6471 (KR) 121 Logic Families/Level of Integration – SSI <12 gates/chip Level of integration ever increasing, because of – MSI 12..99 gates/chip •cost •speed – LSI ..1000 gates/chip •size •power – VLSI …10k gates/chip •reliability – ULSI …100k gates/chip Limits of integration: – GSI …1Meg gates/chip •packaging •power dissipation •inductive and capacitive components Note: Ratio gate count/transistor count •flexibility is roughly 1/10 •critical quantity 29/09/2005 EE6471 (KR) 122 Logic Families/Level of Integration – Remember: Gordon Moore, 1975. Predictions: • Mosfet device dimensions scale down by a factor of 2 every 3 years • #transistors/chip double every 1-2 years. Source: G. Sery, Intel 29/09/2005 EE6471 (KR) 123 Logic Families/Static VI Parameters Vcc Vcc Vcc Ioh Iih Iol Iil Voh Vih Vol Vil Parameter Comment Voh(min) High-Level Output Voltage. The minimum voltage level at a logic circuit output in the logical 1 state under defined load conditions. Vol(max) Low-Level Output Voltage. The maximum voltage level at a logic circuit output in the logical 0 state under defined load conditions. 29/09/2005 EE6471 (KR) 124 Logic Families/Static VI Parameters Vcc Vcc Vcc Ioh Iih Iol Iil Voh Vih Vol Vil Parameter Comment Vih(min) High-Level Input Voltage. The minimum voltage level required for a logical 1 at an input. -
Computer Architectures an Overview
Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements. -
Designing Combinational Logic Gates in Cmos
CHAPTER 6 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS In-depth discussion of logic families in CMOS—static and dynamic, pass-transistor, nonra- tioed and ratioed logic n Optimizing a logic gate for area, speed, energy, or robustness n Low-power and high-performance circuit-design techniques 6.1 Introduction 6.3.2 Speed and Power Dissipation of Dynamic Logic 6.2 Static CMOS Design 6.3.3 Issues in Dynamic Design 6.2.1 Complementary CMOS 6.3.4 Cascading Dynamic Gates 6.5 Leakage in Low Voltage Systems 6.2.2 Ratioed Logic 6.4 Perspective: How to Choose a Logic Style 6.2.3 Pass-Transistor Logic 6.6 Summary 6.3 Dynamic CMOS Design 6.7 To Probe Further 6.3.1 Dynamic Logic: Basic Principles 6.8 Exercises and Design Problems 197 198 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS Chapter 6 6.1Introduction The design considerations for a simple inverter circuit were presented in the previous chapter. In this chapter, the design of the inverter will be extended to address the synthesis of arbitrary digital gates such as NOR, NAND and XOR. The focus will be on combina- tional logic (or non-regenerative) circuits that have the property that at any point in time, the output of the circuit is related to its current input signals by some Boolean expression (assuming that the transients through the logic gates have settled). No intentional connec- tion between outputs and inputs is present. In another class of circuits, known as sequential or regenerative circuits —to be dis- cussed in a later chapter—, the output is not only a function of the current input data, but also of previous values of the input signals (Figure 6.1). -
Design of 64-Bit Arithmetic Logic Unit (ALU) Based on BSIM4 Model Using Tanner
IJSART - Volume 2 Issue 10 –OCTOBER 2016 ISSN [ONLINE]: 2395-1052 Design of 64-bit Arithmetic Logic Unit (ALU) Based on BSIM4 Model Using Tanner Pragati Nagdeote1, Prof. Manisha Waje2 1, 2 Department of ENTC 1, 2 SPPU/G.H.Raisoni College of Engineering and Management, Pune, Maharashtra/Zone, India Abstract- Arithmetic circuits play a vital role in computational CMOS provides: an exceptionally low power-delay product, and digital circuits. Arithmetic Logic Unit (ALU) can perform the ability to accommodate millions of devices on a single various arithmetic and logical functions. Proposed 64-bit ALU chip, and flexible, custom design methodologies which permit comprises of different arithmetic functions such as addition, optimization, as required, for lowest cost, lowest power, or subtraction and logical functions like AND logic, OR logic, highest speed. In the recent years, there has been a large NOR logic and NAND logic. ALU always faces the issues of progress in the area of computer systems which are produce power consumption when there are the complex operations, and based on general purpose micro-processors [4]. ALU is therefore to overcome this problem the low power 64-bit ALU one of the most power hungry building blocks in the is designed using adiabatic logic with 180nm CMOS processor, increasing the power and thermal issues. The technology. BSIM4 model is used for the implementation of presence of multiple ALUs in current-day processors further 64-bit full adder, 64-bit AND logic, 64-bit OR logic, 4:1 creates the problem, impacting the circuit reliability and Multiplexer, 2:1 Multiplexer and Proposed design is verified increasing the power cost. -
Integrated Circuit Design Macmillan New Electronics Series Series Editor: Paul A
Integrated Circuit Design Macmillan New Electronics Series Series Editor: Paul A. Lynn Paul A. Lynn, Radar Systems A. F. Murray and H. M. Reekie, Integrated Circuit Design Integrated Circuit Design Alan F. Murray and H. Martin Reekie Department of' Electrical Engineering Edinhurgh Unit·ersity Macmillan New Electronics Introductions to Advanced Topics M MACMILLAN EDUCATION ©Alan F. Murray and H. Martin Reekie 1987 All rights reserved. No reproduction, copy or transmission of this publication may be made without written permission. No paragraph of this publication may be reproduced, copied or transmitted save with written permission or in accordance with the provisions of the Copyright Act 1956 (as amended), or under the terms of any licence permitting limited copying issued by the Copyright Licensing Agency, 7 Ridgmount Street, London WC1E 7AE. Any person who does any unauthorised act in relation to this publication may be liable to criminal prosecution and civil claims for damages. First published 1987 Published by MACMILLAN EDUCATION LTD Houndmills, Basingstoke, Hampshire RG21 2XS and London Companies and representatives throughout the world British Library Cataloguing in Publication Data Murray, A. F. Integrated circuit design.-(Macmillan new electronics series). 1. Integrated circuits-Design and construction I. Title II. Reekie, H. M. 621.381'73 TK7874 ISBN 978-0-333-43799-5 ISBN 978-1-349-18758-4 (eBook) DOI 10.1007/978-1-349-18758-4 To Glynis and Christa Contents Series Editor's Foreword xi Preface xii Section I 1 General Introduction