DOCSLIB.ORG

Logic Families/Objectives

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Logic Families/Objectives Logic Families/Objectives – Digital Logic Voltage and Current Parameters • Fan-out, Noise Margin, Propagation Delay – TTL Logic Family – Supply current spikes and ground bounce – TTL Logic Family Evolution –ECL – CMOS Logic Families and Evolution – Logic Family Overview 29/09/2005 EE6471 (KR) 121 Logic Families/Level of Integration – SSI <12 gates/chip Level of integration ever increasing, because of – MSI 12..99 gates/chip •cost •speed – LSI ..1000 gates/chip •size •power – VLSI …10k gates/chip •reliability – ULSI …100k gates/chip Limits of integration: – GSI …1Meg gates/chip •packaging •power dissipation •inductive and capacitive components Note: Ratio gate count/transistor count •flexibility is roughly 1/10 •critical quantity 29/09/2005 EE6471 (KR) 122 Logic Families/Level of Integration – Remember: Gordon Moore, 1975. Predictions: • Mosfet device dimensions scale down by a factor of 2 every 3 years • #transistors/chip double every 1-2 years. Source: G. Sery, Intel 29/09/2005 EE6471 (KR) 123 Logic Families/Static VI Parameters Vcc Vcc Vcc Ioh Iih Iol Iil Voh Vih Vol Vil Parameter Comment Voh(min) High-Level Output Voltage. The minimum voltage level at a logic circuit output in the logical 1 state under defined load conditions. Vol(max) Low-Level Output Voltage. The maximum voltage level at a logic circuit output in the logical 0 state under defined load conditions. 29/09/2005 EE6471 (KR) 124 Logic Families/Static VI Parameters Vcc Vcc Vcc Ioh Iih Iol Iil Voh Vih Vol Vil Parameter Comment Vih(min) High-Level Input Voltage. The minimum voltage level required for a logical 1 at an input. Any voltage below this level may not be recognized as a logical 1 by the logic circuit. Vil(max) Low-Level Input Voltage. The maximum voltage level required for a logical 0 at an input. Any voltage above this level may not be recognized as a logical 0 by the logic circuit. 29/09/2005 EE6471 (KR) 125 Logic Families/Static VI Parameters Vcc Vcc Vcc Ioh Iih Iol Iil Voh Vih Vol Vil Parameter Comment Ioh High-Level Output Current. Current flowing into an output in the logical 1 state under specified load conditions. Iol Low-Level Output Current. Current flowing into an output in the logical 0 state under specified load conditions. 29/09/2005 EE6471 (KR) 126 Logic Families/Static VI Parameters Vcc Vcc Vcc Ioh Iih Iol Iil Voh Vih Vol Vil Parameter Comment Iih High-Level Input Current. Current flowing into an input when a specified high-level voltage is applied to that input. Iil Low-Level Input Current. Current flowing into an input when a specified low-level voltage is applied to that input. 29/09/2005 EE6471 (KR) 127 Logic Families/Fan-Out – Fan-out: The maximum number of logic inputs that an output can drive reliably. Beware: Modern mixed-technology digital systems often employ logic from different logic families. In this case Fan-out is meaningless, unless the operating condition is specified exactly. Unless otherwise specified, fan-out is always assumed to refer to load devices of the same family as the driving output. 29/09/2005 EE6471 (KR) 128 Logic Families/Noise (Voltage) Margin Vcc Vcc High state noise margin : Vnh = Voh(min)−Vih(min) Output Input Low state noise margin : Vnl = Vil(max) −Vol(max) Logic 1 Logic 1 Noise margin : Voh(min) = Vnh Vn min(Vnh,Vnl) Vih(min) Abnormal Indetermined Operation Range Noise margin required for reliable operation Vil(max) of digital systems in the presence of noise, Vnl Vol(max) crosscoupling, and ground-bounce. Logic 0 Logic 0 Sometimes quoted: Percentage noise margin… bears little practical value. 29/09/2005 EE6471 (KR) 129 Logic Families/Propagation Delay vi 50% Input t vo vi vo 50% Output t tphl tplh Parameter Comment tphl Input-to-output propagation delay time for output going from high to low. tplh Input-to-output propagation delay time for output going from low to high. (Vague) comparison between logic families: Gate Speed Power Product : ⋅ (e.g. for 74HC00: 25ns*100µW=2.5pJ) tpavg Pdissavg 29/09/2005 EE6471 (KR) 130 Logic Families/TTL Logic Inputs A Output B Standard TTL Logic: •Bipolar Transistor-Transistor Logic •Introduced in 1964 (Texas Instruments) A B Y •Tremendous influence on the characteristics 0 0 1 Vcc of all logic devices today 0 1 1 5V 1 0 1 •Standard TTL shaped digital technology 1 1 0 R1 R2 R4 •Standard TTL Logic (e.g. 7400) practically 4k 1.6k 130 obsolete (i.e. replaced by more advanced Q3 logic families, e.g. 74ALS00) •A large variety of logic functions available Inputs Q1 D1 •Single- or multi-emitter input transistor Q1 A Q2 Output (up to eight emitters) B •Totem-pole output arrangement (Q3, Q4) Q4 R3 1k 29/09/2005 EE6471 (KR) 131 Logic Families/TTL Logic/Static Analysis Vcc Vcc Low State Analysis: 5V 5V •Inputs high (connected to Vcc) •Q1: Inverse-active mode R1 R2 R4 4k 1.6k 130 •Input currents very low (base current of Q2) •Q2 conducting (saturated) •Q4 conducting Q3 •Q3 and D1 off (approx 0.8V at B of Q3) OFF •Power dissipation in R1, Q1, R2, Q2, R3, Q4 OFF Q1 D1 •On-state resistance of Q4 is roughly 1..25Ω Q2 •Non-ideal pull-down: Vcesat (Q4) ON •Load will supply output low state current Q4 R3 ON 1k Q4 is referred to as current-sinking transistor or pull- down transistor Inputs interpreted as “high” when unconnected (floating). DON’T LEAVE INPUTS UNCONNECTED ! Floating inputs are susceptible to noise… 29/09/2005 EE6471 (KR) 132 Logic Families/TTL Logic/Static Analysis Vcc 5V High State Analysis: •One or both inputs low (connected to GND) R1 R2 R4 •Substantial input current (emitter current Q1) 4k 1.6k 130 controlled by R1 •Q1 on (saturated) Q3 •Q2 off ON •Q4 off ON Q1 D1 •Q3 and D1 on •Q3 acts as an “active pull-up” Q2 OFF •Non-ideal pull-up: Vbe (Q3) and Vfw (D1) Q4 •Output high current through R4, Q3, D1 R3 OFF •Power dissipation in R1, Q1, R2, R4, Q3, D1 1k •Vcc will supply output high state current Q3 is referred to as current-sourcing transistor or pull-up transistor 29/09/2005 EE6471 (KR) 133 Logic Families/TTL Logic/Cascading TTL Vcc Vcc Vcc 5V 5V 5V R1 R2 R4 R1 R2 R4 R1 R2 R4 4k 1.6k 130 4k 1.6k 130 4k 1.6k 130 Q3 Iih Q3 Q3 Iil Q1 D1 Q1 D1 Q1 D1 Q2 Q2 Q2 high low Q4 Q4 Q4 R3 R3 R3 1k 1k 1k 29/09/2005 EE6471 (KR) 134 Logic Families/Supply Current Spikes Vcc 5V Output Low-to-High Transient: •Initially: Q3 off, Q4 on (saturated) R1 R2 R4 4k 1.6k 130 •Q4 turned off, Q3 turned on •Change of state of Q4 takes longer than Q3 Q3 •During a short interval both Q3 and Q4 are conducting (cross-conduction, “shot-through”). Q1 i_transient D1 •Supply sees a relatively large current surge. Q2 •Additional current surge due to load Q4 capacitance (e.g. input capacitance of following R3 gate) 1k Cload Whenever a totem-pole TTL output goes from LOW vo to HIGH, a current spike is drawn from the supply. t Essential: POWER SUPPLY DECOUPLING! icc iccl icch Current spikes can cause noise problems (inductive cross- t coupling). Identify loops and minimise loop areas! 29/09/2005 EE6471 (KR) 135 Logic Families/Ground Bounce Vcc 5V Output High-to-Low Transient: R1 R2 R4 •Initially: Q3 on, Q4 off 4k 1.6k 130 •Negligible Q3/Q4 cross-conduction •Fast discharge of load capacitance through Q4 Q3 •Discharge current spike through IC ground pin. Q1 D1 i_transient Q2 Q4 vi R3 1k Cload Current spikes can cause noise problems (inductive cross- coupling). Identify loops and minimise loop areas! 29/09/2005 EE6471 (KR) 136 Logic Families/Ground Bounce Vcc 5V Discharge current path R1 R2 R4 •positive electrode of load capacitance 4k 1.6k 130 •Q4 Q3 •bond wire •IC pin Q1 D1 •tracks on PCB Q2 •ground plane on PCB Q4 •negative electrode of load capacitance R3 1k Cload •sections of the discharge current path are vi_eff i_transient shared with the input voltage loop internal IC GND vi L_shared Transient currents through shared inductance (bond wire, (package, tracks) vl_s tracking) is the cause for “ground bounce”. Ground Bounce = Voltage Difference between internal and external ground external IC GND L_unshared di vl _ s = L _ shared ⋅ L _ shared vi _ eff = vi − vl _ s dt 29/09/2005 EE6471 (KR) 137 Logic Families/Ground Bounce Digital logic gates are differential amplifiers! They look at input voltages with respect to their internal ground. Transient voltages across inductances between internal and external ground distort the input voltage and results in undesired feedback (positive or negative). Typically ground bounce does not significantly impair the transmitted signal, but it interferes in a major way with signal reception. What can be done to reduce ground bounce: •Minimise di/dt by proper choice of gate family •Minimise shared inductance (star point GND connection) •Use ICs with separate driver and logic ground pins •Identify current loops and minimise loop areas 29/09/2005 EE6471 (KR) 138 Logic Families/Ground Bounce 10 8.46 Vcc 5 v1 j v2 R V v2 j 0 V v1eff i2 j v1 i2 10⋅ m ⋅A 5 vls Ls − C 8.46 10 0102030405060708090100 0 tj() 99.994 ns⋅ 10 8.46 Example Parameter: 5 v1effj •Vcc=5V V •Tr=10ns vls j 0 •Tpd=15ns V ils j •Ls=40nH 10⋅ m ⋅A •C=100pF dils 5 •R=10Ω vls = Ls ⋅ − dt 10 10 0102030405060708090100 0 tj() 99.994 29/09/2005 EE6471 (KR)ns⋅ 139 Logic Families/TTL/Logic Evolution BJT (Bipolar Junction Transistor) storage time reduction by using a BC Schottky diode.
Load more

Recommended publications
  • EE 434 Lecture 2
    EE 330 Lecture 6 • PU and PD Networks • Complex Logic Gates • Pass Transistor Logic • Improved Switch-Level Model • Propagation Delay Review from Last Time MOS Transistor Qualitative Discussion of n-channel Operation Source Gate Drain Drain Bulk Gate n-channel MOSFET Source Equivalent Circuit for n-channel MOSFET D D • Source assumed connected to (or close to) ground • VGS=0 denoted as Boolean gate voltage G=0 G = 0 G = 1 • VGS=VDD denoted as Boolean gate voltage G=1 • Boolean G is relative to ground potential S S This is the first model we have for the n-channel MOSFET ! Ideal switch-level model Review from Last Time MOS Transistor Qualitative Discussion of p-channel Operation Source Gate Drain Drain Bulk Gate Source p-channel MOSFET Equivalent Circuit for p-channel MOSFET D D • Source assumed connected to (or close to) positive G = 0 G = 1 VDD • VGS=0 denoted as Boolean gate voltage G=1 • VGS= -VDD denoted as Boolean gate voltage G=0 S S • Boolean G is relative to ground potential This is the first model we have for the p-channel MOSFET ! Review from Last Time Logic Circuits VDD Truth Table A B A B 0 1 1 0 Inverter Review from Last Time Logic Circuits VDD Truth Table A B C 0 0 1 0 1 0 A C 1 0 0 B 1 1 0 NOR Gate Review from Last Time Logic Circuits VDD Truth Table A B C A C 0 0 1 B 0 1 1 1 0 1 1 1 0 NAND Gate Logic Circuits Approach can be extended to arbitrary number of inputs n-input NOR n-input NAND gate gate VDD VDD A1 A1 A2 An A2 F A1 An F A2 A1 A2 An An A1 A 1 A2 F A2 F An An Complete Logic Family Family of n-input NOR gates forms
    [Show full text]
  • CSCE 5730 Digital CMOS VLSI Design
    Lecture 2: Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides are borrowed from various books, websites, authors pages, and other sources for academic purpose only. The instructor does not claim any originality. CSCE 5730: Digital CMOS VLSI Design 1 Lecture Outline • Historical development of computers • Introduction to a basic digital computer • Five classic components of a computer • Microprocessor • IC design abstraction level • Intel processor family • Developmental trends of ICs • Moore’s Law CSCE 5730: Digital CMOS VLSI Design 2 Introduction to Digital Circuits CSCE 5730: Digital CMOS VLSI Design 3 What is a digital Computer ? A fast electronic machine that accepts digitized input information, processes it according to a list of internally stored instruction, and produces the resulting output information. List of instructions Æ Computer program Internal storage Æ Memory CSCE 5730: Digital CMOS VLSI Design 4 Different Types and Forms of Computer • Personal Computers (Desktop PCs) • Notebook computers (Laptop computers) • Handheld PCs • Pocket PCs • Workstations (SGI, HP, IBM, SUN) • ATM (Embedded systems) • Supercomputers CSCE 5730: Digital CMOS VLSI Design 5 Five classic components of a Computer Computer Processor Memory Devices Control Input Datapath Output (1) Input, (2) Output, (3) Datapath, (4) Controller, and (5) Memory CSCE 5730: Digital CMOS VLSI Design 6 What is a microprocessor ? • A microprocessor is an integrated circuit (IC) built on a tiny piece of silicon. It contains thousands, or even millions, of transistors, which are interconnected via superfine traces of aluminum. The transistors work together to store and manipulate data so that the microprocessor can perform a wide variety of useful functions.
    [Show full text]
  • Digital Logic and Design (Course Code: EE222) Ltlecture 6: Lliogic Famili Es
    Indian Institute of Technology Jodhpur, Year 2018‐2019 Digital Logic and Design (Course Code: EE222) LtLecture 6: LiLogic Fam ilies Course Instructor: Shree Prakash Tiwari EilEmail: sptiwari@iitj .ac.i n Webpage: http://home.iitj.ac.in/~sptiwari/ Course related documents will be uploaded on http://home.iitj.ac.in/~sptiwari/DLD/ Note: The information provided in the slides are taken form text books Digital Electronics (including Mano & Ciletti), and various other resources from internet, for teaching/academic use only 1 Overview •Early families (DL, RTL) • TTL •Evolution of TTL family • CMOS family and its evolution 2 Logic families Diode Logic (DL) •simpp;lest; does not scale •NOT not possible (need = an active element) Resistor-Transistor Logic (RTL) • replace diode switch with a tittransistor switc h •can be cascaded = • large power draw 3 Logic families Diode-Transistor Logic (DTL) • essentially diode logic with transistor amplification • reduced power consumption •faster than RTL = DL AND gate Saturating inverter 4 Logic Families • The bipolar transistor as a logical switch TTL Bipolar Transistor-Transistor Logic (TTL) •First introduced by in 1964 (Texas Instruments) •TTL has shaped digital technology in many ways • Standard TTL family (e.g. 7400) is obsolete •Newer TTL families used (e.g. 74ALS00) 6 TTL Bipolar Transistor-Transistor Logic (TTL) Distinct features •Multi‐emitter transistors 7 TTL A Standard TTL NAND gate 8 TTL A standard TTL NAND gate with open collector output 9 TTL evolution Schottky series (74LS00) TTL •A major
    [Show full text]
  • Chapter6-6.Pdf
    MEMS1082 Chapter 6 Digital Circuit 6-6 Department of Mechanical Engineering TTL and CMOS ICs , TTL and CMOS output circuit totem pole configuration When the upper transistor is forward biased and the bottom When input is high, the p- transistor is off, the output is type transistor (top) is off, high. The resistor, transistor, n-type is on. So the and diode drop the actual output is pulled low. The output voltage to a value device sinks current typically about 3.4 V. When the lower transistor is forward When input is low, the n- biased and the top transistor is type transistor (bottom) is off, the output is low. off, p-type is on. So the The TTL device sources current output is pulled high. The when there is a high output and device sources current. sinks current when the output is low. TTL device dissipates power continuously regardless of whether the output is high or low. Department of Mechanical Engineering The MOSFET and MOSFET switching states There are presently two general types of MOSFETs: depletion and enhancement. MOS digital ICs use enhancement MOSFETs exclusively The direction of the arrow indicates either P- or N-channel. The symbols show a broken line between the source and drain to indicate that there is normally no conducting channel between these electrodes. Symbol also shows a separation between the gate and the other terminals to indicate the very high resistance (typically around 1012 Ω ) between the gate and channel. Department of Mechanical Engineering The MOSFET and MOSFET switching states Department of Mechanical Engineering N-MOS Inverter Department of Mechanical Engineering N-MOS NAND Gate Department of Mechanical Engineering N-MOS NOR Gate Department of Mechanical Engineering CMOS Logic The complementary MOS (CMOS) logic family uses both P- and N- channel MOSFETs in the same circuit to realize several advantages over the P-MOS and N- MOS families.
    [Show full text]
  • VLSI Overview
    Lecture 1: VLSI Overview Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides are borrowed from various books, websites, authors pages, and other sources for academic purpose only. The instructor does not claim any origgyinality. Digital CMOS VLSI Design 1 Lecture Outline • Historical development of computers • ItIntro duc tion toabibasic dig ita l computer • Five classic components of a computer • Microprocessor • IC design abstraction level • Processor Trend • DlDevelopmen tltal tdtrendsof ICs • Moore’s Law Digital CMOS VLSI Design 2 Introduction to Digital Circuits Digital CMOS VLSI Design 3 What is a digital Computer ? A fast electronic machine that accepts digitized input information, processes it according to a list of internally stored instruction, and produces the resulting output information. List of instructions Computer program Internal storage Memory Digital CMOS VLSI Design 4 Different Types and Forms of Computer • Personal Computers (Desktop PCs) • Notebook computers (Laptop computers) • Handheld PCs • Pocket PCs • WkttiWorkstations (SGI, HP, IBM, SUN) • ATM (Embedded systems) • Supercomputers Digital CMOS VLSI Design 5 Five classic components of a Computer Computer Processor Memory Devices Control Input Datapath Output (1) Input, (2) Output, (3) Datapath, (4) Controller, and (5) Memory Digital CMOS VLSI Design 6 What is a microprocessor ? • A microprocessor is an integrated circuit (IC) built on a tiny piece of silicon. It contains thousands, or even millions, of transistors, which are interconnected via superfine traces of aluminum. The transistors work together to store and manipulate data so that the microprocessor can perform a wide variety of useful functions. The particular functions a microprocessor performs are dictated by software.
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • Designing Combinational Logic Gates in Cmos
    CHAPTER 6 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS In-depth discussion of logic families in CMOS—static and dynamic, pass-transistor, nonra- tioed and ratioed logic n Optimizing a logic gate for area, speed, energy, or robustness n Low-power and high-performance circuit-design techniques 6.1 Introduction 6.3.2 Speed and Power Dissipation of Dynamic Logic 6.2 Static CMOS Design 6.3.3 Issues in Dynamic Design 6.2.1 Complementary CMOS 6.3.4 Cascading Dynamic Gates 6.5 Leakage in Low Voltage Systems 6.2.2 Ratioed Logic 6.4 Perspective: How to Choose a Logic Style 6.2.3 Pass-Transistor Logic 6.6 Summary 6.3 Dynamic CMOS Design 6.7 To Probe Further 6.3.1 Dynamic Logic: Basic Principles 6.8 Exercises and Design Problems 197 198 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS Chapter 6 6.1Introduction The design considerations for a simple inverter circuit were presented in the previous chapter. In this chapter, the design of the inverter will be extended to address the synthesis of arbitrary digital gates such as NOR, NAND and XOR. The focus will be on combina- tional logic (or non-regenerative) circuits that have the property that at any point in time, the output of the circuit is related to its current input signals by some Boolean expression (assuming that the transients through the logic gates have settled). No intentional connec- tion between outputs and inputs is present. In another class of circuits, known as sequential or regenerative circuits —to be dis- cussed in a later chapter—, the output is not only a function of the current input data, but also of previous values of the input signals (Figure 6.1).
    [Show full text]
  • Design of 64-Bit Arithmetic Logic Unit (ALU) Based on BSIM4 Model Using Tanner
    IJSART - Volume 2 Issue 10 –OCTOBER 2016 ISSN [ONLINE]: 2395-1052 Design of 64-bit Arithmetic Logic Unit (ALU) Based on BSIM4 Model Using Tanner Pragati Nagdeote1, Prof. Manisha Waje2 1, 2 Department of ENTC 1, 2 SPPU/G.H.Raisoni College of Engineering and Management, Pune, Maharashtra/Zone, India Abstract- Arithmetic circuits play a vital role in computational CMOS provides: an exceptionally low power-delay product, and digital circuits. Arithmetic Logic Unit (ALU) can perform the ability to accommodate millions of devices on a single various arithmetic and logical functions. Proposed 64-bit ALU chip, and flexible, custom design methodologies which permit comprises of different arithmetic functions such as addition, optimization, as required, for lowest cost, lowest power, or subtraction and logical functions like AND logic, OR logic, highest speed. In the recent years, there has been a large NOR logic and NAND logic. ALU always faces the issues of progress in the area of computer systems which are produce power consumption when there are the complex operations, and based on general purpose micro-processors [4]. ALU is therefore to overcome this problem the low power 64-bit ALU one of the most power hungry building blocks in the is designed using adiabatic logic with 180nm CMOS processor, increasing the power and thermal issues. The technology. BSIM4 model is used for the implementation of presence of multiple ALUs in current-day processors further 64-bit full adder, 64-bit AND logic, 64-bit OR logic, 4:1 creates the problem, impacting the circuit reliability and Multiplexer, 2:1 Multiplexer and Proposed design is verified increasing the power cost.
    [Show full text]
  • Integrated Circuit Design Macmillan New Electronics Series Series Editor: Paul A
    Integrated Circuit Design Macmillan New Electronics Series Series Editor: Paul A. Lynn Paul A. Lynn, Radar Systems A. F. Murray and H. M. Reekie, Integrated Circuit Design Integrated Circuit Design Alan F. Murray and H. Martin Reekie Department of' Electrical Engineering Edinhurgh Unit·ersity Macmillan New Electronics Introductions to Advanced Topics M MACMILLAN EDUCATION ©Alan F. Murray and H. Martin Reekie 1987 All rights reserved. No reproduction, copy or transmission of this publication may be made without written permission. No paragraph of this publication may be reproduced, copied or transmitted save with written permission or in accordance with the provisions of the Copyright Act 1956 (as amended), or under the terms of any licence permitting limited copying issued by the Copyright Licensing Agency, 7 Ridgmount Street, London WC1E 7AE. Any person who does any unauthorised act in relation to this publication may be liable to criminal prosecution and civil claims for damages. First published 1987 Published by MACMILLAN EDUCATION LTD Houndmills, Basingstoke, Hampshire RG21 2XS and London Companies and representatives throughout the world British Library Cataloguing in Publication Data Murray, A. F. Integrated circuit design.-(Macmillan new electronics series). 1. Integrated circuits-Design and construction I. Title II. Reekie, H. M. 621.381'73 TK7874 ISBN 978-0-333-43799-5 ISBN 978-1-349-18758-4 (eBook) DOI 10.1007/978-1-349-18758-4 To Glynis and Christa Contents Series Editor's Foreword xi Preface xii Section I 1 General Introduction
    [Show full text]
  • CMOS, the Ideal Logic Family Iha Nu Otg F5,Aco Uptcnsn About Sink Temperature Can Output Room CMOS at a 5V, TTL
    CMOS, the Ideal Logic Family AN-77 National Semiconductor CMOS, the Ideal Application Note 77 Logic Family Stephen Calebotta January 1983 INTRODUCTION The 54C/74C line consists of CMOS parts which are pin Let's talk about the characteristics of an ideal logic family. It and functional equivalents of many of the most popular should dissipate no power, have zero propagation delay, parts in the 7400 TTL series. This line is typically 50% faster controlled rise and fall times, and have noise immunity equal than the 4000A series and sinks 50% more current. For to 50% of the logic swing. ease of design, it is spec'd at TTL levels as well as CMOS levels, and there are two temperature ranges available: The properties of CMOS (complementary MOS) begin to 54C, 55 Cto 125 C or 74C, 40 Cto 85 C. Table I approach these ideal characteristics. b § a § b § a § compares the port parameters of the 54C/74C CMOS line First, CMOS dissipates low power. Typically, the static pow- to those of the 54L/74L low power TTL line. er dissipation is 10 nW per gate which is due to the flow of leakage currents. The active power depends on power sup- CHARACTERISTICS OF CMOS ply voltage, frequency, output load and input rise time, but The aim of this section is to give the system designer not typically, gate dissipation at 1 MHz with a 50 pF load is less familiar with CMOS, a good feel for how it works and how it than 10 mW. behaves in a system.
    [Show full text]
  • Logic Families
    Logic Families PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Mon, 11 Aug 2014 22:42:35 UTC Contents Articles Logic family 1 Resistor–transistor logic 7 Diode–transistor logic 10 Emitter-coupled logic 11 Gunning transceiver logic 16 Transistor–transistor logic 16 PMOS logic 23 NMOS logic 24 CMOS 25 BiCMOS 33 Integrated injection logic 34 7400 series 35 List of 7400 series integrated circuits 41 4000 series 62 List of 4000 series integrated circuits 69 References Article Sources and Contributors 75 Image Sources, Licenses and Contributors 76 Article Licenses License 77 Logic family 1 Logic family In computer engineering, a logic family may refer to one of two related concepts. A logic family of monolithic digital integrated circuit devices is a group of electronic logic gates constructed using one of several different designs, usually with compatible logic levels and power supply characteristics within a family. Many logic families were produced as individual components, each containing one or a few related basic logical functions, which could be used as "building-blocks" to create systems or as so-called "glue" to interconnect more complex integrated circuits. A "logic family" may also refer to a set of techniques used to implement logic within VLSI integrated circuits such as central processors, memories, or other complex functions. Some such logic families use static techniques to minimize design complexity. Other such logic families, such as domino logic, use clocked dynamic techniques to minimize size, power consumption, and delay. Before the widespread use of integrated circuits, various solid-state and vacuum-tube logic systems were used but these were never as standardized and interoperable as the integrated-circuit devices.
    [Show full text]
  • How to Select Little Logic
    Application Report SCYA049A–April 2010–Revised July 2016 How to Select Little Logic Samuel Lin................................................................................................... Standard Linear and Logic ABSTRACT TI Little Logic devices are logic-gate devices assembled in a small single-, dual-, or triple- gate package. Little Logic devices are widely used in portable equipment, such as mobile phones, MP3 players, and notebook computers. Little Logic devices are also used in desktop computers and telecommunications. Little Logic gates are common components for easy PC board routing, schematic design, and bug fixes that add without taking up significant space. Little Logic devices are offered in several product categories that meet specific requirements of low and ultra-low voltage, and low power. This application report discusses critical characteristics, features, and applications of TI’s newest Little Logic family and package offerings. Contents 1 Introduction ................................................................................................................... 2 2 Little Logic Product Families ............................................................................................... 4 3 Key Concerns in Little Logic Selection .................................................................................. 15 4 System Applications of Little Logic Gates............................................................................... 23 5 Little Logic Package Options/Trend.....................................................................................
    [Show full text]