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EE 434 Lecture 2 EE 330 Lecture 6 • PU and PD Networks • Complex Logic Gates • Pass Transistor Logic • Improved Switch-Level Model • Propagation Delay Review from Last Time MOS Transistor Qualitative Discussion of n-channel Operation Source Gate Drain Drain Bulk Gate n-channel MOSFET Source Equivalent Circuit for n-channel MOSFET D D • Source assumed connected to (or close to) ground • VGS=0 denoted as Boolean gate voltage G=0 G = 0 G = 1 • VGS=VDD denoted as Boolean gate voltage G=1 • Boolean G is relative to ground potential S S This is the first model we have for the n-channel MOSFET ! Ideal switch-level model Review from Last Time MOS Transistor Qualitative Discussion of p-channel Operation Source Gate Drain Drain Bulk Gate Source p-channel MOSFET Equivalent Circuit for p-channel MOSFET D D • Source assumed connected to (or close to) positive G = 0 G = 1 VDD • VGS=0 denoted as Boolean gate voltage G=1 • VGS= -VDD denoted as Boolean gate voltage G=0 S S • Boolean G is relative to ground potential This is the first model we have for the p-channel MOSFET ! Review from Last Time Logic Circuits VDD Truth Table A B A B 0 1 1 0 Inverter Review from Last Time Logic Circuits VDD Truth Table A B C 0 0 1 0 1 0 A C 1 0 0 B 1 1 0 NOR Gate Review from Last Time Logic Circuits VDD Truth Table A B C A C 0 0 1 B 0 1 1 1 0 1 1 1 0 NAND Gate Logic Circuits Approach can be extended to arbitrary number of inputs n-input NOR n-input NAND gate gate VDD VDD A1 A1 A2 An A2 F A1 An F A2 A1 A2 An An A1 A 1 A2 F A2 F An An Complete Logic Family Family of n-input NOR gates forms a complete logic family Family of n-input NAND gates forms a complete logic family Having both NAND and NOR gates available is a luxury Can now implement any combinationalA1 logic function !! A 1 A2 F A2 F If add one flip flop, can implement any Boolean system !! An An Flip flops easy to design but will discuss sequential logic systems later Other logic circuits • Other methods for designing logic circuits exist • Insight will be provided on how other logic circuits evolve • Several different types of logic circuits are often used simultaneously in any circuit design Pull-up and Pull-down Networks VDD VDD PUN A B A B PDN GND GND PU network comprised of p-channel device and “tries” to pull B to VDD when conducting PD network comprised of n-channel device and “tries to pull B to GND when conducting One and only one of these networks is conducting at the same time (to avoid contention) Pull-up and Pull-down Networks VDD VDD PUN A C A C B B PDN PU network comprised of p-channel devices PD network comprised of n-channel devices One and only one of these networks is conducting at the same time Pull-up and Pull-down Networks VDD VDD A A PUN C C B B PDN PU network comprised of p-channel devices PD network comprised of n-channel devices One and only one of these networks is conducting at the same time Pull-up and Pull-down Networks V In these circuits, the PUN and PDN have DD the 3 interesting characteristics 1. PU network comprised of p-channel PUN devices 2. PD network comprised of n-channel Y X devices n 3. One and only one of these networks is conducting at the same time PDN What are VH and VL? What is the power dissipation? How fast are these logic circuits? What are VH and VL? What is the power dissipation? How fast are these logic circuits? Consider the inverterVDD Use switch-level model for MOS devices VDD B A A B A What are VH and VL? What is the power dissipation? How fast are these logic circuits? Consider the inverter Use switch-level model for MOS devices VDD VH=VDD V =0 L A B ID=0 thus PH=PL=0 A tHL=tLH=0 (too good to be true?) Pull-up and Pull-down Networks For these circuits, the PUN and PDN have 3 interesting characteristics Three key characteristics of these Static CMOS Gates VDD 1. PU network comprised of p-channel devices 2. PD network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time PUN Y X Three key properties of these Static CMOS Gates n 1. What are VH and VL? VH=VDD, VL=0 (too good to be true?) PDN 2. What is the power dissipation? PH=PL=0 (too good to be true?) 3. How fast are these logic circuits? tHL=tLH=0 (too good to be true?) These 3 properties are inherent in all Boolean circuits that have these 3 characteristics !!! Pull-up and Pull-down Networks Three key characteristics of Static CMOS Gates 1. PU network comprised of p-channel devices VDD 2. PD network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time PUN Y Three properties of Static CMOS Gates (based X upon simple switch-level model) n 1. V =V , V =0 (too good to be true?) H DD L PDN 2. PH=PL=0 (too good to be true?) 3. tHL=tLH=0 (too good to be true?) These 3 properties are inherent in Boolean circuits with these 3 characteristics Pull-up and Pull-down Networks Concept can be extended to arbitrary number of inputs n-input NOR gate n-input NAND gate VDD VDD X 1 X1 X2 Xn Y X2 X1 Xn X2 Y X1 X2 Xn Xn Pull-up and Pull-down Networks Concept can be extended to arbitrary number of inputs n-input NOR gate n-input NAND gate VDD VDD X1 X1 X2 Xn Y X2 X1 Xn X2 Y X1 X2 Xn Xn 1. PU network comprised of p-channel devices 2. PD network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time Pull-up and Pull-down Networks VDD VDD VDD PUN X1 X1 X2 Xn Y n-input NOR gateX2 Y X X1 n Xn X2 Y 1. PU network comprised of p-channelPD Ndevices X1 2. PD network comprised of n-channel devices X2 Xn 3. One and only one of these networksXn is conducting at the same time VH=VDD, VL=0 PH=PL=0 n-input NAND gate tHL=tLH=0 Nomenclature VDD VDD X1 X1 X2 Xn n-input NAND gate Y n-input NOR gateX2 X1 In this class, logic circuits that are implemented by interconnecting multiple- input NAND and NOR gates will be referred to as “Static CMOS Logic” Xn X2 Y Since the set of NAND gates is complete, any combinational logic function can X1 be realizedX2 with Xthen NAND circuit structures considered thus far Xn Since the set NOR gates is complete, any combinational logic function can be realized with the NOR circuit structures considered thus far Many logic functions are realized with “Static CMOS Logic” and this is probably the dominant design style used today! Example 1: Circuit Structures Circuit Design How many transistors are required to realize the function F A B A C in a basic CMOS process if static NAND and NOR gates are used? Assume A, B and C are available. Example 1: How many transistors are required to realize the function F A B A C in a basic CMOS process if static NAND and NOR gates are used? Assume A, B and C are available. Solution: C A F B 20 transistors and 5 levels of logic Example 1: How many transistors are required to realize the function F A B A C in a basic CMOS process if static NAND and NOR gates are used? Assume A, B and C are available. Solution (alternative): From basic Boolean Manipulations F A B A C A B A C F A 1 CB A B A F B 8 transistors and 3 levels of logic Example 1: How many transistors are required to realize the function F A B A C in a basic CMOS process if static NAND and NOR gates are used? Assume A, B and C are available. Solution (alternative): From basic Boolean Manipulations F A 1 CB A B F A B A B A F B 6 transistors and 2 levels of logic Example 2: XOR Function A Y B Y=A B A widely-used 2-input Gate Static CMOS implementation Y=AB + AB A Y B 22 transistors 5 levels of logic Delays unacceptable (will show later) and device count is too large ! Example 3: Y AB CD Standard Static CMOS Implementation A B Y C D 3 levels of Logic 16 Transistors if Basic CMOS Gates are Used Can the same Boolean functionality be obtained with less transistors? Observe: VDD C D A B Y Y A B CD B D A C Significant reduction in transistor count and levels of logic for realizing same Boolean function Termed a “Complex Logic Gate” implementation Some authors term this a “compound gate” Complex Logic Gates VDD Pull-up Network C D AY A BB CD Y B D A C Pull-down Network Complex Gates VDD Pull up and pull down network never both conducting C D One of the two networks is always conducting A B Y B D A C Complex Gates Nomenclature: VDD PUN Y X n When the logic gate shown is not a multiple-input NAND or NOR PgateDN but has Characteristics 1, 2, and 3 above, the gate will be referred to as a Complex Logic Gate Complex Logic Gates also implement static logic functions and some authors would refer to this as Static CMOS Logic as well but we will make the distinction and refer to this as “Complex Logic Gates” Complex Gates VDD PUN Y X n Complex Gate Design Strategy: PDN 1.
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