DOCSLIB.ORG

Implementing Dimensional-View of 4X4 Logic Gate/Circuit for Quantum Computer Hardware Using Xylinx

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Implementing Dimensional-View of 4X4 Logic Gate/Circuit for Quantum Computer Hardware Using Xylinx BABAR et al.: IMPLEMENTING DIMENSIONAL VIEW OF 4X4 LOGIC GATE IMPLEMENTING DIMENSIONAL-VIEW OF 4X4 LOGIC GATE/CIRCUIT FOR QUANTUM COMPUTER HARDWARE USING XYLINX MOHAMMAD INAYATULLAH BABAR1, SHAKEEL AHMAD3, SHEERAZ AHMED2, IFTIKHAR AHMED KHAN1 AND BASHIR AHMAD3 1NWFP University of Engineering & Technology, Peshawar, Pakistan 2City University of Science & Information Technology, Peshawar, Pakistan 3ICIT, Gomal University, Pakistan Abstract: Theoretical constructed quantum computer (Q.C) is considered to be an earliest and foremost computing device whose intention is to deploy formally analysed quantum information processing. To gain a computational advantage over traditional computers, Q.C made use of specific physical implementation. The standard set of universal reversible logic gates like CNOT, Toffoli, etc provide elementary basis for Quantum Computing. Reversible circuits are the gates having same no. of inputs/outputs known as its width with 1-to-1 vectors of inputs/outputs mapping. Hence vector input states can be reconstructed uniquely from output states of the vector. Control lines are used in reversible gates to feed its reversible circuits from work bits i.e. ancilla bits. In a combinational reversible circuit, all gates are reversible, and there is no fan-out or feedback. In this paper, we introduce implementation of 4x4 multipurpose logic circuit/gate which can perform multiple functions depending on the control inputs. The architecture we propose was compiled in Xylinx and hence the gating diagram and its truth table was developed. Keywords: Quantum Computer, Reversible Logic Gates, Truth Table 1. QUANTUM COMPUTING computations have been performed during which operation based on quantum Quantum computer is a computation device computations were executed on a small no. of that incorporates quantum mechanical qubits. phenomena distinctively to perform operation It is assumed that the Q.C will be able to on data in terms of superposition & handle different problems with much faster entanglement. In contrast to traditional speed as compared to the conventional computer where data is represented by means computers, if they built on large scale [7]. of bits, Q.C makes use of qubits for data The primary objects of Quantum Computing representation. Mathematical theory of are vectors and matrices of a Hilbert space computation mainly emphasizes on to model over the complex numbers. the computation abstraction from any Vectors are written as bras such as <Φ| and particular computer implementation. kets such as |Ψ> . |Ψ> corresponds to a normal With the development of technology, (vertical) vector whereas <Φ| corresponds to tremendous change has been observed in transposed (horizontal) and complex computer architectures. In addition computers conjugated vectors. with different machine architectures can be observed at any given time. To make them 2. BITS vs. QUBITS useful mathematicians have to conceptualize and abstract all these superficial architectural Memory of conventional computer is made up differences away and also to focus on the of bits and is used to hold either binary digit 1 factors that really composes computation [3]. or 0. The machine manipulates those bits by Still quantum computing known to be an means of transferring from logic gates to emerging technology and different memory and vice versa where as in Q.C, IJSSST Vol. 9 No. 5, December 2008 8 ISSN 1473-804x Online, 1473-8031 Print BABAR et al.: IMPLEMENTING DIMENSIONAL VIEW OF 4X4 LOGIC GATE memory makes use of holding data in terms of qubits .i.e. 1 or 0 or critically a superposition of these. Qubits implementation for Q.C is represented by particles having two spin states i.e. “up” written as | 0> and “down” written as |1 >:). They can also be entwined with other qubits which results the astonishing computational power of a quantum computer. Entanglement is an exclusive quantum Figure 1: Qubit Representation observable fact. It is a property of a multi-qubit state space and can be thought of Conventional bit 1 is represented by up arrow, as a resource that the measurement on one bit 0 is represented by down arrow and qubit will directly affect the other [7]. The arrow-in-between pertains to a superposition process of extracting information from a set of of 1 & 0. Moreover the arrow may be moving qubits is called measurement. around the vertical axis that pertains to the Just as classical computation is based on the qubit region [3]. ability to store and manipulate information on Consider conventional computing device collections of two-state “bits”, quantum operated on three bits register in which bits in computation relies on ensembles of two-state the register at any given time pertains to quantum systems called qubits. Unlike the definite state like 1-0-1 but in Q.C, qubits may classical bit, which occupies one of two be in a state of all the allowed classical states. mutually exclusive states, the qubit exists in a In general, the register is described by the superposition of two states. For our purposes, following wave function: the most general model of the qubit is: |ψ >= a|000> + b|001 >+ c|010 >+ d |100 >+ |ψ >= αβ|0|1 >+ > e |110 >+ f |011 >+ g |101 >+ h|111> Where α and β are complex numbers such Where a, b, c are coefficients for complex numbers having probabilities expressed in that terms of amplitudes squares for measuring |α |2 + | β |2 = 1 and T T each state qubits [2]. | 0 > = [ 1,0 ] , | 1 > = [ 1,0 ] To record the register state having n qubits are orthonormal basis vectors in the quantum register (Q.R), it requires 2n complex 2-dimensional state space of the qubit. The numbers. For instance quantum register with 3 physical meaning of α and β is that any given qubits requires 23=8 numbers. It is concluded measurement of the qubit will show the 2 that no. of encoded classical states in Q.R system to be in state | 0 >: with probability |β| exponentially grows with corresponding [7]. Another way to express an arbitrary single numbers of qubits. qubit is θ θ |ψ >= eeiiγγφcos|0 >+()+ sin|1 > [6] 3. THE QUANTUM CIRCUIT MODEL 22 Graphical representation of qubits can be Circuits consist of wires holding different shown by sphere with arrow in it, as in the values of bits for transferring to gates which figure below: are responsible to perform different primitive operations on these transferred bits. The circuit depth is known to be total number of time slices only in that case when the circuit can be visualized as being divided into a sequence of discrete time slices subject to the IJSSST Vol. 9 No. 5, December 2008 9 ISSN 1473-804x Online, 1473-8031 Print BABAR et al.: IMPLEMENTING DIMENSIONAL VIEW OF 4X4 LOGIC GATE application of single time slice required by a increase in physical entropy of process then it single gate. Quantum circuitry consists of is termed as physically reversible process, in sequence of quantum gates applied to Q.R. other words its known as isentropic. Moreover Quantum register having size n is made up no one can fix the limit to the closeness with combination of uniquely addressable through which one can approach perfect qubits having individual couplings. Each reversibility. According to Rolf Landauer’s quantum gate carries reversible property Principal “for a computational process to be which incorporates transformation by means physically reversible, it must also be logically of unitary operator between the inputs and reversible”. outputs. Only in that case operator U will be Discrete/deterministic computational process known as unitary when U’U=1. Hence is known as logically reversible if there is quantum circuit can be defined in terms of 1-to-1 mapping between old computational Q.R, to which a finite no. of quantum states to new one and transition function. operations are applied [3]. Probably the main motivation to support reversible computing is to enhance the 4. QUANTUM DECOHERENCE computer power consumption beyond the primary limit of Von Neumann Landauer i.e. The main problem is to keep computer kTln2 energy dissipated per irreversible bit component in coherent state, because the little operation, where T is environment interference from the external world would temperature and the value of Bolt Mann’s effect the system to become decohere. This constant k=1.38 × 10-23 J/K. may cause the computational steps of the quantum computer to be violated. Candidate The implementation of reversible computing system decoherence or de-phasing time at low as stated in Wikipedia “Tends to typify and temperature usually range between seconds control the physical dynamics of mechanisms and nanoseconds. In addition error correction to carry out desired computational operations results in increased number of required qubits so precisely that we can accumulate [7]. insignificant total amount of uncertainty regarding the complete physical state of the 5. REVERSIBLE COMPUTATIONS AND mechanism per each logic operation that is UNCOMPUTATION performed. Alternatively, we need to track the state of the active energy that is involved in It is currently believed that quantum carrying out computational operations within computing is the most general physical model the machine, and to design the machine in of computation, encompassing classical such a way that most of this energy is computation. However, this is apparently recovered in an organized form which can be contradicted by the fact that all quantum reused for subsequent operations, rather than computations are invertible / reversible, to dissipate into the form of heat”. whereas many classical computations are irreversible. 6. REVERSIBLE LOGIC GATES Any computational process which is time invertible can be known as reversible Reversible logic gained much consideration in computing. It refers to a time-reversed version the field of optical computing, quantum of the process that exists within the same computing and low power design.
Load more

Recommended publications
  • EE 434 Lecture 2
    EE 330 Lecture 6 • PU and PD Networks • Complex Logic Gates • Pass Transistor Logic • Improved Switch-Level Model • Propagation Delay Review from Last Time MOS Transistor Qualitative Discussion of n-channel Operation Source Gate Drain Drain Bulk Gate n-channel MOSFET Source Equivalent Circuit for n-channel MOSFET D D • Source assumed connected to (or close to) ground • VGS=0 denoted as Boolean gate voltage G=0 G = 0 G = 1 • VGS=VDD denoted as Boolean gate voltage G=1 • Boolean G is relative to ground potential S S This is the first model we have for the n-channel MOSFET ! Ideal switch-level model Review from Last Time MOS Transistor Qualitative Discussion of p-channel Operation Source Gate Drain Drain Bulk Gate Source p-channel MOSFET Equivalent Circuit for p-channel MOSFET D D • Source assumed connected to (or close to) positive G = 0 G = 1 VDD • VGS=0 denoted as Boolean gate voltage G=1 • VGS= -VDD denoted as Boolean gate voltage G=0 S S • Boolean G is relative to ground potential This is the first model we have for the p-channel MOSFET ! Review from Last Time Logic Circuits VDD Truth Table A B A B 0 1 1 0 Inverter Review from Last Time Logic Circuits VDD Truth Table A B C 0 0 1 0 1 0 A C 1 0 0 B 1 1 0 NOR Gate Review from Last Time Logic Circuits VDD Truth Table A B C A C 0 0 1 B 0 1 1 1 0 1 1 1 0 NAND Gate Logic Circuits Approach can be extended to arbitrary number of inputs n-input NOR n-input NAND gate gate VDD VDD A1 A1 A2 An A2 F A1 An F A2 A1 A2 An An A1 A 1 A2 F A2 F An An Complete Logic Family Family of n-input NOR gates forms
    [Show full text]
  • Application of Logic Gates in Computer Science
    Application Of Logic Gates In Computer Science Venturesome Ambrose aquaplane impartibly or crumpling head-on when Aziz is annular. Prominent Robbert never needling so palatially or splints any pettings clammily. Suffocating Shawn chagrin, his recruitment bleed gravitate intravenously. The least three disadvantages of the other quantity that might have now button operated system utility scans all computer logic in science of application gates are required to get other programmers in turn saves the. To express a Boolean function as a product of maxterms, it must first be brought into a form of OR terms. Application to Logic Circuits Using Combinatorial Displacement of DNA Strands. Excitation table for a D flipflop. Its difference when compared to HTML which you covered earlier. The binary state of the flipflop is taken to be the value of the normal output. Write the truth table of OR Gate. This circuit should mean that if the lights are off and either sound or movement or both are detected, the alarm will sound. Transformation of a complex DPDN to a fully connected DPDN: design example. To best understand Boolean Algebra, we first have to understand the similarities and differences between Boolean Algebra and other forms of Algebra. Write a program that would keeps track of monthly repayments, and interest after four years. The network is of science topic needed resource in. We want to get and projects to download and in science. It for the security is one output in logic of application of the basic peripheral devices, they will not able to skip some masterslave flipflops are four binary.
    [Show full text]
  • Hardware Abstract the Logic Gates References Results Transistors Through the Years Acknowledgements
    The Practical Applications of Logic Gates in Computer Science Courses Presenters: Arash Mahmoudian, Ashley Moser Sponsored by Prof. Heda Samimi ABSTRACT THE LOGIC GATES Logic gates are binary operators used to simulate electronic gates for design of circuits virtually before building them with-real components. These gates are used as an instrumental foundation for digital computers; They help the user control a computer or similar device by controlling the decision making for the hardware. A gate takes in OR GATE AND GATE NOT GATE an input, then it produces an algorithm as to how The OR gate is a logic gate with at least two An AND gate is a consists of at least two A NOT gate, also known as an inverter, has to handle the output. This process prevents the inputs and only one output that performs what inputs and one output that performs what is just a single input with rather simple behavior. user from having to include a microprocessor for is known as logical disjunction, meaning that known as logical conjunction, meaning that A NOT gate performs what is known as logical negation, which means that if its input is true, decision this making. Six of the logic gates used the output of this gate is true when any of its the output of this gate is false if one or more of inputs are true. If all the inputs are false, the an AND gate's inputs are false. Otherwise, if then the output will be false. Likewise, are: the OR gate, AND gate, NOT gate, XOR gate, output of the gate will also be false.
    [Show full text]
  • Delay and Noise Estimation of CMOS Logic Gates Driving Coupled Resistive}Capacitive Interconnections
    INTEGRATION, the VLSI journal 29 (2000) 131}165 Delay and noise estimation of CMOS logic gates driving coupled resistive}capacitive interconnections Kevin T. Tang, Eby G. Friedman* Department of Electrical and Computer Engineering, University of Rochester, PO Box 27031, Computer Studies Bldg., Room 420, Rochester, NY 14627-0231, USA Received 22 June 2000 Abstract The e!ect of interconnect coupling capacitance on the transient characteristics of a CMOS logic gate strongly depends upon the signal activity. A transient analysis of CMOS logic gates driving two and three coupled resistive}capacitive interconnect lines is presented in this paper for di!erent signal combinations. Analytical expressions characterizing the output voltage and the propagation delay of a CMOS logic gate are presented for a variety of signal activity conditions. The uncertainty of the e!ective load capacitance on the propagation delay due to the signal activity is also addressed. It is demonstrated that the e!ective load capacitance of a CMOS logic gate depends upon the intrinsic load capacitance, the coupling capacitance, the signal activity, and the size of the CMOS logic gates within a capacitively coupled system. Some design strategies are also suggested to reduce the peak noise voltage and the propagation delay caused by the interconnect coupling capacitance. ( 2000 Elsevier Science B.V. All rights reserved. Keywords: Coupling noise; Signal activity; Delay uncertainty; Deep submicrometer; CMOS integrated circuits; Intercon- nect; VLSI 1. Introduction On-chip coupling noise in CMOS integrated circuits (ICs), until recently considered a second- order e!ect [1,2], has become an important issue in deep submicrometer (DSM) CMOS integrated circuits [3}5].
    [Show full text]
  • Designing Combinational Logic Gates in Cmos
    CHAPTER 6 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS In-depth discussion of logic families in CMOS—static and dynamic, pass-transistor, nonra- tioed and ratioed logic n Optimizing a logic gate for area, speed, energy, or robustness n Low-power and high-performance circuit-design techniques 6.1 Introduction 6.3.2 Speed and Power Dissipation of Dynamic Logic 6.2 Static CMOS Design 6.3.3 Issues in Dynamic Design 6.2.1 Complementary CMOS 6.3.4 Cascading Dynamic Gates 6.5 Leakage in Low Voltage Systems 6.2.2 Ratioed Logic 6.4 Perspective: How to Choose a Logic Style 6.2.3 Pass-Transistor Logic 6.6 Summary 6.3 Dynamic CMOS Design 6.7 To Probe Further 6.3.1 Dynamic Logic: Basic Principles 6.8 Exercises and Design Problems 197 198 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS Chapter 6 6.1Introduction The design considerations for a simple inverter circuit were presented in the previous chapter. In this chapter, the design of the inverter will be extended to address the synthesis of arbitrary digital gates such as NOR, NAND and XOR. The focus will be on combina- tional logic (or non-regenerative) circuits that have the property that at any point in time, the output of the circuit is related to its current input signals by some Boolean expression (assuming that the transients through the logic gates have settled). No intentional connec- tion between outputs and inputs is present. In another class of circuits, known as sequential or regenerative circuits —to be dis- cussed in a later chapter—, the output is not only a function of the current input data, but also of previous values of the input signals (Figure 6.1).
    [Show full text]
  • 10.3 CMOS Logic Gate Circuits
    11/14/2004 section 10_3 CMOS Logic Gate Circuits blank.doc 1/1 10.3 CMOS Logic Gate Circuits Reading Assignment: pp. 963-974 Q: Can’t we build a more complex digital device than a simple digital inverter? A: HO: CMOS Device Structure Q: A: HO: Synthesis of CMOS Gates HO: Examples of CMOS Logic Gates Example: CMOS Logic Gate Synthesis Example: Another CMOS Logic Gate Synthesis Jim Stiles The Univ. of Kansas Dept. of EECS 11/14/2004 CMOS Device Structure.doc 1/4 CMOS Device Structure For every CMOS device, there are essentially two separate circuits: 1) The Pull-Up Network 2) The Pull-Down Network The basic CMOS structure is: VDD A B C PUN D Inputs Y = f() A,B,C ,D A B PDN Output C D A CMOS logic gate must be in one of two states! Jim Stiles The Univ. of Kansas Dept. of EECS 11/14/2004 CMOS Device Structure.doc 2/4 State 1: PUN is open and PDN is conducting. VDD PUN In this state, the output is Y =0 LOW (i.e., Y =0). PDN State 2: PUN is conducting and PDN is open. VDD PUN In this state, Y =0 the output is HIGH (i.e.,Y =1). PDN Jim Stiles The Univ. of Kansas Dept. of EECS 11/14/2004 CMOS Device Structure.doc 3/4 Thus, the PUN and the PDN essentially act as switches, connecting the output to either VDD or to ground: VDD VDD OR Y =0 Y =VDD * Note that the key to proper operation is that one switch must be closed, while the other must be open.
    [Show full text]
  • ECE 410: VLSI Design Course Lecture Notes (Uyemura Textbook)
    ECE 410: VLSI Design Course Lecture Notes (Uyemura textbook) Professor Andrew Mason Michigan State University ECE 410, Prof. A. Mason Lecture Notes Page 2.1 CMOS Circuit Basics • CMOS = complementary MOS drain source – uses 2 types of MOSFETs gate gate to create logic functions •nMOS source drain nMOS pMOS •pMOS • CMOS Power Supply VDD CMOS – typically single power supply + CMOS VDD logic = – VDD, with Ground reference - logic circuit circuit • typically uses single power supply • VDD varies from 5V to 1V V •Logic Levels VDD logic 1 – all voltages between 0V and VDD voltages – Logic ‘1’ = VDD undefined – Logic ‘0’ = ground = 0V logic 0 voltages ECE 410, Prof. A. Mason Lecture Notes Page 2.2 Transistor Switching Characteristics •nMOS drain Vout nMOS –switching behavior gate • on = closed, when Vin > Vtn Vin nMOS – Vtn = nMOS “threshold voltage” + Vgs > Vtn = on Vgs – Vin is referenced to ground, Vin = Vgs - source • off = open, when Vin < Vtn •pMOS + source pMOS –switching behavior Vsg • on = closed, when Vin < VDD - |Vtp| - pMOS – |Vtp| = pMOS “threshold voltage” magnitude Vin Vsg > |Vtp| = on gate – Vin is referenced to ground, Vin = VDD-Vsg Vsg = VDD - Vin • off = open, when Vin > VDD - |Vtp| drain Rule to Remember: ‘source’ is at • lowest potential for nMOS • highest potential for pMOS ECE 410, Prof. A. Mason Lecture Notes Page 2.3 Transistor Digital Behavior •nMOS drain Vout nMOS Vin Vout (drain) gate Vin nMOS 1 Vs=0 device is ON + Vgs > Vtn = on 0 ? device is OFF Vgs - source •pMOS Vin Vout (drain) pMOS + source 1 ? device is OFF Vsg 0 Vs=VDD=1 device is ON - pMOS Vin Vsg > |Vtp| = on gate Vsg = VDD - Vin Vin drain pMOS Vout VDD off VDD-|Vtp| on Notice: on When Vin = low, nMOS is off, pMOS is on When Vin = high, nMOS is on, pMOS is off Vtn off Æ Only one transistor is on for each digital voltage nMOS ECE 410, Prof.
    [Show full text]
  • Mechanical Computing Systems Using Only Links and Rotary Joints
    Mechanical Computing Systems Using Only Links and Rotary Joints RALPH C. MERKLE ROBERT A. FREITAS JR. TAD HOGG THOMAS E. MOORE MATTHEW S. MOSES JAMES RYLEY March 27, 2019 Abstract A new model for mechanical computing is demonstrated that requires only two basic parts: links and rotary joints. These basic parts are com- bined into two main higher level structures: locks and balances, which suffice to create all necessary combinatorial and sequential logic required for a Turing-complete computational system. While working systems have yet to be implemented using this new approach, the mechanical simplicity of the systems described may lend themselves better to, e.g., microfabri- cation, than previous mechanical computing designs. Additionally, simu- lations indicate that if molecular-scale implementations could be realized, they would be far more energy-efficient than conventional electronic com- puters. 1 Introduction Methods for mechanical computation are well-known. Simple examples include function generators and other devices which are not capable of general purpose (Turing-complete) computing (for review, see [1]), while the earliest example of a design for a mechanical general purpose computer is probably Babbage's Analytical Engine, described in 1837 [2]. One of the very first modern digital computers was a purely mechanical device: the Zuse Z1, completed in 1938 [3]. arXiv:1801.03534v2 [cs.ET] 25 Mar 2019 At a time when silicon-based electronic computers are pervasive, powerful, and inexpensive, the motivation for studying mechanical computer architectures is not immediately obvious. However, many research groups are currently inves- tigating mechanical, electromechanical, and biochemical alternatives to conven- tional semiconductor computer architectures because of their unique potential advantages.
    [Show full text]
  • How to Select Little Logic
    Application Report SCYA049A–April 2010–Revised July 2016 How to Select Little Logic Samuel Lin................................................................................................... Standard Linear and Logic ABSTRACT TI Little Logic devices are logic-gate devices assembled in a small single-, dual-, or triple- gate package. Little Logic devices are widely used in portable equipment, such as mobile phones, MP3 players, and notebook computers. Little Logic devices are also used in desktop computers and telecommunications. Little Logic gates are common components for easy PC board routing, schematic design, and bug fixes that add without taking up significant space. Little Logic devices are offered in several product categories that meet specific requirements of low and ultra-low voltage, and low power. This application report discusses critical characteristics, features, and applications of TI’s newest Little Logic family and package offerings. Contents 1 Introduction ................................................................................................................... 2 2 Little Logic Product Families ............................................................................................... 4 3 Key Concerns in Little Logic Selection .................................................................................. 15 4 System Applications of Little Logic Gates............................................................................... 23 5 Little Logic Package Options/Trend.....................................................................................
    [Show full text]
  • Estimation of Capacitance in CMOS Logic Gates
    Capacitance and Power Modeling at Logic-Level João Baptista Martins *, Ricardo Reis José Monteiro {batista,reis}@inf.ufrgs.br [email protected] II, UFRGS, Porto Alegre, Brazil IST / INESC, Lisboa, Portugal Abstract Accurate and fast power estimation of CMOS static) techniques, e.g. [2]. circuits during the design phase is required to guide Statistical techniques simulate the circuit repeatedly power optimization techniques employed to meet until the power values converge to an average power, stringent power specifications. Logic-level power based on some statistical measures. Probabilistic estimation tools, such as those available in the SIS and techniques propagate input statistics through the circuit to POSE frameworks are able to accurate calculate the obtain the switching probability for each gate in the switching activity under a given delay model. circuit. Probabilistic techniques are employed in the However, capacitance and delay modeling is crude. power estimation tools inside SIS [3] and POSE [4]. The objective of the work described in this paper is to In this paper, we focus on the problem of capacitance investigate how close can logic-level power estimates modeling. This is typically done very simplistically at the get to estimates obtained with circuit-level simulators logic level. We propose to build a more accurate model. such as SPICE. At the logic-level, only the input and output nodes of the We propose new models for the input and output gates are available. We present an equivalent load capacitances of logic gates, taking into account the capacitance model for each external node, computed from gate´s internal capacitances and the interconnect the internal transistor capacitances and the capacitances extracted from layout.
    [Show full text]
  • Fpgas and How Do They Work
    What are FPGAs and how do they work Andre Zibell Julius-Maximilians-Universität Würzburg RD51 electronics school CERN, 5.2.2014 Images: Wikipedia Motivation • FPGA : Field Programmable Gate Array -> can be reprogrammed at any time (unlike ASICs) -> Array of logic gates • A gate implements a basic logic function, like OR, AND, NAND, etc... • Any logic function, complex or not, can be built from a number of interconnected „gates“. • With enough gates (even of a single type) it is possible to build up any type of digital circuitry (Even processors) 2 Images: cbmhardware.de, hackedgadgets.com Digital electronics in the 70’s • Use of may logic gate chips, to perform complex operations • Wire routing difficult and prone to errors • Limited functionality due to available board space 3 Images: wikipedia Evolution of logic density • Development of chips, that contain several (different) logic gates that were cascadable • Programmable Array Logic (PAL, late 70‘s): One-time-programmable interconnection of „dozens of logic gates“ by burning of fuses • Generic Array Logic (GAL, 1985) Replaces several PALs, re-programmable • Complex Programmable Logic Device (CPLD) Contain hundreds of logic gates, devices with hundreds of pins available • -> FPGAs Contain not only many thousand (or million) logic gates, but much more... 4 FPGA Layout • An FPGA contains a very (!) large number of „Configurable Logic Blocks“ (CLB) • A programmable interconnection matrix propagates signals in between blocks • I/O blocks connect to the world outside of the FPGA • This
    [Show full text]
  • Digital Electronics
    Digital Electronic Engineering Name Class Teacher Ellon Academy Technical Faculty Learning Intentions I will learn about TTL and CMOS families of IC's, being able to distinguish between them I will be able to identify single logic gate symbols I will be able to complete Truth Tables for single logic gates and combinational logic circuits I will learn to analyse and simplify combinational logic circuits I will learn what a Boolean expression is and how to write one for a given logic circuit I will learn about NAND gates and I will be able to determine equivalent circuits made from them I will learn to form circuits to given specification Success Criteria I can develop digital electronic control systems by: Designing and constructing complex combinational logic circuits Describing logic functions using Boolean operators Simplifying logic circuits using NAND equivalents Testing and evaluating combinational logic circuits against a specification YENKA is a free program you can download at home to build electronic circuits and help you with your studies http://www.yenka.com/en/Free_student_home_licences/ To access video clips that will help on this course go to www.youtube.com/MacBeathsTech 1 Switching Logic Although it may not always seem like it, electronics and electronic systems are very logical in the way that they work. In the simplest form, if you want a light to come on, then you press a switch. Of course, it gets more complicated than that. Most technological systems involve making more complicated decisions: for example, sorting out bottles into different sizes, deciding whether a room has a burglar in it or not, or knowing when to turn a central heating system on or off.
    [Show full text]