Capacitance and Power Modeling at Logic-Level João Baptista Martins *, Ricardo Reis José Monteiro {batista,reis}@inf.ufrgs.br [email protected] II, UFRGS, Porto Alegre, Brazil IST / INESC, Lisboa, Portugal Abstract Accurate and fast power estimation of CMOS static) techniques, e.g. [2]. circuits during the design phase is required to guide Statistical techniques simulate the circuit repeatedly power optimization techniques employed to meet until the power values converge to an average power, stringent power specifications. Logic-level power based on some statistical measures. Probabilistic estimation tools, such as those available in the SIS and techniques propagate input statistics through the circuit to POSE frameworks are able to accurate calculate the obtain the switching probability for each gate in the switching activity under a given delay model. circuit. Probabilistic techniques are employed in the However, capacitance and delay modeling is crude. power estimation tools inside SIS [3] and POSE [4]. The objective of the work described in this paper is to In this paper, we focus on the problem of capacitance investigate how close can logic-level power estimates modeling. This is typically done very simplistically at the get to estimates obtained with circuit-level simulators logic level. We propose to build a more accurate model. such as SPICE. At the logic-level, only the input and output nodes of the We propose new models for the input and output gates are available. We present an equivalent load capacitances of logic gates, taking into account the capacitance model for each external node, computed from gate´s internal capacitances and the interconnect the internal transistor capacitances and the capacitances extracted from layout. The results we interconnection capacitance. present show an agreement of the logic-level estimates The interconnection capacitance is currently being and SPICE, with less that 10% error. extracted from layout information. We have performed several experiments on (necessarily) simple circuits where power estimates were obtained both using SPICE, 1. Introduction and SIS using the capacitance values obtained through Power consumption is becoming one of the most our model. The results are very promising, with power important design challenges in the design of VLSI differences of less than 10%. circuits. Optimization techniques for low power are being This paper is organized as follows. In Section 2, we employed at all design levels of abstraction. In order to briefly present the capacitance model used for a transistor guide designers and optimization tools, there is a pressing MOSFET. In Section 3, we describe the methodology for need for accurate and fast power estimation tools. calculating the equivalent capacitances associated the During normal operation, the power dissipation of a input and output nodes of logic gates. In Section 4, we CMOS circuit is directly related to the switching activity. describe the experimental setup and the tools used. For a well designed circuit, the total average power can Experimental results are presented in Section 5. In be approximated by the switched-capacitance power [5]. Section 6, we give some conclusions and discuss future This is an underlying assumption of almost all of the research. available power estimation tools at the logic gate and higher levels of abstraction. The average dynamic power consumption of a CMOS circuit is then given by: 2. Mosfet Capacitance Model 1 n The MOSFET transistors exhibit a number of parasitic 2 (1) Power = . f .Vdd .∑ Ci.αi capacitance [6] (Figure 1), which must be accounted for 2 i=1 in circuit design: gate-to-source capacitance (C ), gate- Where f is the clock frequency, V is the supply voltage, GS dd to-drain capacitance (C ), gate-to-bulk capacitance C and α are capacitance load and average switching of GD i i (C ), source-to-bulk capacitance (C ) and drain to bulk the logic gate i, respectively. GB SB capacitance (C ). In this work, our interest will be the Significant amount of work has been carried out in DB switching region of the transistors and all the developing efficient techniques to estimate the switching capacitances will be considered, with the exception of activity of a CMOS circuit [9]. These techniques can be C . divided into two classes: statistical techniques (also GB Although these capacitances are a nonlinear function known as dynamic techniques), e.g. [1]; probabilistic (or * This researcher was supported by UFSM and CAPES/Brazil. of the voltage, the general approach is to assume them as A. CMOS Inverter a linear, time-invariant element. Given some technology The CMOS inverter (Figure 2) presents two externals parameters and the size the transistor (W/L), a value for nodes. In this case, equivalent capacitances at the input x. each of these parasite capacitances can be computed [6]. Cin x, and output y, Cout y, nodes can be simply computed using: Figure 1- Parasites Capacitances of the MOSFET For definition [6]: (a) CG = Cox LW + 2Co (2) 1 C = G = C (WL) + C (3) GD GS 2 ox o C DB,bot = K (Vl )C j0 AD (4) C = K (V )C l (5) (b) DB,sw 1/ 3 l jsw D Figure 2 – Parasite capacitances of CMOS inverter C DB = C DB,bot + C DB,sw (6) (a) Transistor-level representation (b) Logic-level representation CSB,bot = K(Vl )C j0 AS (7) CSB,sw = K1/ 3 (Vl )C jswlS (8) Cinx =CGSp +CGDp +CGSn +CGDn (10) CSB = CSB,bot + CSB,sw (9) (11) Couty =CDBp +CGDp +CGDn +CDBn where: L = channel length B. 2 -Input CMOS NAND Gate W = channel width In the case of a CMOS 2-input NAND gate (figure 3), Co = overlap capacitance there are two inputs nodes with concentrate capacitance Cj0 = zero bias capacitance per unit area and one output node. The additional difficulty is that we Cjsw = zero-bias sidewall capacitance per unit now have internal capacitance modeling. We analyze the perimeter equivalent capacitance from superposition of the signals. AD = Area of dreno For example, when calculate the equivalent capacitance lD = perimeter of dreno to a input node, the inputs and output will be in the AS = Area of source ground level. The capacitance of internal nodes LS = perimeter of source depends on the logic value of the others inputs. To model this effect we are assuming a probability of 0.5 that all inputs are set to 1. That is, the NMOS transistors will be ON at half the time. 3. Modeling Gate Input and Output Capacitances For circuits described at the logic level there is only access to the logic gates input and output nodes. Therefore, all capacitances internal to the gate have to be taken into account in concentrated capacitance models at these external nodes. In this section we describe how we compute the equivalent capacitance load for any logic gate from its transistor level description. and CAgate is: C A3,N * CT ,N C Agate = p0 (C A1,N + ) + C A3,N + CT ,N + p1 (C A1,N + C A3,N ) + C A1,P + C A3,P (17) where p0 is probability second input to be equal the ZERO and p1 is probability second input to be equal the ONE (p0 + p1 = 1). Input “b” In the same form, can analyses the second input. (a) For input combinations 00 and 01, the mn1 transistor is OFF and Cb1 is equal: CB1,N * CT1,N Cb1,N = 0.5(CB3,N + ) (18) CB1,N + CT1,N (b) For input combinations 10 and 11, the mn1 transistor is Figure 3 – Parasite Capacitances of 2-input NAND ON and CB2 is equal: (a) Transistor-level representation C = 0.5(C + C ) (19) (b) Logic-level representation b2,N B1,N B3,N Then In the case NAND2, the input combination possible is 00, 01, 10 and 11. CB,N = Cb1,N + Cb2,N (20) Input “a”: CB1,N * CT1,N CB,N = 0.5(CB3,N + ) + 0.5(CB1,N + CB3,N ) For input combinations 00 and 10, the “mn2” CB1,N + CT1,N transistor is OFF and equivalent capacitance node (C ) a1 (21) is equal: CT1,N = C A4,N + C A3,N + C B2,N (22) CA3,N * CT ,N Ca1 = 0.5(CA1,N + ) (12) CA3,N + CT ,N In terms probabilistics : CB1,N * CT1,N CT ,N = CA4,N + CB1,N + CB2,N (13) CB,N = p0 (CB3,N + ) + p1 (CB1,N + CB3,N ) CB3,N + CT1,N For input combinations 01 and 11, the mn2 transistor is ON and equivalent capacitance (Ca2 ) is equal: (23) Ca2 = 0.5(CA1, N + CA3,N ) (14) and CBgate is: Then CB1,N * CT1,N CBgate = p0 (CB3,N + ) + CB1,N + CT1,N CA,N = Ca1 + Ca2 + p1 (C B1,N + CB3,N ) + C B1,P + C B3,P (24) CA3,N * CT ,N CA,N = 0.5(CA1,N + ) + 0.5(CA1,N + CA3,N ) CA3,N + CT ,N Where: CAgate and CBgate are equivalent capacitances for input A (15) and input B, respectively. In terms probabilistics: And output is: C A3,N * CT ,N Cout = C A1,N + C A2,N + C A3,P + C A4,P + C B3,P + C B4,P C A,N = p0 (C A1,N + ) + p1 (C A1,N + C A3,N ) C A3,N + CT ,N (25) (16) C. NAND with n-inputs CTi(0) = CSB(0) + CGD(1) + CDB(1) (27) These considerations also are valid for CMOS For q=1 to n-2 NAND´s with n inputs, where n is an integer number and q probability=0.5. This case one input is switching and CTi(q) = CTi(0) + ∑ (CGS(i) + CSB(i) + CGD(i+1) + C DB(i+1) ) others inputs assume 0 or 1 values.