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ECSE-4760 Real-Time Applications in Control & Communications

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ECSE-4760 Real-Time Applications in Control & Communications Rensselaer Polytechnic Institute ECSE-4760 Real-Time Applications in Control & Communications EXPERIMENTS IN DIGITAL LOGIC DESIGN Number of Sessions – 4 INTRODUCTION Over the past few decades the digital world has come into its own. Even though engineering has gone into specialization, it is necessary to understand digital circuits to be able to communicate with others. This experiment attempts to teach a simple method of designing digital circuits. Due to the quick pace of the lab, it is highly recommended that you read one of the references. This will enable you to proceed quickly through the preliminary problems so you will have more time for the design problems. The following is an outline of the experiment. Following each section will be a set of questions that should be answered to show an understanding of the material presented. Any difficulties should be referred to a reference or your instructor. You should use the DesignWorks (LogicWorks or any other you may have) logic circuit simulator on the Macintosh after most sections to cement together all the preceding sections. BACKGROUND THEORY Boolean Algebra Switching Algebra Combinational Logic Minimization Flip-Flops and Registers Counters Synthesis of Synchronous Circuits EXPERIMENTAL PROCEDURE Questions and Problems Simulator Operation & FPGA Implementation REFERENCES It is required that you show all circuits, as built, in your write-up. Please include equations too. The first part of the procedure section contains all the questions and problems to be answered and the second part describes the use of DesignWorks. Note: all references to DesignWorks (on Macintosh computers) throughout this procedure may be replaced with LogicWorks on the lab Windows PCs. 1 BACKGROUND THEORY Since the digital world consists of discrete levels, functions can be described in truth tables as opposed equations for the continuous world. The three basic digital functions are AND, OR, and NOT. Their symbols and truth tables are shown below. These functions (from now on called gates) are such that as soon as the inputs change, the outputs will also change. (There actually is a small delay dependent on the type of gate. See reference [1].) INPUT OUTPUT A B F A 0 0 0 F B 0 1 0 1 0 0 1 1 1 FIGURE 1. AND gate and truth table. INPUT OUTPUT A B F A 0 0 0 F B 0 1 1 1 0 1 1 1 1 FIGURE 2. OR gate and truth table. INPUT OUTPUT A F A F 0 1 A F 1 0 FIGURE 3. NOT gate and truth table. Very often an OR and AND gate will have a NOT at the end of it (because of hardware considerations). These will then be called NOR and NAND gates respectively. Please do problem 1 in the QUESTIONS AND PROBLEMS of the EXPERIMENTAL PROCEDURE. BOOLEAN ALGEBRA George Boole (1815-64) introduced an algebra of logic in the mid-1800's, however, the present- day application of Boolean algebra is credited to a paper by C. Shannon in 1938. The techniques and manipulations provided by Boolean Algebra are a necessity to efficient logic design. A. Definition A set of elements B and two binary operations '+' and '·' over B form a Boolean Algebra {B, +, ·} if and only if the following postulates hold: 2 Postulate 1 - The set of B objects or elements are subject to an equivalence relationship, denoted '=', which satisfies the principle of substitution, i.e., if A = B, A may be substituted for B in any expression involving B without affecting the validity of the expression. As in ordinary algebra, the letters of the alphabet are used to represent variables. Postulate 2 (Closure) - Whenever A, B ∈ B then (A + B) ∈ B (A · B) ∈ B Postulate 3 (Identity) - There exist two identity elements (called 0 and 1) such that: 0 + A = A + 0 = A (additive identity) 1 · A = A · 1 = A (multiplicative identity) Postulate 4 - '+' and '·' are: i. commutative A + B = B + A A · B = B · A ii. associative A + (B + C) = (A + B) + C A · (B · C) = (A · B) · C iii. distributive over each other A · (B + C) = (A · B) + (A · C) A + (B · C) = (A + B) · (A + C) Postulate 5 - For every element A in B there exists an element A (termed the complement of A) such that: A + A = 1 A ⋅ A = 0 € Postulate 6 - There are at least two elements X and Y in B such that X ≠ Y. B. Theorems € 1. The 0 and 1 elements are unique. 2. For every element A in B: A + A = A and A · A = A 3. A + 1 = 1 and A · 0 = 0 4. The elements 0 and 1 are distinct and 1 = 0 or 0 = 1. 5. A + AB = A and A · (A + B) = A. This is often termed the absorption rule. (The '·' is understood, thus A · B = AB) 6. A = (A ) = A € € 7. A + A B = A + B and A ⋅ (A + B) = AB 8. (A + B) ⋅ (A + C) = AC + A B and AB + BC + A C = AB + A C 9. DeMorgan's Theorem € AB = A + B € € € A + B = A ⋅ B € C. Duality € Notice that the previous postulates and theorems were given in pairs. In each case one postulate in a pair can be obtained from the other by interchanging 0 and 1 along with '+' and '·'. This is called the principle of duality. Every theorem which can be proven for Boolean algebra has a dual which is also true. For example: A + 0 = A A · 1 = A and A + (B · C) = (A + B) · (A + C) A · (B + C) = (A · B) + (A · C) 3 SWITCHING ALGEBRA Switching algebra is a mathematical framework for the design and analysis of logic networks using binary decision-making elements such as NAND and NOR gates. The distinctive feature is that variables and functions can assume only two values, 0 and 1. Thus Switching algebra is a subset of Boolean algebra restricted to two elements (B = 0, 1). Switching algebra will provide a means of describing functional relationships in a form that corresponds precisely to a network of gates. A. Properties of Switching Algebra 1. Distinctness of 0 and 1 X ≠ 0 if and only if X = 1 X ≠ 1 if and only if X = 0 2. Operations AND, '·' 0 · 0 = 0 0 · 1 = 1 · 0 = 0 1 · 1 = 1 OR, '+' 0 + 0 = 0 0 + 1 = 1 + 0 = 1 1 + 1 = 1 NOT, '"" ' 1 = 0 0 = 1 The associative law allows us to extend definitions of AND and OR to many variables. Thus for Z =€ A + B + C + D + E, then Z = 1 if any of A, B, C, D, or E is 1, in any combination. Similarly Z =€ ABCDE is 1 if and only if all the variables A, B, C, D, and E are 1. B. DeMorgan's Theorem The two basic duals of the theorem are: XY = X + Y X + Y = X ⋅Y DeMorgan's theorem as well as other theorems can be extended to many variables: ABCDE... A B C D E ... € = + + + + + A B C ... A B C ... € + + + = ⋅ ⋅ ⋅ DeMorgan's theorem expresses a relationship between AND and OR that is important to € recognize. Consider the equation Z = A + B + C. We could interpret this as Z = 1 when A or B or C is € 1. An alternative is Z = 0 if A and B and C are 0. This is represented by Z = A ⋅ B ⋅C which is equivalent to Z = A + B + C by DeMorgan's theorem. All this leads to the need to realize that a gate can be realized by its dual using DeMorgan's € theorem. Some examples are as follows: 4 AND version OR version A A F = AB F F = A + B F B ! ! ! B A circle represents a NOT. A A F = AB!! B F F =!A +!B B F A A !F =!A!B F F = A +B F B B FIGURE 4. It is important to note that AB and A ⋅ B are not equivalent expressions. The truth table for both is shown below. INPUT OUTPUT € € __ __ ____ _ _ A B A B A B AB 0 0 1 1 1 1 0 1 1 0 1 0 1 0 0 1 1 0 0 0 1 1 0 0 FIGURE 5. Answer question 2 in the QUESTIONS AND PROBLEMS of the EXPERIMENTAL PROCEDURE. COMBINATIONAL LOGIC Combinational logic refers to networks whose outputs depend solely on their inputs, and not on any previous state. The analysis of combinational logic requires the writing of the Boolean algebra equation for each element of the network, and then combining these for the final output equation. For example: A EE = =AB A BC C B E 1 1 1 ! !C EE = =A AB!CB C F 2 2 A F = E + E E 3 = E11 + E22 !B C E 2 FF= =AB A BC!+C A +B CA!B C FIGURE 6. The truth table is: € 5 INPUT OUTPUT A B C F Sequence 0 0 0 0 !ABC ! ! 0 0 1 0 !ABC ! 0 1 0 0 ABC! ! 0 1 1 0 ABC! 1 0 0 0 ABC! ! 1 0 1 1 ABC! 1 1 0 1 ABC! 1 1 1 0 ABC FIGURE 7. DeMorgan's theorem states that AB = A + B . Therefore a NAND gate is also a NOT OR gate, as shown below. A A F F B € 1 B 2 F = AB F = A + B F 1 = AB!!! F 2 =!A +!B FIGURE 8. When analyzing NAND circuits, a NOTed-OR can be substituted in place of a NAND gate. This is usually done€ at odd levels as shown below. € A A E 1 E 1 B B F 1 F 2 C C D E D E 2 __ 2 E 1 = AB E1 = AB __ E 2 = CD E 2 = CD ______ __ F1 = AB CD = AB + CD = F 2 F1 = AB CD = AB + CD = F2 FIGURE 9.
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