Design and Simulation of V&Pl Submodules Using Nand And

Home , AND gate, NAND gate, NAND logic, NOR gate, NOR logic

DESIGN AND SIMULATION OF V&PL SUBMODULES USING NAND AND NOR GATE

H.Hasim, Syirrazie CS Instrumentation and Automation Center, Technical Support Division, Malaysia Nuclear Agensi 43000, Bangi, Kajang, Selangor

Abstract Digital Integarted Circuit(IC) design is an alternative to current analog IC design. Both have vise verse advan- tages and disadvantages. This paper investigate and compare sub-modules of voting and protecting logic (V&PL) using only two input either NAND gate(74LS00) or NOR gate (74LS02). On the previous research, V&PL submodule are mixed of six input NOR gate, 2 input AND gate, and Inverter. The result show a complexity of circuity and diﬃculty of ﬁnding six input NOR gate. We extend this analysis by comparable of less complexity of PMOS and NMOS used in NAND and NOR gate as V&PL sub-module, less time propagation delay, with high frequency and less total nombor of transistor used. Kanaugh map minimizer, logisim, and LTSpice used to design and develop of V&PL sub-module Complementary Metal Oxide Semiconductor(CMOS) NAND and NOR gate.Result show that, propagation delay of NAND gate is less with high frequency than NOR gate.

Keywords: CMOS, NOR gate, NAND gate, Voting and Protecting Logic(V&PL)

1 Introduction

One of the key challenges in IC design is making used of transistor. Transistor can be either biasing and funtion as amplifier or operated in saturated and cut-off region. To be digitalize, transistor will operated in saturated and cut-off region. The saturated region is when the flat or staedy-state amount of voltage throught out of time while in cut-off region it is approximately zeros volt. Fig. 1 define each region of transistor.

Figure 1: Region of Operation

Every CMOS gate consist of PMOS and NMOS.CMOS NAND and NOR gate are show on Fig. 2. We can easily distanguse both with the connection type which are either in series or parallel. Both gates are tend to be simple

1 design compare to other gate. More-over, both are universal gate. Fig. 3 show NAND and NOR is used as function as AND, OR, and inverter. However the diﬃculty is when we need to design sub-module circuit using NAND or NOR gate only. 74LS00 and 74LS02 are the four NAND gates with two input and four NOR gates with two input.

Figure 2: (i) Two Input NOR Gate (ii) Two Input NAND Gate

V&PL submodules operated only when there is any two input are trigger high with logic ”1”. It can be say as 2004 function, where-by 2 is represented two logic input trigger with high level, 00 is the others two logic input out of 4 are trigger low logic level and 4 is the total number of input of V&PL submodule. The input of V&PL are connected to channel 1 up to channel 4. Each channel is the output sensor while output of V&PL connected to ﬁnal actuator logic(FAL). Redundancy is applied for safety purposes.

Figure 3: Show Implementation of Inverting, OR, and AND Gate Using Either NAND or NOR Gate

2 Design of V&PL Submodule

Truth table is the main theory behind any digital system. These V&PL truth table have only 4 input(A,B,C, and D) with one output which is X. The output level will trigger high when any two or more of input are high level. Table. 1 show the truth table of V&PL submodule. From this truth table, all logic ”1” and ”0” are represented in Karnaugh Map Minimizer(k-map). Thus boolean expression of output(x) can be summarized. From the truth table, when the output (x) is hgh level, the equestion will be :

X = 0011 + 0101 + 0110 + 0111 + 1001 + 1010 + 1011 + 1100 + 1101 + 1110 + 1111 (1)

2 Table 1: Truth Table of V&PL Submodule

X = A¯BCD¯ + AB¯ CD¯ + ABC¯ D¯ + ABCD¯ + AB¯CD¯ + ABC¯ D¯ + ABCD¯ + ABC¯D¯ + ABCD¯ + ABCD¯ + ABCD (2) While the output(x) is low level, the equestion will be :

X = (0 + 0 + 0 + 0)(0 + 0 + 0 + 1)(0 + 0 + 1 + 0)(0 + 1 + 0 + 0)(1 + 0 + 0 + 0) (3)

X = (A¯ + B¯ + C¯ + D¯)(A¯ + B¯ + C¯ + D)(A¯ + B¯ + C + D¯)(A¯ + B + C¯ + D¯)(A + B¯ + C¯ + D¯) (4) K-Map Minimizer was used to simplified and minimize all the above equestion. Fig. 4 show K-Map Minimizer simplified equestion (2) and (4). both high level and low level can be minimize and summaries. Direct implementation using equestion (2), will involve eleven AND gate with four input and one OR gate with six input. While, for the equestion (4), the direct implementation will involve five OR gate with four input and one AND gate with five input. However, beside k-map minimizer we also can used boolean algebric law and rules.

Figure 4: K-Map Minimizer of NAND and NOR Gate

3 2.1 NAND gate of V&PL submodule From Fig. 4(i), the simpliﬁcation of equestion will be:

X = CD + BD + BC + AB + AD + AC (5) When applying eular boolean algebric law and rule, output x will be :

X = CD + BD + BC + AB + AD + AC (6) The main target is to used two input NAND gate only in this V&PL submodules. However, the challanges is to design six input NAND gate using only two input NAND gate. Thus, by applying boolean rule and law on equestion (6), an illustrated of Sea of Gate(SOG) V&PL submodule using NAND gate as on Fig. 5.

Figure 5: SOG of V&PL Submodules Using NAND gate

2.2 NOR gate of V&PL submodule While from Fig. 4(ii), the simpliﬁcation of equestion will be:

X = (A + B + C)(A + B + D)(A + C + D)(B + C + D) (7) However to simpliﬁed further more, the output (X) will be:

X = (A + B + C)(A + B + D)(A + C + D)(B + C + D) (8) Only two input NOR gate had been used to design V&PL submodule. However, the diﬃculty is to design three and four input NOR gate using only two input NOR gate. Thus, by applying boolean eular rule and law on equestion (8), an illustrated of Sea of Gate(SOG) V&PL submodule using NOR gate as on Fig. 6.

Figure 6: SOG of V&PL Submodules Using NOR gate

4 3 Simulation-Set Up and Result

There are two types of device under test(DUT) had been used to verify and finding the design output. The first DUT had been used was SOG NAND. While on second DUT had been used was SOG NOR. The first verification is to check structurer and functional. While the second result, is to find the number of gate, PMOS, NMOS, and transistor used. Further more, propagation delay and frequency also will be find. The time1 of input output of each NAND and NOR gate is tabulated on Table. 2.

Table 2: Time Propagation From High to Low and Low to High Level of NAND and NOR Gate Propagation Delay Types of Gate NAND (ns) NOR (ns) tP LH 0.108 0.173 tPHL 0.129 0.085

3.1 DUT of V&PL Submodules Using NAND Gate

Figure 7: DUT of V&PL Submodule Using NAND Gate

Based on Fig. 7 above,( A,B,C, and D) are the input of DUT. More-over it had one output port with VSS connected to ground. The transient time is test at 100us. The input D is connected to VDD which is 5V. The input (A,B, and C) are the pulse wave with rise and fall time of 1ns. While on Fig. 8, the input and output waveform produce from out DUT of V&PL using NAND gate. Based on waveform, found that this design and circuit structural and function correctly. The output trigger logic level high when any two or more of the input are logic level high. Counting of gate in Fig. 5, PMOS and NMOS will be 34 with total number of 64 transistor. The 17 NAND logic gate was used. To ﬁnd Propagation delay and frequency, the mathematical equestion below had been used. 1 t = (t + t ) (9) PD 2 P LH PHL

1 tPD = 2 (0.108 + 0.129)

tPD = 0.119 ns perNANDgate.

Total propagation delay of V&PL submodule using NAND gate is 2.015 ns. 1 f = (10) tPD

1 f = 2.015 f = 496.401MHz

5 Figure 8: DUT Waveform of V&PL Submodule Using NAND Gate

3.2 DUT of V&PL Submodules Using NOR Gate Looking on Fig. 10, the input and output waveform produce from out DUT of V&PL using NOR gate. Look on waveform, found that this design and circuit structural and function correctly. The output trigger logic level high when any two or more of the input are logic level high. Finding number of gate in Fig. 6, PMOS and NMOS will be 34 with total number of 64 transistor. The 17 NOR logic gate was used. Propagation delay and frequency been calculated base on equestion (9) and (10).

1 tPD = 2 (0.173 + 0.085)

tPD = 0.129 ns perNORgate.

While the total propagation delay of V&PL submodule using NOR gate is 2.193 ns and the frequency is:

1 f = 2.193 f = 455.996MHz

Figure 9: DUT Waveform of V&PL Submodule Using NOR Gate

4 Conclusion

This article design, simulated and comparing both V&PL submodules either using two input NAND gate or two input NOR gate. The design complexity are based on count of the number of gate, transistor, PMOS, and NMOS used. Table. 3 comparing characteristic of both NAND and NOR gate of V&PL submodules. In conclusion, NAND SOG is more suitable for high speed and less propagation delay per gate and per V&PL of V&PL submodule compare to NOR. While both had same desgn complexity circuit. The trade-oﬀ of NORgate can be improve future and expend study on static and dynamic power of both gates.

6 Table 3: Comparion of NAND and NOR SOG Characteristic as V&PL Submodule Characteristic Types of Gate NAND (ns) NOR (ns) Total No. of Gate 17 17 Total No. of PMOS 34 34 Total No. of NMOS 34 34 Total No. of Transistor 68 68 Time Propagation Delay Per Gate 0.119 ns 0.129 ns Time Propagation Delay Per V&PL 2.015 ns 2.153 ns Frequency of V&PL 496.401 MHz 455.996 MHz

References

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