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Static CMOS Circuits Static CMOS Circuits • Conventional (ratio-less) static CMOS – Covered so far • Ratio-ed logic (depletion load, pseudo nMOS) • Pass transistor logic ECE 261 Krish Chakrabarty 1 Example 1 module mux(input s, d0, d1, output y); assign y = s ? d1 : d0; endmodule 1) Sketch a design using AND, OR, and NOT gates. ECE 261 Krish Chakrabarty 2 1 Example 1 module mux(input s, d0, d1, output y); assign y = s ? d1 : d0; endmodule 1) Sketch a design using AND, OR, and NOT gates. ECE 261 Krish Chakrabarty 3 Example 2 2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available. ECE 261 Krish Chakrabarty 4 2 Example 2 2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available. ECE 261 Krish Chakrabarty 5 Bubble Pushing • Start with network of AND / OR gates • Convert to NAND / NOR + inverters • Push bubbles around to simplify logic – Remember DeMorgan’s Law ECE 261 Krish Chakrabarty 6 3 Example 3 3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available. ECE 261 Krish Chakrabarty 7 Example 3 3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available. ECE 261 Krish Chakrabarty 8 4 Compound Gates • Logical Effort of compound gates ECE 261 Krish Chakrabarty 9 Example 4 • The multiplexer has a maximum input capacitance of 16 units on each input. It must drive a load of 160 units. Estimate the delay of the NAND and compound gate designs. H = 160 / 16 = 10 B = 1 N = 2 ECE 261 Krish Chakrabarty 10 5 NAND Solution ECE 261 Krish Chakrabarty 11 NAND Solution ECE 261 Krish Chakrabarty 12 6 Compound Solution ECE 261 Krish Chakrabarty 13 Compound Solution ECE 261 Krish Chakrabarty 14 7 Example 5 • Annotate your designs with transistor sizes that achieve this delay. Informal homework exercise (see textbook)! ECE 261 Krish Chakrabarty 15 Input Order • Our parasitic delay model was too simple – Calculate parasitic delay for Y falling • If A arrives latest? • If B arrives latest? ECE 261 Krish Chakrabarty 16 8 Input Order • Our parasitic delay model was too simple – Calculate parasitic delay for Y falling • If A arrives latest? 2 • If B arrives latest? 2.33 ECE 261 Krish Chakrabarty 17 Inner & Outer Inputs • Outer input is closest to rail (B) • Inner input is closest to output (A) • If input arrival time is known – Connect latest input to inner terminal ECE 261 Krish Chakrabarty 18 9 Asymmetric Gates • Asymmetric gates favor one input over another • Ex: suppose input A of a NAND gate is most critical – Use smaller transistor on A (less capacitance) – Boost size of noncritical input – So total resistance is same • gA = 10/9 • gB = 2 • gtotal = gA + gB = 28/9 • Asymmetric gate approaches g = 1 on critical input • But total logical effort goes up ECE 261 Krish Chakrabarty 19 Symmetric Gates • Inputs can be made perfectly symmetric ECE 261 Krish Chakrabarty 20 10 Skewed Gates • Skewed gates favor one edge over another • Ex: suppose rising output of inverter is most critical – Downsize noncritical nMOS transistor • Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. – gu = – gd = ECE 261 Krish Chakrabarty 21 Skewed Gates • Skewed gates favor one edge over another • Ex: suppose rising output of inverter is most critical – Downsize noncritical nMOS transistor • Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. – gu = 2.5 / 3 = 5/6 – gd = 2.5 / 1.5 = 5/3 ECE 261 Krish Chakrabarty 22 11 HI- and LO-Skew • Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition. • Skewed gates reduce size of noncritical transistors – HI-skew gates favor rising output (small nMOS) – LO-skew gates favor falling output (small pMOS) • Logical effort is smaller for favored direction • But larger for the other direction ECE 261 Krish Chakrabarty 23 Catalog of Skewed Gates ECE 261 Krish Chakrabarty 24 12 Catalog of Skewed Gates ECE 261 Krish Chakrabarty 25 Catalog of Skewed Gates ECE 261 Krish Chakrabarty 26 13 Asymmetric Skew • Combine asymmetric and skewed gates – Downsize noncritical transistor on unimportant input – Reduces parasitic delay for critical input ECE 261 Krish Chakrabarty 27 Best P/N Ratio • We have selected P/N ratio for unit rise and fall resistance (μ = 2-3 for an inverter). • Alternative: choose ratio for least average delay • Ex: inverter – Delay driving identical inverter – tpdf = – tpdr = – tpd = – Differentiate tpd w.r.t. P – Least delay for P = ECE 261 Krish Chakrabarty 28 14 Best P/N Ratio • We have selected P/N ratio for unit rise and fall resistance (μ = 2-3 for an inverter). • Alternative: choose ratio for least average delay • Ex: inverter – Delay driving identical inverter – tpdf = (P+1) – tpdr = (P+1)(μ/P) – tpd = (P+1)(1+μ/P)/2 = (P + 1 + μ + μ/P)/2 – Differentiate tpd w.r.t. P – Least delay for P = ECE 261 Krish Chakrabarty 29 P/N Ratios • In general, best P/N ratio is sqrt of that giving equal delay. – Only improves average delay slightly for inverters – But significantly decreases area and power ECE 261 Krish Chakrabarty 30 15 Observations • For speed: – NAND vs. NOR – Many simple stages vs. fewer high fan-in stages – Latest-arriving input • For area and power: – Many simple stages vs. fewer high fan-in stages ECE 261 Krish Chakrabarty 31 Combinational vs. Sequential Logic Ou t Lo gic In Lo gic In Ou t Circuit Circuit State (a)Co m b ina tion a l (b)Se qu e ntial Outpu t= f(In) Outpu t= f(I n,Pr eviou s In) ECE 261 Krish Chakrabarty 32 16 Static CMOS Circuit (Review) At every point in time (except during the switching transients) each gate output is connected to either VDD or V ssvia a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. ECE 261 Krish Chakrabarty 33 Static CMOS (Review) VD D In 1 In 2 PUN PMO S On ly In 3 F=G In 1 In 2 PDN NM O S On ly In 3 VSS PUN and PDN are Du alNe tw ork s ECE 261 Krish Chakrabarty 34 17 Properties of Complementary CMOS Gates (Review) Highno isema rgins: VOHandVOL are atVDD andGN D ,re s pec t ively . No stati cpower co nsump ti on: Ther e nev er ex ists adire c t pa th be t w e e n VD D and VSS(GN D ) inste a dy -s ta te mode. Comp arable riseandfa lltime s : (u nder th eappr o priate sca lin gco nditions) ECE 261 Krish Chakrabarty 35 Influence of Fan-In and Fan-Out on Delay VD D A B C D Fa n -Ou t:Nu m b e rofGa tes Co n n e c ted Every fanout (output) adds two gate capacitances (pMOS and nMOS) A B Fa n In:Qu a d r aticTe r mdu e to: C 1.Re sistan c eInc rea s ing D 2.Ca p a c itan c e Inc r ea s ing a 2+ tp = a1 FI+ 2FI a3 FO ECE 261 Krish Chakrabarty 36 18 Fast Complex Gate-Design Techniques •Tr a nsisto rSizing: As lo ng as Fa n-o utCapacita nce domin ate s •Pro gre ssive Sizing: Ou t In N MN CL M1 >M2 >M3 >MN C3 In 3 M3 C In 2 M2 2 In 1 M1 C1 ECE 261 Krish Chakrabarty 37 Fast Complex Gate - Design Techniques •Tr a nsisto rOr d ering criticalpath criticalpath C In L CL 3 M3 In1 M1 C In M2 2 C2 2 In2 M2 In C1 C 1 M1 In3 M3 3 (a) (b) ECE 261 Krish Chakrabarty 38 19 Fast Complex Gate - Design Techniques •Im proved Logic De sign ECE 261 Krish Chakrabarty 39 Ratioed Logic VD D VD D VD D Resistiv e Dep le tio n PM O S Lo ad RL Lo ad VT<0 Lo ad VSS F F F In 1 In 1 In 1 In 2 PD N In 2 PD N In 2 PD N In 3 In 3 In 3 VSS VSS VSS (a )re sistiv e lo a d (b )de p letio n lo a d NM O S (c )pse u d o -N M O S Go a l:to re d u c eth e nu m b e rofde v ic esov ercom p le me nta r y CM O S Careful design needed! ECE 261 Krish Chakrabarty 40 20 Ratioed Logic VD D •VO H=VD D RPDN Resistive VOL = VDD RL + RPDN Load RL Desired: RL >> RPDN (to keep noise margin low) F t = 0.69R C In1 PLH L L In2 PDN RPDN In3 Problems: 1) Static power dissipation 2) Difficult to implement a large VS S resistor, eg 40k resistor (typical value) needs 3200 μ2 of n-diff, i.e. 1,000 transistors! ECE 261 Krish Chakrabarty 41 Active Loads VD D VDD Depletion PMOS Load VT <0 Load VS S F F In1 In1 In2 PDN In2 PDN In3 In3 VS S VS S dep letion load NM O S pseu do-N M O S • Depletion-mode transistor has negative threshold • On if VGS = 0 • Body effect may be a problem! ECE 261 Krish Chakrabarty 42 21 Pseudo-nMOS VD D F C A B C D L • No problems due to body effect • N-input gate requires only N+1 transistors • Each input connects to only a single transistor, presenting smaller load to preceding gate • Static power dissipation (when output is zero) • Asymmetric rise and fall times Example: Suppose minimal-sized gate consumes 1 mW of static power.
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