DOCSLIB.ORG

Voltage Controlled Memristor Threshold Logic Gates, 2016 IEEE APCCAS, Jeju, Korea, October 25-28, 2016

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Voltage Controlled Memristor Threshold Logic Gates, 2016 IEEE APCCAS, Jeju, Korea, October 25-28, 2016 A. Maan, A. P. James, Voltage Controlled Memristor Threshold Logic Gates, 2016 IEEE APCCAS, Jeju, Korea, October 25-28, 2016 Voltage Controlled Memristor Threshold Logic Gates Akshay Kumar Maan Alex Pappachen James Queensland Microelectronic Facility School of Engineering, Nazabayev University Griffith University Astana, Kazakhastan Queensland 4111, Australia Web: www.biomicrosystems.info/alex Email: [email protected] Email: [email protected] Abstract—In this paper, we present a resistive switching weights to the inputs, while the CMOS inverter behaves as memristor cell for implementing universal logic gates. The cell a threshold logic device. The weights are programmed via has a weighted control input whose resistance is set based on a the resistive switching phenomenon of the memristor device. control signal that generalizes the operational regime from NAND We show that resistive switching makes it possible to use the to NOR functionality. We further show how threshold logic in same cell architecture to work in the NAND, NOR or XOR the voltage-controlled resistive cell can be used to implement a configuration, and can be implemented in a programmable XOR logic. Building on the same principle we implement a half adder and a 4-bit CLA (Carry Look-ahead Adder) and show array architecture. We hypothesise that if such circuits are that in comparison with CMOS-only logic, the proposed system developed in silicon that can be programmed and reused to shows significant improvements in terms of device area, power generate different logic gate functionalities, we will be able to dissipation and leakage power. move a step closer towards the development of low power and large scale threshold logic applications. I. INTRODUCTION A. Proposed Logic The discovery of the physical memristor, the fourth basic circuit element, as theorised by Leon Chua in 1971 [1], by Hewlett-Packard Laboratories [2], has refocussed the research on memristive systems. The memristor device exhibits a re- sistive switching phenomenon in which a dielectric suddenly changes its (two terminal) resistance under the action of a strong electric field or current. Since the change in resistance is non-volatile and reversible, applications containing such devices lay within memory and computing applications [3]– [6]. The circuits that are inspired from firing of neurons and weighted inputs referred to as threshold logic can be imple- mented with memristors due to their varied resistive states that Fig. 1. Resistive memory threshold logic cell circuit consisting of resistance are useful as weights. There are, in general, several challenges switching devices R1, R2 and Rc, and a CMOS inverter to threshold logic implementation in silicon, including a lim- ited number of inputs per gate, limited generalization of the In the proposed logic, we first design a threshold logic cell, and difficulties with integration with conventional logic based cell that will act as a NOR or NAND gate based on V families [7]. Recent developments in memristor technology [1] a preset control voltage C (Fig. 1). This cell forms the unit which, along with the resistive switching property of the have stimulated renewed interest in using switching devices for R R R developing threshold logic gates. However, although these have memristors ( 1, 2, C ) involved, can be used to design smaller chip areas and lower leakage power than conventional an entire logic family of gates. We call it resistive switching threshold logic and use it to design an XOR gate and larger CMOS logic gates, they often have higher power dissipation for threshold logic gates. XOR circuits: a full adder and a 4-bit Carry Look-ahead Adder (LCA). Figure 1 shows the design of the proposed memory The key element of the proposed CMOS inverter/memristor threshold logic cell that utilizes two input memristors R1 and circuits is a memristive [1], [8], [9] device that exhibits R2, connected to the inputs V1 and V2, respectively. In general, resistance-switching [10], [11], [12], [13]. We propose a Vi is the input voltage corresponding to ith input terminal, memristor-based resistive threshold logic gate family that where i can have values 1, 2, 3, . , N . The control voltage progresses from previous work [3] on memristive gates with Vc connected to resistor Rc is used to program the gate to respect to the simplified cell structure with the ability to NAND, NOR or XOR functionality. In case of a 2-terminal control the gate operations through external input control cell in-order to get the NOR functionality the control voltage signals. This strategy is inspired from the cognitive ability Vc should be greater than 0.5 V (logic 1) and for NAND gate of human brain which results from the brain’s ability to it should be below 0.5 V (logic 0), if the input voltage values program and reuse similar neural structures through formation are 0V and 1V for low and high voltage levels. In order to get of appropriate neural networks. In the proposed design, the the XOR functionality, Vc should be the NOR output of inputs resistive switching devices [14], are used as programmable V1 and V2. For NAND and NOR the input resistance is set as R1 = R2 = Rc = R, while for XOR configuration Rc changes according to the control voltage Vc. The CMOS inverter, with an inverter threshold Vth, is used to convert the Vo voltage to the binary state Vout, reflective of the gate operation. All voltages share a common ground. B. Threshold Logic A linear threshold logic gate (LTG) has the following transfer function: . n 1 if Σ wixi >= T f (x1, ..., xn) = i=1 (1) 0 otherwise where xi is a Boolean input variable, wi is an integer weight of the corresponding input i, and the threshold T Fig. 2. Spice simulation result shows the switching of resistance state of the memristor when voltages V1&V2 applied across it is an integer number. In the proposed design we implement the weights wi using the resistive switching property of the TABLE I. TRUTH TABLE FOR NAND AND NOR OPERATION BASED memristor device, xi are the inputs available to the gates and CONTROL VOLTAGE Vc the threshold T is implemented using a CMOS inverter [8]. V1 V2 Vc Rc Vo Vout NAND NOR Vc = Vc = Vc = Vc = NAND NOR C. Memristor 0 1 0 1 0 0 0 1 RH RH 0 < 1 1 On applying an initial threshold voltage memristive devices 0.5 0 1 0 1 RH RH < > 1 0 are brought into ON state upon which they show linear 0.5 0.5 conductance with a configurable slope 1/R [8]. Thus they 1 0 0 1 RH RH < > 1 0 are especially suitable for implementing weights in the pro- 0.5 0.5 1 1 0 1 RH RH > > 0 0 posed threshold logic circuits. The memristor model used for 0.5 0.5 simulation is the spice model that was proposed by [15]. This 6 device has a large ROFF /RON ratio (10 ) while still retaining ns a relatively low switching time (about 10 ). V2 + Vc)/3. While the threshold operation using the inverter From Figure 2 we can see that when voltages 3.5V and can be represented as: . −3.5V are applied across the positive and negative terminals 1 if Vo < V of the memristor, we get a high resistance state (which we Vout = th (3) denote with RH ) and if the reverse voltages (−3.5V and 3.5V ) 0 otherwise are applied across its positive and negative terminals, we get low resistance state (which we denote with R ). This voltage L As shown in Table I NAND logic is achieved when the levels, +/−3.5V , are used to set high and low resistance states control voltage V is logic 0 and NOR logic is obtained when of memristor and are represented as +/ − V , the training c TR the control voltage V is logic 1. voltage [7]. If we use any voltage in between the training c voltages the resistance state of the memristor will not change. Hence we can use these voltage levels for the working of the E. XOR Threshold Logic cell and will refer to them as the testing voltage VTE which can be 1V for logic high and 0V for logic low. Figure 3 shows the XOR configuration of resistive memory threshold logic. In order to get the XOR configuration resistors R R R R D. NAND/NOR Threshold Logic 1 and 2 should be at high resistive state H and c should change its resistance according to the control voltage Vc based From Figure 1, the output voltage of the N input resistive on Eq. 4. divider circuit is given by: . Vc/Rc + Vi/Ri Vo = . (2) 1/Ri + 1/Rc For NAND, NOR and XOR operation we keep the re- sistances of the inputs to a high resistance RH state. For NAND/NOR operation, Rc also remains at high resistance. To configure the circuit as NAND gate the control voltage Vc is logic high, whereas for NOR functionality it is logic low. Since for NAND and NOR configuration all resistors are kept equal, for a 2 input cell Eq. 2 changes to: Vo = (V1 + Fig. 3. XOR configuration of resistive memory threshold logic. TABLE II. TRUTH TABLE FOR XOR OPERATION BASED CONTROL VOLTAGE Vc AND CORRESPONDING CHANGE IN Rc . HERE Vc IS THE NORED OUTPUT OF V1 AND V2 V1 V2 Vc Rc Vo Vout 0 0 1 RL > 0.5 0 0 1 0 RH < 0.5 1 1 0 0 RH < 0.5 1 1 1 0 RH > 0.5 0 Fig. 5. Timing diagram showing the NAND/NOR operation of the proposed memristor threshold logic.
Load more

Recommended publications
  • Episode 5.02 – NAND Logic
    Episode 5.02 – NAND Logic Welcome to the Geek Author series on Computer Organization and Design Fundamentals. I’m David Tarnoff, and in this series, we are working our way through the topics of Computer Organization, Computer Architecture, Digital Design, and Embedded System Design. If you’re interested in the inner workings of a computer, then you’re in the right place. The only background you’ll need for this series is an understanding of integer math, and if possible, a little experience with a programming language such as Java. And one more thing. Our topics involve a bit of figuring, so it might help to keep a pencil and paper handy. In our last episode, we covered three attributes of the sum-of-product expression including its general format and the benefits derived from it, a method to generate a truth table from a given sum-of- products expression, and lastly, a simple procedure we can use to create the proper sum-of-products expression from a given truth table. In this episode, we’re going to look at a fourth attribute. While this last trait may appear to be no more than an interesting exercise in Boolean algebra, it turns out that it offers several benefits when we implement our SOP expressions with digital circuitry. In Episode 4.08 – DeMorgan’s Theorem, we showed how an inverter can be distributed across the inputs of an AND or an OR gate by flipping the operation. In other words, we can distribute an inverter from the output of an AND gate across all the gate’s inputs as long as we change the gate operation to an OR.
    [Show full text]
  • ECSE-4760 Real-Time Applications in Control & Communications
    Rensselaer Polytechnic Institute ECSE-4760 Real-Time Applications in Control & Communications EXPERIMENTS IN DIGITAL LOGIC DESIGN Number of Sessions – 4 INTRODUCTION Over the past few decades the digital world has come into its own. Even though engineering has gone into specialization, it is necessary to understand digital circuits to be able to communicate with others. This experiment attempts to teach a simple method of designing digital circuits. Due to the quick pace of the lab, it is highly recommended that you read one of the references. This will enable you to proceed quickly through the preliminary problems so you will have more time for the design problems. The following is an outline of the experiment. Following each section will be a set of questions that should be answered to show an understanding of the material presented. Any difficulties should be referred to a reference or your instructor. You should use the DesignWorks (LogicWorks or any other you may have) logic circuit simulator on the Macintosh after most sections to cement together all the preceding sections. BACKGROUND THEORY Boolean Algebra Switching Algebra Combinational Logic Minimization Flip-Flops and Registers Counters Synthesis of Synchronous Circuits EXPERIMENTAL PROCEDURE Questions and Problems Simulator Operation & FPGA Implementation REFERENCES It is required that you show all circuits, as built, in your write-up. Please include equations too. The first part of the procedure section contains all the questions and problems to be answered and the second part describes the use of DesignWorks. Note: all references to DesignWorks (on Macintosh computers) throughout this procedure may be replaced with LogicWorks on the lab Windows PCs.
    [Show full text]
  • Digital Logic Design
    Digital Logic Design Chapter 3 Gate-Level Minimization Nasser M. Sabah Outline of Chapter 3 2 Introduction The Map Method Four-Variable Map Five-Variable Map Product of Sums Simplification NAND & NOR Implementation Other Two-Level Implementations Exclusive-OR Function Introduction 3 Gate-level minimization refers to the design task of finding an optimal gate-level implementation of Boolean functions describing a digital circuit. The Map Method 4 The complexity of the digital logic gates The complexity of the algebraic expression Logic minimization Algebraic approaches: lack specific rules The Karnaugh map A simple straight forward procedure A pictorial form of a truth table A diagram made up of squares Each square represents one minterm of the function that is to be minimized. Review of Boolean Function 5 Boolean function Sum of minterms Sum of products (or product of sum) in the simplest form A minimum number of terms A minimum number of literals The simplified expression may not be unique Two-Variable Map 6 A two-variable map Four minterms x' = row 0; x = row 1 y' = column 0; y = column 1 A truth table in square diagram Figure 3.1 Two-variable Map xy m3 xym 1 m 2 m 3 xyxy'' xy Representation of functions in the map Three-Variable Map 7 A three-variable map Eight minterms The Gray code sequence Any two adjacent squares in the map differ by only on variable. Primed in one square and unprimed in the other. e.g., m5 and m7 can be simplified. m57 m xy'(') z xyz xz y y xz Three-variable Map Three-Variable
    [Show full text]
  • Lab 1: Study of Gates & Flip-Flops
    Lab 1: Study of Gates & Flip-flops Aim To familiarize with circuit implementations using ICs and test the behavior of different logic gates and Flip-flops. Hardware Requirement a. Equipments - Digital IC Trainer Kit b. Discrete Components - 74LS00 Quad 2-Input NAND gate 74LS02 Quad 2-Input NOR gate 74LS04 Hex 1-Input NOT gate 74LS08 Quad 2-Input AND gate 74LS10 Triple 3-Input NAND gate 74LS11 Triple 3-Input AND gate 74LS32 Quad 2-Input OR gate 74LS86 Quad 2-Input XOR 74LS73 JK-Flip flop 74LS74 D Flip flop Background Digital logic devices are the circuits that electronically perform logic operations on binary variables. The binary information is represented by high and low voltage levels, which the device processes electronically. The devices that perform the simplest of the logic operations (such as AND, OR, NAND, etc.) are called gates. For example, an AND gate electronically computes the AND of the voltage encoded binary signals appearing at its inputs and presents the voltage encoded result at its output. The digital logic circuits used in this laboratory are contained in integrated circuit (IC) packages, with generally 14 or 16 pins for electrical connections. Each IC is labeled (usually with an 74LSxx number) to identify the logic it performs. The logic diagrams and pin connections for these IC’s are described in the TTL Data Book by Texas Instruments1. The transistor-transistor logic(TTL) IC’s used in this laboratory require a 5.0 volt power supply for operation. TTL inputs require a voltage greater than 2 volts to represent a binary 1 and a voltage less than 0.8 volts to represent a binary 0.
    [Show full text]
  • Realization of Morphing Logic Gates in a Repressilator with Quorum Sensing Feedback
    Realization of Morphing Logic Gates in a Repressilator with Quorum Sensing Feedback Vidit Agarwal, Shivpal Singh Kang and Sudeshna Sinha Indian Institute of Science Education and Research (IISER) Mohali, Knowledge City, SAS Nagar, Sector 81, Manauli PO 140 306, Punjab, India Abstract We demonstrate how a genetic ring oscillator network with quorum sensing feedback can operate as a robust logic gate. Specifically we show how a range of logic functions, namely AND/NAND, OR/NOR and XOR/XNOR, can be realized by the system, thus yielding a versatile unit that can morph between different logic operations. We further demonstrate the capacity of this system to yield complementary logic operations in parallel. Our results then indicate the computing potential of this biological system, and may lead to bio-inspired computing devices. arXiv:1310.8267v1 [physics.bio-ph] 30 Oct 2013 1 I. INTRODUCTION The operation of any computing device is necessarily a physical process, and this funda- mentally determines the possibilities and limitations of the computing machine. A common thread in the history of computers is the exploitation and manipulation of different natural phenomena to obtain newer forms of computing paradigms [1]. For instance, chaos comput- ing [2], neurobiologically inspired computing, quantum computing[3], and DNA computing[4] all aim to utilize, at the basic level, some of the computational capabilities inherent in natural systems. In particular, larger understanding of biological systems has triggered the interest- ing question: what new directions do bio-systems offer for understanding and implementing computations? The broad idea then, is to create machines that benefit from natural phenomena and utilize patterns inherent in systems to encode inputs and subsequently obtain a desired output.
    [Show full text]
  • Universal Gate - NOR Digital Electronics 2.2 Intro to NAND & NOR Logic
    Universal Gate - NOR Digital Electronics 2.2 Intro to NAND & NOR Logic Universal Gate – NOR This presentation will demonstrate… • The basic function of the NOR gate. • How an NOR gate can be using to replace an AND gate, an OR gate or an INVERTER gate. • How a logic circuit implemented with AOI logic gates Universal Gate – NOR could be re-implemented using only NOR gates • That using a single gate type, in this case NOR, will reduce the number of integrated circuits (IC) required to implement a logic circuit. Digital Electronics AOI Logic NOR Logic 2 More ICs = More $$ Less ICs = Less $$ NOR Gate NOR Gate as an Inverter Gate X X X (Before Bubble) X Z X Y X Y X Z X Y X Y Z X Z 0 0 1 0 1 Equivalent to Inverter 0 1 0 1 0 1 0 0 1 1 0 3 4 Project Lead The Way, Inc. Copyright 2009 1 Universal Gate - NOR Digital Electronics 2.2 Intro to NAND & NOR Logic NOR Gate as an OR Gate NOR Gate as an AND Gate X X Y Y X X Z X Y X Y Y Z X Y X Y X Y Y NOR Gate “Inverter” “Inverters” NOR Gate X Y Z X Y Z 0 0 0 0 0 0 0 1 1 0 1 0 Equivalent to OR Gate Equivalent to AND Gate 1 0 1 1 0 0 1 1 1 1 1 1 5 6 NOR Gate Equivalent of AOI Gates Process for NOR Implementation 1.
    [Show full text]
  • Universal Gate - NAND Digital Electronics 2.2 Intro to NAND & NOR Logic
    Universal Gate - NAND Digital Electronics 2.2 Intro to NAND & NOR Logic Universal Gate – NAND This presentation will demonstrate • The basic function of the NAND gate. • How a NAND gate can be used to replace an AND gate, an OR gate, or an INVERTER gate. • How a logic circuit implemented with AOI logic gates can Universal Gate – NAND be re-implemented using only NAND gates. • That using a single gate type, in this case NAND, will reduce the number of integrated circuits (IC) required to implement a logic circuit. Digital Electronics AOI Logic NAND Logic 2 More ICs = More $$ Less ICs = Less $$ NAND Gate NAND Gate as an Inverter Gate X X X (Before Bubble) X Z X Y X Y X Z X Y X Y Z X Z 0 0 1 0 1 Equivalent to Inverter 0 1 1 1 0 1 0 1 1 1 0 3 4 Project Lead The Way, Inc Copyright 2009 1 Universal Gate - NAND Digital Electronics 2.2 Intro to NAND & NOR Logic NAND Gate as an AND Gate NAND Gate as an OR Gate X X Y Y X X Z X Y X Y Y Z X Y X Y X Y Y NAND Gate Inverter Inverters NAND Gate X Y Z X Y Z 0 0 0 0 0 0 0 1 0 0 1 1 Equivalent to AND Gate Equivalent to OR Gate 1 0 0 1 0 1 1 1 1 1 1 1 5 6 NAND Gate Equivalent to AOI Gates Process for NAND Implementation 1.
    [Show full text]
  • New Approaches for Memristive Logic Computations
    Portland State University PDXScholar Dissertations and Theses Dissertations and Theses 6-6-2018 New Approaches for Memristive Logic Computations Muayad Jaafar Aljafar Portland State University Let us know how access to this document benefits ouy . Follow this and additional works at: https://pdxscholar.library.pdx.edu/open_access_etds Part of the Electrical and Computer Engineering Commons Recommended Citation Aljafar, Muayad Jaafar, "New Approaches for Memristive Logic Computations" (2018). Dissertations and Theses. Paper 4372. 10.15760/etd.6256 This Dissertation is brought to you for free and open access. It has been accepted for inclusion in Dissertations and Theses by an authorized administrator of PDXScholar. For more information, please contact [email protected]. New Approaches for Memristive Logic Computations by Muayad Jaafar Aljafar A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical and Computer Engineering Dissertation Committee: Marek A. Perkowski, Chair John M. Acken Xiaoyu Song Steven Bleiler Portland State University 2018 © 2018 Muayad Jaafar Aljafar Abstract Over the past five decades, exponential advances in device integration in microelectronics for memory and computation applications have been observed. These advances are closely related to miniaturization in integrated circuit technologies. However, this miniaturization is reaching the physical limit (i.e., the end of Moore’s Law). This miniaturization is also causing a dramatic problem of heat dissipation in integrated circuits. Additionally, approaching the physical limit of semiconductor devices in fabrication process increases the delay of moving data between computing and memory units hence decreasing the performance. The market requirements for faster computers with lower power consumption can be addressed by new emerging technologies such as memristors.
    [Show full text]
  • A Noise-Assisted Reprogrammable Nanomechanical Logic Gate
    pubs.acs.org/NanoLett A Noise-Assisted Reprogrammable Nanomechanical Logic Gate Diego N. Guerra,† Adi R. Bulsara,‡ William L. Ditto,§ Sudeshna Sinha,| K. Murali,⊥ and P. Mohanty*,† † Department of Physics, Boston University, 590 Commonwealth Avenue, Boston, Massachusetts 02215, ‡ SPAWAR Systems Center Pacific, Code 71, 53560 Hull Street, San Diego, California 92152, § School of Biological and Health Systems Engineering, Arizona State University, Tempe, Arizona 85287, | Institute of Mathematical Sciences, Taramani, Chennai 600 113, India, and ⊥ Physics Department, Anna University, Chennai 600 025, India ABSTRACT We present a nanomechanical device, operating as a reprogrammable logic gate, and performing fundamental logic functions such as AND/OR and NAND/NOR. The logic function can be programmed (e.g., from AND to OR) dynamically, by adjusting the resonator’s operating parameters. The device can access one of two stable steady states, according to a specific logic function; this operation is mediated by the noise floor which can be directly adjusted, or dynamically “tuned” via an adjustment of the underlying nonlinearity of the resonator, i.e., it is not necessary to have direct control over the noise floor. The demonstration of this reprogrammable nanomechanical logic gate affords a path to the practical realization of a new generation of mechanical computers. KEYWORDS Nanomechanical logic, nanomechanical computing, logical stochastic resonance, stochastic resonance, nanomechanical resonator practical realization of a nanomechanical logic applied as input stimuli to a two-state system, the response device, capable of performing fundamental logic can result in a specific logical output with a probability (for operations, is yet to be demonstrated despite a long- obtaining this output) controlled by the noise intensity.
    [Show full text]
  • 1 Novel Reconfigurable Logic Gates Using Spin Metal-Oxide
    Novel Reconfigurable Logic Gates Using Spin Metal-Oxide-Semiconductor Field-Effect Transistors Satoshi Sugahara1, 2*, Tomohiro Matsuno1, and Masaaki Tanaka1,2** 1 Department of Electronic Engineering, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo, 113-8656, Japan 2 PRESTO, Japan Science and Technology Agency, 4-1-8 Honcho, Kawaguchi 332-0012, Japan We propose and numerically simulate novel reconfigurable logic gates employing spin metal-oxide-semiconductor field-effect transistors (spin MOSFETs). The output characteristics of the spin MOSFETs depend on the relative magnetization configuration of the ferromagnetic contacts for the source and drain, that is, high current-drive capability in the parallel magnetization and low current-drive capability in the antiparallel magnetization [S. Sugahara and M. Tanaka: Appl. Phys. Lett. 84 (2004) 2307]. A reconfigurable NAND/NOR logic gate can be realized by using a spin MOSFET as a driver or an active load of a complimentary MOS (CMOS) inverter with a neuron MOS input stage. Its logic function can be switched by changing the relative magnetization configuration of the ferromagnetic source and drain of the spin MOSFET. A reconfigurable logic gate for all symmetric Boolean functions can be configured using only five CMOS inverters including four spin MOSFETs. The operation of these reconfigurable logic gates was confirmed by numerical simulations using a simple device model for the spin MOSFETs. KEYWORDS: spintronics, spin transistor, spin MOSFET, reconfigurable logic, FPGA *E-mail address: [email protected] **E-mail address: [email protected] 1 1 Introduction The area of spintronics (or spin electronics) in which uses not only charge transport of electrons but also the spin degree of freedom of electrons is used has generated much interest in recent years.
    [Show full text]
  • Designing Combinational Logic Gates in Cmos
    CHAPTER 6 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS In-depth discussion of logic families in CMOS—static and dynamic, pass-transistor, nonra- tioed and ratioed logic n Optimizing a logic gate for area, speed, energy, or robustness n Low-power and high-performance circuit-design techniques 6.1 Introduction 6.3.2 Speed and Power Dissipation of Dynamic Logic 6.2 Static CMOS Design 6.3.3 Issues in Dynamic Design 6.2.1 Complementary CMOS 6.3.4 Cascading Dynamic Gates 6.5 Leakage in Low Voltage Systems 6.2.2 Ratioed Logic 6.4 Perspective: How to Choose a Logic Style 6.2.3 Pass-Transistor Logic 6.6 Summary 6.3 Dynamic CMOS Design 6.7 To Probe Further 6.3.1 Dynamic Logic: Basic Principles 6.8 Exercises and Design Problems 197 198 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS Chapter 6 6.1Introduction The design considerations for a simple inverter circuit were presented in the previous chapter. In this chapter, the design of the inverter will be extended to address the synthesis of arbitrary digital gates such as NOR, NAND and XOR. The focus will be on combina- tional logic (or non-regenerative) circuits that have the property that at any point in time, the output of the circuit is related to its current input signals by some Boolean expression (assuming that the transients through the logic gates have settled). No intentional connec- tion between outputs and inputs is present. In another class of circuits, known as sequential or regenerative circuits —to be dis- cussed in a later chapter—, the output is not only a function of the current input data, but also of previous values of the input signals (Figure 6.1).
    [Show full text]
  • Switching Theory and Logic Design
    SWITCHING THEORY AND LOGIC DESIGN LECTURE NOTES B.TECH (II YEAR – II SEM) (2018-19) Prepared by: Ms M H Bindu Reddy, Assistant Professor Department of Electrical & Electronics Engineering MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY (Autonomous Institution – UGC, Govt. of India) Recognized under 2(f) and 12 (B) of UGC ACT 1956 (Affiliated to JNTUH, Hyderabad, Approved by AICTE - Accredited by NBA & NAAC – ‘A’ Grade - ISO 9001:2015 Certified) Maisammaguda, Dhulapally (Post Via. Kompally), Secunderabad – 500100, Telangana State, India SYLLABUS UNIT -I: Number System and Gates: Number Systems, Base Conversion Methods, Complements of Numbers, Codes- Binary Codes, Binary Coded Decimal Code and its Properties, Excess-3 code, Unit Distance Code, Error Detecting and Correcting Codes, Hamming Code.Digital Logic Gates, Properties of XOR Gates, Universal Logic Gates. UNIT -II: Boolean Algebra and Minimization: Basic Theorems and Properties, Switching Functions, Canonical and Standard Forms,Multilevel NAND/NOR realizations. K- Map Method, up to Five variable K- Maps, Don’t Care Map Entries, Prime and Essential prime Implications, Quine Mc Cluskey Tabular Method UNIT -III: Combinational Circuits Design: Combinational Design, Half adder,Fulladder,Halfsubtractor,Full subtractor,Parallel binary adder/subtracor,BCD adder, Comparator, decoder, Encoder, Multiplexers, DeMultiplexers, Code Converters. UNIT -IV: Sequential Machines Fundamentals: Introduction, Basic Architectural Distinctions between Combinational and Sequential circuits, classification of sequential circuits, The binary cell, The S-R- Latch Flip-Flop The D-Latch Flip-Flop, The “Clocked T” Flip-Flop, The “ Clocked J-K” Flip-Flop, Design of a Clocked Flip-Flop, Conversion from one type of Flip-Flop to another, Timing and Triggering Consideration. UNIT -V: Sequential Circuit Design and Analysis: Introduction, State Diagram, Analysis of Synchronous Sequential Circuits, Approaches to the Design of Synchronous Sequential Finite State Machines, Design Aspects, State Reduction, Design Steps, Realization using Flip-Flops.
    [Show full text]