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An Algorithm for the Synthesis of NAND Logic Networks Using a Diagrammatic Approach

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Scholars' Mine Masters Theses Student Theses and Dissertations 1966 An algorithm for the synthesis of NAND logic networks using a diagrammatic approach Donald Robert Nelson Follow this and additional works at: https://scholarsmine.mst.edu/masters_theses Part of the Electrical and Computer Engineering Commons Department: Recommended Citation Nelson, Donald Robert, "An algorithm for the synthesis of NAND logic networks using a diagrammatic approach" (1966). Masters Theses. 5761. https://scholarsmine.mst.edu/masters_theses/5761 This thesis is brought to you by Scholars' Mine, a service of the Missouri S&T Library and Learning Resources. This work is protected by U. S. Copyright Law. Unauthorized use including reproduction for redistribution requires the permission of the copyright holder. For more information, please contact [email protected]. 2 ABSTRACT A diagrammatic approach is presented for the synthesis of multilevel NAND networks realizing combinational logic expressions. The network synthesized is restricted to only uncomplemented inputs. The synthesis algorithm involves the determination of minimum sum of products and product of sums expressions for a Boolean function, construction of an a-~ diagram from these expressions followed by implementation with NAND gates directly from the diagram. The resulting network is a minimal or near minimal NAND gate realization of the given function. The algorithm is applicable to com­ pletely or incompletely specified Boolean functions and is extended to include NOR synthesis. 3 ACKNOWLEDGEMENT The author would like to express his appreciation for the encouragement and guidance he received from his advisor, Dr. James H. Tracey. 4 TABLE OF CONTENTS ABSTRACT 2 ACKNOWLEDGEMENT 3 LIST OF FIGURES 5 CHAPTER I. INTRODUCTION 6 CHAPTER II. THE SYNTHESIS OF NAND NETWORKS USING a-~ DIAGRAMS 12 A. Construction of the a-~ diagram 13 1. The a-set 14 2. The ~-set 17 3. The a-~ Diagram 19 4. Simplification of the a-~ Diagram 22 B. The Network Synthesis 23 1. The Synthesis 24 2. Extension to NOR Synthesis 44 3. Worked Examples 44 CHAPTER III. SUMMARY 52 BIBLIOGRAPHY 53 VITA 54 5 LIST OF FIGURES Figure page 1 An a-~ diagram illustration 12 2 Example function for the a-set 14 determination 3 Example function for the ~-set 18 determination 4 An a-~ diagram 20 5 Dual and complement a-~ diagrams 21 6 Illustration of algorithm step 2 25 7 Illustration of algorithm step 4 26 8 Illustration of algorithm step 6 27 9 Illustration of algorithm step 8 28 10 Illustration of algorithm step 10 29 11 Illustration of algorithm step 12 30 12 Redundant gate removal 31 13 Illustration of rule 1 32 14 Illustration of rule 2 33 15 Two-level equivalents 34 16 Illustration of reading the a-~ diagram 37 17 Modification of Figure 16 37 18 Decomposition of a diagram 43 6 CHAPTER I INTRODUCTION The problem in logical design of synthesizing NAND networks with only uncomplemented inputs available has been and still is of great importance. The NAND element is chosen because of its inherent amplification and drive capability and because it is a universal logic element. That is to say, any Boolean function may be realized using combinations of only these gates. Another reason for choos­ ing the NAND element is the growing importance of integrated circuits in the digital field and the relative ease of fab­ ricating these elements using integrated circuit techniques. The networks synthesized by the method described in this paper will be restricted to only uncomplemented inputs. Frequently the inputs to the networks to be synthesized will be the outputs from other NAND networks. The complemented outputs of these gates are generally not available. It is well known that if the theory of two-stage networks using AND and OR gatesis extended to this problem, the resulting networks will not necessarily be minimal or least-cost net­ works. In this paper, a network will be said to be minimal if it realizes the desired Boolean expression with a min­ imum number of inputs to a minimum number of gates. Smith (lf assumed the availability of both complemented and uncomplemented inputs in his synthesis procedure. A com- *Numbers in parentheses are references to the Bibliography. 7 puter was utilized to investigate all of the possible ways of interconnecting a given number of NAND elements and all of the functionsof three variables that each connection could generate. The minimum network was then selected. This procedure could become overwhelming for a greater num- ber of variables. The recent work by Dietmeyer and Schneider (2) was to develop a programmable algorithm for the synthesis of NAND and NOR networks. Again, both complemented and uncomple- mented inputs were assumed available. The algorithm was developed so as to satisfy fan-in requirements of the gating used,by factoring in a prescribed manner. The object of this work is not to guarantee minimal networks but to pro- vide speed and accuracy of design satisfying fan-in restric- tion. The two papers already cited considered problems where both complemented and uncomplemented inputs were assumed. In this paper, the inputs are restricted to only uncomple- mented variables. The papers reviewed below consider this latter class of problems. For functions of three variables the work done by Hellerman (3) is significant. An exhaustive method was employed to select the minimum NAND and NOR network for gen­ erating functions of three variables with uncomplernented inputs available. All possible combinational networks with seven and fewer blocks (242 ) were examined (fan-in was lim­ ited to three variables). The networks were examined in 8 ascending order of number of blocks with all combinations of inputs. The first network found to generate one of the 256 Boolean functions of three variables was selected as were all others using the same number of gates. The one with the fewest inputs was then selected as the minimal network real- izing that function. This was possible as all others to be obtained would contain a larger number of gates. When it is desired to synthesize functions of more than three variables~ a complete enumeration and selection techniques become un- wieldy and impractical if not impossible byknown techniques and computing capability. This is easily seen by noting that 4 there are 22 = 65~536 functions of four variables not to mention the number of possible NAND implementations for each one. Maley and Earle (4) present an algebraic approach to the synthesis of functions of several variables using NAND gates. This approach is to factor a sum of products expres- sion of the given switching function in a prescribed manner. With the judicious use of added redundanc~ a logically equiv­ alent expression is obtained which is suitable for synthesis with NANDs. The complexity of the network realized using this approach depends on the facility of the user in manip­ ulating the Boolean expression. For a large number of vari­ ables, this algebraic approach can become quite inefficient with the possibility that the resulting network has more gates and inputs than the two-level network for the minimum sum of products expression with single-input gates used as 9 inverters. In the previously cited work by Maley and Earle. a method of factoring on a Karnaugh map is presented for the synthesis of multi-level NAND networks. This method is eas­ ily applicable to functions of only a few variables. However, it has been this author's experience that networks synthesized by this map factoring approach tend to have excessive levels of logic. As with the previously mentioned algebraic method, the complexity of the network realized depends to a large extent on the skill of the user. NAND networks limited to three levels with only uncom­ plemented inputs available have been called TANT (Three­ level AND - NOT network with True inputs) networks by McCluskey (5) and Gimpel (6). Gimpel and McCluskey consider the same class of functions to be considered in this paper. However~ their solutions are limited to TANT networks. Gimpel describes an approach using prime implicants of the TANT expression which are analogous but not equivalent to the prime implicants in AND -OR synthesis. The approach is similar to the Quine-McCluskey algorithm for two-level AND -OR synthesis. The resulting network is a minimum gate count TANT network. The algorithm of this paper does not restrict the solution to a TANT network. Ellis (7) has developed a systematic procedure for synthesizing NOR and NAND networks limited to three levels. The procedure is essentially an extension of the algebraic approach of Maley and Earle utilizing redundancy and factor- 10 ing so that the outputs of third-level gates may be shared by second-level gates. In this method, the prime implicants are listed and then grouped into one of three basic patterns. This grouping leads to possible reduction in the final NAND network by the sharing of gates on the input level of logic. These gates generate the negated variables in the prime implicants. This paper presents an approach to the synthesis of multi-level NAND networks which is a modification of the work done by Akers (8). In his paper, Akers utilizes the concept of an a-p diagram to develop a method for multi­ level AND -OR synthesis. The approach is diagrammatic, i. e., the network is synthesized directly from a diagram which represents the switching function. This paper is concerned with the construction of a modified a-p diagram suitable for NAND networks, diagram simplification, and diagram transformation into minimal or near-minimal NAND networks. The techniques developed by Akers for the manip­ ulation of the diagram applicable to the problem being con­ sidered in this paper will be summarized when needed. It is the author 1 s feeling that the method herein described is easier to apply than those in the previously cited literature.
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