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Masters Theses Student Theses and Dissertations
1966
An algorithm for the synthesis of NAND logic networks using a diagrammatic approach
Donald Robert Nelson
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Recommended Citation Nelson, Donald Robert, "An algorithm for the synthesis of NAND logic networks using a diagrammatic approach" (1966). Masters Theses. 5761. https://scholarsmine.mst.edu/masters_theses/5761
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2
ABSTRACT
A diagrammatic approach is presented for the synthesis of multilevel NAND networks realizing combinational logic expressions. The network synthesized is restricted to only uncomplemented inputs. The synthesis algorithm involves the determination of minimum sum of products and product of sums expressions for a Boolean function, construction of an a-~ diagram from these expressions followed by implementation with NAND gates directly from the diagram. The resulting network is a minimal or near minimal NAND gate realization of the given function. The algorithm is applicable to com pletely or incompletely specified Boolean functions and is extended to include NOR synthesis. 3
ACKNOWLEDGEMENT
The author would like to express his appreciation for the encouragement and guidance he received from his advisor, Dr. James H. Tracey. 4
TABLE OF CONTENTS ABSTRACT 2 ACKNOWLEDGEMENT 3 LIST OF FIGURES 5 CHAPTER I. INTRODUCTION 6 CHAPTER II. THE SYNTHESIS OF NAND NETWORKS
USING a-~ DIAGRAMS 12
A. Construction of the a-~ diagram 13 1. The a-set 14
2. The ~-set 17
3. The a-~ Diagram 19 4. Simplification of the
a-~ Diagram 22 B. The Network Synthesis 23 1. The Synthesis 24 2. Extension to NOR Synthesis 44
3. Worked Examples 44
CHAPTER III. SUMMARY 52
BIBLIOGRAPHY 53
VITA 54 5
LIST OF FIGURES
Figure page
1 An a-~ diagram illustration 12 2 Example function for the a-set 14 determination
3 Example function for the ~-set 18 determination
4 An a-~ diagram 20
5 Dual and complement a-~ diagrams 21 6 Illustration of algorithm step 2 25 7 Illustration of algorithm step 4 26 8 Illustration of algorithm step 6 27 9 Illustration of algorithm step 8 28
10 Illustration of algorithm step 10 29
11 Illustration of algorithm step 12 30
12 Redundant gate removal 31
13 Illustration of rule 1 32
14 Illustration of rule 2 33 15 Two-level equivalents 34
16 Illustration of reading the a-~ diagram 37
17 Modification of Figure 16 37
18 Decomposition of a diagram 43 6
CHAPTER I
INTRODUCTION
The problem in logical design of synthesizing NAND
networks with only uncomplemented inputs available has
been and still is of great importance. The NAND element
is chosen because of its inherent amplification and drive
capability and because it is a universal logic element.
That is to say, any Boolean function may be realized using
combinations of only these gates. Another reason for choos
ing the NAND element is the growing importance of integrated
circuits in the digital field and the relative ease of fab
ricating these elements using integrated circuit techniques.
The networks synthesized by the method described in
this paper will be restricted to only uncomplemented inputs.
Frequently the inputs to the networks to be synthesized will
be the outputs from other NAND networks. The complemented
outputs of these gates are generally not available. It is
well known that if the theory of two-stage networks using
AND and OR gatesis extended to this problem, the resulting
networks will not necessarily be minimal or least-cost net works. In this paper, a network will be said to be minimal
if it realizes the desired Boolean expression with a min
imum number of inputs to a minimum number of gates.
Smith (lf assumed the availability of both complemented
and uncomplemented inputs in his synthesis procedure. A com-
*Numbers in parentheses are references to the Bibliography. 7 puter was utilized to investigate all of the possible ways of interconnecting a given number of NAND elements and all of the functionsof three variables that each connection could generate. The minimum network was then selected.
This procedure could become overwhelming for a greater num- ber of variables.
The recent work by Dietmeyer and Schneider (2) was to develop a programmable algorithm for the synthesis of NAND and NOR networks. Again, both complemented and uncomple- mented inputs were assumed available. The algorithm was developed so as to satisfy fan-in requirements of the gating used,by factoring in a prescribed manner. The object of this work is not to guarantee minimal networks but to pro- vide speed and accuracy of design satisfying fan-in restric- tion.
The two papers already cited considered problems where both complemented and uncomplemented inputs were assumed.
In this paper, the inputs are restricted to only uncomple- mented variables. The papers reviewed below consider this latter class of problems.
For functions of three variables the work done by
Hellerman (3) is significant. An exhaustive method was employed to select the minimum NAND and NOR network for gen erating functions of three variables with uncomplernented inputs available. All possible combinational networks with seven and fewer blocks (242 ) were examined (fan-in was lim ited to three variables). The networks were examined in 8 ascending order of number of blocks with all combinations of inputs. The first network found to generate one of the 256 Boolean functions of three variables was selected as were all others using the same number of gates. The one with the fewest inputs was then selected as the minimal network real- izing that function. This was possible as all others to be obtained would contain a larger number of gates. When it is desired to synthesize functions of more than three variables~ a complete enumeration and selection techniques become un- wieldy and impractical if not impossible byknown techniques and computing capability. This is easily seen by noting that 4 there are 22 = 65~536 functions of four variables not to mention the number of possible NAND implementations for each one. Maley and Earle (4) present an algebraic approach to the synthesis of functions of several variables using NAND gates. This approach is to factor a sum of products expres- sion of the given switching function in a prescribed manner.
With the judicious use of added redundanc~ a logically equiv alent expression is obtained which is suitable for synthesis with NANDs. The complexity of the network realized using this approach depends on the facility of the user in manip ulating the Boolean expression. For a large number of vari ables, this algebraic approach can become quite inefficient with the possibility that the resulting network has more gates and inputs than the two-level network for the minimum sum of products expression with single-input gates used as 9 inverters.
In the previously cited work by Maley and Earle. a method of factoring on a Karnaugh map is presented for the synthesis of multi-level NAND networks. This method is eas
ily applicable to functions of only a few variables. However, it has been this author's experience that networks synthesized by this map factoring approach tend to have excessive levels of logic. As with the previously mentioned algebraic method, the complexity of the network realized depends to a large extent on the skill of the user.
NAND networks limited to three levels with only uncom plemented inputs available have been called TANT (Three level AND - NOT network with True inputs) networks by McCluskey (5) and Gimpel (6). Gimpel and McCluskey consider the same class of functions to be considered in this paper.
However~ their solutions are limited to TANT networks.
Gimpel describes an approach using prime implicants of the
TANT expression which are analogous but not equivalent to the prime implicants in AND -OR synthesis. The approach is similar to the Quine-McCluskey algorithm for two-level
AND -OR synthesis. The resulting network is a minimum gate count TANT network. The algorithm of this paper does not restrict the solution to a TANT network. Ellis (7) has developed a systematic procedure for synthesizing NOR and NAND networks limited to three levels.
The procedure is essentially an extension of the algebraic approach of Maley and Earle utilizing redundancy and factor- 10
ing so that the outputs of third-level gates may be shared
by second-level gates. In this method, the prime implicants
are listed and then grouped into one of three basic patterns.
This grouping leads to possible reduction in the final NAND
network by the sharing of gates on the input level of logic.
These gates generate the negated variables in the prime implicants.
This paper presents an approach to the synthesis of
multi-level NAND networks which is a modification of the work done by Akers (8). In his paper, Akers utilizes the concept of an a-p diagram to develop a method for multi level AND -OR synthesis. The approach is diagrammatic,
i. e., the network is synthesized directly from a diagram which represents the switching function. This paper is concerned with the construction of a modified a-p diagram suitable for NAND networks, diagram simplification, and diagram transformation into minimal or near-minimal NAND networks. The techniques developed by Akers for the manip ulation of the diagram applicable to the problem being con sidered in this paper will be summarized when needed. It is the author 1 s feeling that the method herein described is easier to apply than those in the previously cited literature.
This diagrammatic approach has the advantage of giving a visual interpretation to the concepts of fan-in, fan-out and levels of logic. In most instances, the network synthe sized by this method will be minimal. Finally~ the procedure will be extended to include synthesis with NOR gates through ll
the use of the duality property of the NAND and NOR. 12
CHAPTER II
THE SYNTHESIS OF NAND NETWORKS USING a-~ DIAGRAMS
As in Akers' method, the synthesis procedure to be presented in this chapter involves the construction and use of a diagram derived from the specifications of a switching function. A switching function F(x1 , x 2 , ... , xn) is described by Akers (9) as an ~ + !(column truth table defin- ing for each n-bit binary input combination the correspond ing value ofF (either 0 or 1). The table must be consist ent which means that F cannot be both 0 and 1 for the same input combination. In his paper, Akers utilizes the concept of a logically passive function described in a previous paper (9) to obtain what he calls a and ~ sets. Stated simply, any switching function realizable with only AND and
OR gates is logically passive. A diagram is constructed from these a and~ sets. This diagram is called the a- ~ diagram. The diagram has the property that reading horizon tally corresponds to logical multiplication and reading ver tically to logical addition. This is illustrated in Figure
1.
A B A B
c c D D f = ABAB + CCDD = AB + CD = ( A+C ) ( B+C ) (A+ D) ( B+ D)
Figure 1. An a-~ diagram illustration 13
The method described by Akers for the construction of
this diagram may be quite lengthy and is not particularly
suited for our problem. For this reason, a different method
of obtaining the diagram will be presented. This method has
the advantage that it involves the familiar procedure of
selecting minimal sets of prime implicants and implicates
from a Karnaugh map.
A. Construction of the a-{3 Diagram
The usefulness of the synthesis method presented in this paper is based on the relative ease with which it may be applied. The construction of the a-{3 diagram is an inte gral part of this procedure. It has been the author's ex perience that the method presented by Akers for this con struction is somewhat tedious and lengthy. Therefore, a new and simpler method will be developed in this paper.
The a-{3 diagram is formed as a rectangular array having one row for each term in a sum of products representation of the switching function to be synthesized and one column for each factor in a product of sums representation for the same function. Since there may be more than one sum of products and product of sums representation of a given function, the possibility of more than one different a-{3 diagram repre senting the same function is not obviated. Because of this, the question is raised as to whether or not one diagram may be better than another in so far as synthesis is concerned.
This is indeed the case. It is necessary then to select the
11 best 11 a-{3 diagram which will in turn yield a minimum or near 14
minimum network. The next two sections describe how to develop this "best" a-(3 diagram.
1. The a-set
The terms that comprise a sum of products expression for a functio~ f, will be called the a-set for that function.
Clearly, there may be more than one a-set for any given func- tion. The problem is to obtain an a-set that will include all of the minimal sum of products expressions for f. The selection of such an a-set is best illustrated by an example.
Consider the switching function, f, in Figure 2 (a) .
(f = ~ 2' 4, 5, 6, 8, 10, 11, 13, 15)
A B c D :tf 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 1
0 1 0 0 1 CD 0 1 0 1 1 AB 00 01 11 10 0 1 1 1 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 0 1 1 1 0 0 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 1 1 1 1 (b) 1 1 1 0 0 1 0 0 0 1 1 0 0 1 0 1 1 1 1 1 1 0 1 0 1 (a)
F ~gure. 2 . Example function for the a-set determination 15
The function is first mapped on a Karnaugh map as shown
in Figure 2(b). Then all minimum sum of products expressions
are formed. Minimal expressions are of interest because they
yield minimum row a-~ diagrams. It will be shown that simpli
fication of the a-~ diagram in terms of row and column elim
ination corresponds to simplification of the resulting NAND network.
For the example function there are three minimum sum of products expressions.
fl = ABD + ACD + ABC + ACD + ABD
f2 = ABD + ACD + ABC+ ACD + BCD
f3 = ABD+ ACD + ABC+ ABC + ABD
It appears that a decision must be mace as to which min- imal expression to use. This decision will be postponed by constructing a sum of products expression for the function , and corresponding a-set which includes all minimal forms.
The a-~ diagram will then contain a collection of all minimal sum of products of the function. Simplification of the a-~ diagram to be described later corresponds to selection of the best minimal form for NAND implementation. It is a relative ly easy matter to perform this selection on the a-~ diagram as opposed to selection before diagramming. This points out an important advantage of the diagrammatic approach over the previously cited algebraic approaches. The minimum expres sion which has this property can be obtained by first logic ally multiplying together all minimal sum of products expres sions. Thensimplify with only the following three theorems: 16
1. a·a = 0 2. a·a =a
3. a + ab = a
An equivalent procedure, and one that will save time and effort in most cases is to first select the terms that appear in all minimum sum of products expressions for f.
Designate the logical sum of these terms by r. The sums of
in . f are designated by the remaining terms fl' f2' f3 .. n s That is to say sl' s2, s3 . . . n .
fl = r + sl
f2 = r + s2
f3 = r + 53
r s + n where f 1 , f 2 , f 3 ... fn are the minimal sum of products expressions for f and therefore are all logically equivalent
to f.
It then follows that
s n
where f is the desired sum of products expression. It is a obvious that f is logically equivalent to f. a For the example function 17
r ABD ACD ABC = + + s 1 = ACD + ABD
s2 = ACD + BCD
s 3 = ABC + ABD Therefore
fa = ABD + ACD + ABC + ABCD + ABCD + ABCD and the a-set is
{ABD, ACD, ABC, ABCD, ABCD, ABCD}
A summary of the steps involved in obtaining the a-set is as
follows:
1. Map the function.
2. Read all minimal sum of products expressions. 3. Logically multiply together all minimal sum of
products expressions.
4. Simplify the resulting sum of products expression
by using only selected theorems.
5· Select all resulting terms as elements of the
a-set.
2. The {3-set
The set of terms from the dual of a product of sums expression for a function will be called the {3-set of that function. Again,there may be more than one {3-set for any given function. The {3-set will be obtained in a manner similar to that used for obtaining the a-set and will utilize the same Karnaugh map. The determination of the
{3-set for the first example is trivial. Therefore, tc better illustrate the.: selection of the · ~-set con-sider the 18 new function that is shown mapped in Figure 3. CD AB 00 01 11 10
0 0 1 1 0 1
0 1 1 1 1 1
1 1 0 1 0 1
1 0 0 1 0 0
Figure 3. Example function for the ~-set determination
All minimum product of sums expressions are formed.
Minimal expressions are of interest because they yield mini mum column a-~ diagrams. As stated in connection with the a-set determination, simplification of the a-~ diagram in terms of column elimination corresponds to simplification of the resulting NAND network. For this example there are two minimal product of sums:
fl = (A+ c + D)(B + c + D) (A + c + D)(A + B + D)
f2 = (A + c + D)(B + c + D) (A + c + D) (A + B + c)
The ~-set is determined from the dual expressions which are as follows, ACD + BCD + ACD + ABD fl dual =
= ACD + BCD + ACD + ABC f2 dual
The same procedure as was used in the determination of the a-set is now followed. All of these dual expressions are logically multiplied together. Simplification of the resulting expression is accomplished by the application of only the three Boolean theorems used in a-set simplification. 19
The terms of the resulting expression, f co t't t ~ dual' ns 1 u e
the ~-set. In the present example,
f ~ dual = ACD + BCD + ACD + ABCD
Note that by taking the dual of f~ dual ' a product of sums
expression is obtained, f~, which is equivalent to f.
f~ = (A+ C + D)(B + C + D)(A + C + D)(A + B + C + D)
The terms of f~ dual form the elements of the ~-set. The
~-set for the example is
{ ACD ~ BCD' ACD' ABCD}. Therefore, the selection of which minimal product of sums
expression to use is postponed to the a-~ diagram simpli
fication where it can be done with greater facility.
3. The a-~ Diagram
After the a and ~ sets have been determined, the a- ~ diagram can be constructed. This diagram is formed as a
rectangular array having one row for each term of the a-set
and one column for each term of the ~-set. The literals in
each term of the a-set are the labels for the rows. The
literals of each term of the ~-set are the labels for the
columns. In square i,j are entered the literals that appear
as labels for both row i and column j. Once the literals
have been entered in the squares , the labels on the rows and columns may be omitted. The diagram constructed in this manner will be called the a-~ diagram.
The a-set for the function of Figure 2(a) was determined as 20
{lilln~ ACD~ ABC~ ABCD~ ABCD ~ ABeD} The {3-set is easily determined as -- { ABD~ BCD~ ACD~ ABc}.
The a-{3 diagram for this function is shown with the row and column labels retained for clarity in Figure 4.
ABD BCD ACD ABC - ABD B - D AD A
ACD --A CD -D c
ABC -A B -c B
ABCD -BD c A AC
ABCD D BC A ABC - ABCD D B AC AB
Figure 4. An a-{3 diagram From the preceeding example it is seen that the result-
ing a-{3 diagram may contain squares with more than one entry. The a-{3 diagram to be used in the synthesis algorithm must consist of squares with single entries. Before this problem is discussed~ it will be advantageous to make the following definitions.
Definition 1. A column (row) of an a-{3 diagram that has as entries only complemented variables will be referred to as a comple- mented column (row).
Definition 2. A column (row) of an a-{3 diagram that has as entries only uncomplemented variables will be referred to as an 21 uncomplemented column (row).
In the synthesis procedure it will be necessary to be able to form the a-{3 diagram of the dual and of the comple- ment of a function if the a-{3 diagram of the function itself has already been determined. Since the dual of an expression is obtained by interchanging all occurrences of+ and ·~ and of 1 and o~ the a-{3 diagram of the dual of a function is obtained by simply interchanging the elements of the a and {3 sets. This procedure is illustrated in Figure 5(a). By
DeMorgan's Law~ the a-{3 diagram of the complemented function is obtained by interchanging the a and {3 sets and complement ing all literals. This is shown in Figure 5(b).
- - A B D D A B D - - B c A B B c A - - - - D A B c D A B
a-{3 diagram of f D B c a-{3 diagram of the
dual of f (a)
- A B D - - B c A
D A B
--D B -c
(b) a-{3 diagram of f
Figure 5· Dual and complement a-{3 diagram 22
In this paper the different letters in a Boolean expres sion used to denote statements concerning bivalued situations will be called variables. For example _, in the expression
AB + AC + A ( D + E ) there are five variables A, B, C, D, and E. Each occurance of a variable or its complement is called a literal. There are seven literals in the example expression. In light of this definition, the literal B is not a variable but is the complement of a variable, namely B. Unless otherwise spec ified, the terms variable and uncomplemented variable will be used interchangeably.
4. Simplification of the a-~ Diagram
The a-~ diagram to be used in the algorithm must consist of squares with a single entry. Akers (8) lists the follow ing four rules which may be applied in simplifying the a-~ diagram: 1. Rows and columns may be rearranged in any order.
This is possible because no particular order is
required in labeling the rows and columns with
elements of the a-~ sets. 2. If one row (column) has the same literals (and
perhaps others) in the same squares as a second,
it may be removed. 3. A literal may be removed from any row (column)
in which it does not appear alone. This must
be done one at a time. 4. All but one literal may be removed from any square. 23
When the a-~ diagram is being simplified, i.e.,reduced to a diagram consisting of squares with single entries, the lit erals that are retained in given squares will be selected so as to yield a-~ diagrams with the following desired proper ties. The list is in descending order of priority.
1. Remove redundant literals so as to yield a
diagram that contains only uncomplemented
variables.
2. Remove redundant literals so as to yield a
row whose entries are a single complemented
variable. 3. Remove redundant literals so as to yield a
diagram that contains only complemented
variables. 4. Remove redundant literals so as to yield a
diagram with all columns complemented or
uncomplemented. 5. Remove redundant literals so as to form an
uncomplemented row. 6. Remove redundant literals so as to form a
maximum number of complemented columns.
Remaining columns should show a minimum
number of complemented variables.
After elimination of redundant literals according to rules 2 or 5, reconsider the a-~ diagram exclusive of the complement- ed or uncomplemented row.
B. The Network Synthesis 24
After the a-~ diagram is simplified~ the synthesis
algorithm will be employed to obtain the required network
realization. The word3 11 gate 11 and"NAND gate"will be used
interchangeably in this algorithm.
The concept of a level or stage of gating used in the synthesis algorithm will be as described by Gimpel (6). A
gate in a network is said to be a first-stage gate (or to be
on level one) if it is an output gate. A gate is said to be
an n th-stage gate ( or on 1 eve 1 n ) 1'f 1't f ee d s only an ( n-1 )th_
stage gate (or gates). If a network is loop free~ i.e. free of feedback loops, then such a numbering scheme is well de-
fined. The networks synthesized by the following algorithm will be loop free. So as not to disrupt the flow of the algorithm from step to step, the algorithm will simply be stated. Justi
fication for the steps will follow.
1. The Synthesis Algorithm
Step 1.
Does the a-~ diagram contain only uncomplemented vari- ables? If it does, go to step 2. If it does not, go to step 3. Step 2. synthesize the function that is diagrammed, f, by using two levels of logic. The variables on each row form the in puts to second-level gates, one gate for each row. The out puts of these gates are the inputs to a first-level gate.
The output of this gate is f. This procedure is illustrated in Figure 6. 25
c A B c
D E F f G H I
a-p diagram satisfying conditions of step 2.
The variables A, B, C,
etc. are generalized
and all functions of
the same variables.
Figure 6. Illustration of algorithm step 2
Does the a-p diagram contain a row with a single comple mented variable? If it does, go to step 4. If not, go to
step 5. Step 4. Remove from the a-p diagram that row whose entries are all the same complemented variable, say A. The new a-p dia gram represents f 1 where f = f 1 + A. f 1 is then synthesized by applying the algorithm to its a-p diagram starting with step 1. The variable A is input to the output gate for f 1 . With the addition of the A input the output of this gate is now the desired function, f. The general procedure is illus- trated in Figure 7(a) with a specific example in Figure 7(b). 26
- f == fl + A
(a)
A B c
D.. E F - - - G G G - G G G
and finally
c---t.._____.
f
(b)
Figure 7. Illustration of algorithm step 4 27
Step .5..
Does the a-~ diagram contain only complemented variables? If it does, go to step 6. If not go to step 7. Step 6.
Form the complement of the a-~ diagram, a-~. Synthesize
a-~ with two levels of logic as in step 2. The output of the
network obtained is f. The desired function, f, is obtained
by using f as the input to a single-input gate. The output
of this gate is f. This step is illustrated in Figure 8.
-A -D - B -E
--c F
a-~ diagram for f
c ----1.____., f
Figure 8. Illustration of algorithm step 6
Step ']_.
Does the a-~ diagram consist of only complemented and uncomplemented columns? If it does, go to step 8. If not, go to step 9· 28
Step 8.
Synthesize the function, f, with a TANT network. The variables in each complemented column are the inputs to third-level gates, one gate for each column. The outputs of all third-level gates are inputs to all second-level gates, one for each row, along with the uncomplemented variables in each row. The outputs of the second-level gates are inputs to the first-level gate. The output of the first-level gate is f. This is illustrated in Figure g. - - A A B c D - D c D -A A - - D B D A A - - A A D c B
a-~ diagram of f
A A c B
A B ---1 c D--~~....,__,..., D
f
B D
A B
Figure g. Illustration of algorithm step 8
--·------29
Step 2.·
Does the a-~ diagram contain an uncomplemented row? If
it does~ go to step 10. If not, go to step 11.
Step 10.
The uncomplemented row in the a-~ diagram for the func
tion~ f~ is removed. The removed row represents f 2 and the
remaining a-~ diagram represents f 1 where f = f 1 + f 2 . The
diagram of f 1 is then synthesized by applying the algorithm
to its a-~ diagram starting with step 3. The variables in
the uncomplemented row are the inputs to a single gate. The
output of this gate~ which is f 2 , is then input to what was
the output gate of f 1 • The output of this gate is now the desired function f. This procedure is illustrated in Figure
10.
A I B I c A B c
[
Figure 10. Illustration of algorithm step 10 30 step 11.
Does the a-~ diagram have at least one complemented column? If it does, go to step 12. If not, go to step 13.
Step 12.
The variables in each complemented column are the inputs to third-level gates, one gate for each complemented column.
The outputs of all third-level gates are inputs to all second- level gates. There is one second-level gate for each row.
The literals in each row exclusive of those in the comple- mented columns are inputs to the second-level gates. If a literal in a complemented column is repeated in its row, it will be input to the second-level gate for that row. If a literal input at the second stage is a complemented variable, it will be formed by using a single-input gate as an inverter.
The outputs of the second-level gates are the inputs to the first-level gate. The output of this gate is the desired function f. This step is illustrated in Figure 11. ~~ffi rn
B
A f c
A
Figure 11. Illustration of algorithm step 12 31
Step l3_.
It is well known that two levels of NAND logic, or NAND -
NAND networks, are equivalent from terminal considerations to
AND - OR logic. Select the minimal sum of products expres- sion for the function that contains the fewest complemented variables. Synthesize the function with two levels of NAND circuitry as if synthesizing with AND - OR logic. If comple- mented variables are needed they will be obtained by using a single-input gate as an inverter on the third level.
A network synthesized by formal application of the algorithm may contain gates which feed the same gates and have identical inputs. All but one of these gates are re- dundant and may be removed. This simplification is so obvious that such gates would normally not be generated even though specified by the algorithm. This procedure is illustrated in Figure 12.
c -B c - - A B -B - c A c A B a-~ diagram for f
A
Redundant
B
Figure 12. Redundant gate removal 32
After the network has been realized, it may be possible to reduce the number of inputs. The following two rules will be helpful in the reduction.
Rule 1. Consider a gate, N1 , that has as inputs
the set of inputs { x} = x 1 , x 2 , . • · xn
and the outputs of at least two gates, N2 and N3. Also assume that {x} is a set of
inputs to N2 along with the set of inputs
{y} = y 1 , y 2 , .•. yn~none of whose ele ments are included in {x}. Further assume
at least one of the inputs {y}, y 1,is an
input to N3 . The input to N1 from N3 is redundant and may be removed. This is
illustrated for the general case in Figure
13(a). A more specific example is shown in
Figure 13 (b) .
{x} {- {y} {--
Figure l3(a). Illustration of rule 1 33
Inputs marked by an X are redundant and may be removed.
A B B ------1 f B c
C-----1...___
Figure 13(b). Illustration of rule 1
Rule 2. Consider a gate, N1, that has among its
inputs the output of a gate, N2 . Suppose
further that N2 feeds only N1 and that N1
and N2 have some common inputs, x 1 , x 2 , . x . These inputs are redundant in n puts to N2 and may be removed. This is illustrated in Figure 14.
Inputs marked by an X are redundant and may be removed.
Figure 14. Illustration of rule 2 34
The following discussion is intended to support the synthesis algorithm and network simplification rules. As previously stated, it is well known that two levels of NAND logic is equivalent from a terminal point of view to two levels of AND - OR logic. This equivalent property is illus trated in Figure 15.
f 1 = AB CD = AB + CD f 2 = AB + CD (a) (b) Figure 15. Two-level equivalents
In general, if Boolean equations are arranged in a form where the output gate is an OR (sum of products of sums of products, etc.), they may be implemented in NAND logic simply by changing all gates in the AND - OR implementation to NANDs and complementing all single variable inputs to odd levels.
To illustrate this consider the Boolean function
f = A + BCD + BCD
The AND - OR network is 35
B D c
A J----f
D
and the equivalent NAND representation is c~-A-ID-t
B
D----t__ __.
If complemented variables are not available~ as is the assumption in this paper, single-input NANDs would be used to form C and D to give a total of five gates. If redundancy is added and f is factored as A + BD(C + D) + BC(C + D) a savings of gates may be obtained by using a single gate to generate the common factor. A NAND network using only four gates that represents this factored expression is
c f D 36
It 1s clear from the previous discussion that if a
Boolean function is to be implemented in NAND circuitry and
only uncomplemented inputs are available~ any variable that
appears complemented in the function must be an input to an
odd-level gate. Further~ from an extension of the two-level
NAND and AND - OR equivalence~ it is obvious that odd-level
NAND gates perform an equivalent OR operation with single
inputs complemented and even-level gates the AND operation.
From the foregoing illustration and discussion one can
deduce that when implementing a Boolean function in NAND
logic~ it is desirable to arrange the function in a form where the output gate is an OR with all occurrencesof comple mented variables appearing singly in a sum. Complemented variables appearing singly in a sum corresponds to the vari able itself as an input to an equivalent OR~ or odd-level gate~ in the NAND realization. Also~ the judicious addition of redundancy and factoring in such a manner that common factors are obtained corresponds to the sharing of gates in the network realization.
The addition of redundancy and proper factoring of a function to produce a minimum or near minimum NAND network is easily implemented through use of the a-~ diagram.
Akers has shown that reading the a-~ diagram horizon tally corresponds to logical multiplication and that reading vertically corresponds to logical addition. A sum of pro ducts expression may be read by forming the logical sum of the rows. Likewise~ a product of sums expression may be 37
read by forming the logical product of the columns. An illustration of this is shown in Figure 16.
~ c A
~ A c = (A+ C + B)(A + C) A B
Figure 16. Illustration of reading the a-~ diagram
Multilevel expressions may be obtained by combinations of
the above two procedures. Thus, multilevel forms of the example are:
f = AC + A(C + B) and
f = (A+ c)(A + C) + AB
Akers has also shown that one may let a section of an
a-~ diagram be represented by a new variable. Consider such a modification of Figure 16 shown in Figure 17.
c D A
A B
Figure 17. Modification of Figure 16
One method for reading this diagram yields f = CD + AD + AB where D =A + C. Therefore f = C(A +C) + A(A +C) + AB.
With the preceeding discussion in mind, attention will
now be focused on the individual steps of the algorithm. An a-~ diagram which satisfies the conditions of each step will be shown. The algebraic expression will be read and the 38
resulting network indicated.
An a-p diagram satisfying the condition of step 1 is
A B
C B
The two-level sum of products expression for this diagram is read as AB + BC. By application of step 2 the NAND network is
A B
AB + BC
B c whose output is the desired function as indicated.
An a-p diagram satisfying the condition of step 3 is
B c -- A A
The sum of products expression for this diagram is A + BC and by application of step 4 the required NAND realization is
B c ----l..___ A+ BC A---1.___ 39
Clearly, the removal of a row with a single complemented
variable is equivalent to forcing this complemented variable
to appear singly in the sum. The simplest implementation
will show this variable as an input to the output gate. The
conditions of step 5 are satisfied by the following a-~
diagram. The complement a-~ diagram, a-~, is also shown.
~ ~ B c ~ ~ ~ A c ~
a-~ a-~
The complement of the function is read from a-~ as c + AB. By step 6 the desired function is synthesized by the follow- ing network,
c
= CA + CB
A
B
the output of which is the function read from the a-~ diagram.
An a-~ diagram containing all complemented variables usually requires a large number of inverters at the input. Comple- mentation of the a-~ diagram has the effect of performing this complementation with a single inverter on the output.
As an example of an a-~ diagram that fulfills the con- dition of step 7, consider that of the EXCLUS!VE-OR func tion AB + AB shown below. The breakdown of the diagram by 40
step 8 is also shown to indicate how the procedure of remov ing a complemented column is equivalent to the addition of redundancy so that a gate may be shared.
- A B - B A
The expression read in this manner is A(A + B) + B(A + B) and the resulting NAND network is
A------~
+ B(A + B)=
The conditions of step 9 are satisfied by the next a-{3 diagram.
A B - c A - A c
The sum of products expression is AB + AC + AC. Implementa- tion by step 10 provides a gate for the term AB on the second level as shown in the resulting network below. 41
A B
A(A + C) + c(A + c) = AB + AC + AC
Prime implicants with no complemented variables have been
termed "frontal prime implicants" by McCluskey (5). The variables of such terms will appear as inputs to a second-
level gate in the minimum network realization.
An a-~ diagram which satisfies the condition of step 11
is shown below.
The multilevel expression A(B + A) + C(A + B) may be ~ead so
that the third-level gate generating A+ B may be shared.
The network which results by application of algorithm step
12 is 42
A C(A + B) + A(A + B) B BC + AB = "Ac + Ai3 c--
The reading of complemented columns in this manner allows for
sharing of gates on the third level and reduces the number of
gates that must be used as inverters to generate complemented
variables.
Support will now be given to the input simplification
rules. The function realized by the network of Figure 13(b)
before application of rule 1 is
A(A + B)(B +C) + B(A + B)(B +C) + C(A + B)(B +C)
After application of rule 1~ the function realized is
A(A + B) + B(A + B)(B + C) + C(B + C) It can easily be shown that the two expressions are logically equivalent. Application of rule 1 is an application of the
Boolean simplification theorem x(x + Y) (Y + z) = x(x + Y) The output of the network in Figure 14 before the appli- cation of input reduction rule 2 is
It is clear that x 1 and x 2 are redundant in the term x 1x 2x 3 . 43
Application of rule 2 removes these redundant literals by application of the Boolean identity X+ XY =X+ Y.
In some cases when a large a-~ diagram is encounteredJ it may be advantageous to decompose the diagram into smaller diagramsJ each corresponding to a subfunction of the original
Boolean expression. This will be most desirable with dia grams that are to be synthesized by application of step 13, which results in a two-level network plus inverters on some inputs.
A description of the process of decomposition using a-~ diagrams is given by Akers (1). Given the diagram of a function FJ cut the a-~ diagram into smaller a-~ diagrams
G and H. H and G may now be synthesized independently. A network realization of F may be obtained by combining the outputs of the networks realizing G and H in a manner similar to that shown in Figure 10. This procedure is illustrated in Figure 18.
F
a-P diagram of F
G H
H
Figure 18. Decomposition of a diagram 44
In decomposing the a-~ diagram one should usually
attempt to form smaller a-~ diagrams which rank higher on
the priority list (see page 23) than the original diagram. 2. Extension to NOR Synthesis
The NOR function is the dual of the NAND. To synthesize
a given function using NOR gates, obtain the a-~ diagram as
in synthesis with NANDs. Form the dual a-~ diagram before
any simplification is employed. As previously described,
the dual a-~ diagram is formed by simply interchanging the
a-set and ~-set. The dual a-~ diagram is then simplified
as described for NAND synthesis. The algo~ithm can then be applied directly to the dual a-~ diagram, substituting
NOR gates for NANDs in the final network realization. This procedure is simply that of taking the dual of the given func
tion twice, once forming the dual a-~ diagram and once by re placing NAND gates with NOR gates.
3. Worked Examples In order to illustrate the diagrammatic procedure pre sented in this paper, three examples will be worked in detail.
EXAMPLE PROBLEM 1. Design a NAND circuit which realizes
the switching function, x, shown
mapped below. CD AB 00 01 11 10
0 0 0 0 0 0 0 1 0 1 0 0
1 1 1 1 0 1
1 0 0 0 0 1 45
There is only one minimal sum of products expression and one minimal product of sums expression. Therefore, the a-set is easily determined as
and the [3-set is
{ CD, BC, AD}
The a-[3 diagram is then constructed and is shown below.
The row and column labels are retained for clarity.
CD BC AD - ABC c B A - BCD c B D - ACD D c A
Since each square contains only one literal no simplification is necessary. The algorithm is then applied to the a-[3 dia- gram. The conditions of algorithm step 7 are the first to be satisfied and the network is synthesized by step 8. The
NAND realization is
A
B
c B X D D
A c 46
This function has been synthesized by Ellis (7). In that work the solution was arrived at by a partly systematic
and partly trial and error procedure. The synthesis by the
algorithm of this paper is simple and straight-forward,follow
ing only well defined steps.
EXAMPLE PROBLEM 2. Design a NAND circuit which realizes
the switching function, y, shown
mapped below.
CD A B 00 01 11 10
0 0 1 0 0 1
0 1 1 1 1 1
1 1 1 0 1 1
1 0 1 1 1 1
Solution: The a-set is determined from the logical multi plication of the two minimal sum of products expressions
yl = D + AB + AB + AC
y 2 = D + AB + AB + BC
After this multiplication and the allowed simplification
yly2 = D + AB + AB + ABC from which the a-set is
{ D, AB , AB , ABC}
There is one minimal product of sums expression from which
the ~-set is determined as
{ ABD, ABCD }
The a-~ diagram is then constructed and is shown below. 47
ABD ABCD - D D -D - AB A B
AB B -A
ABC AB c
The removal of either A or B in the bottom row is arbitrary.
For this example, B will be removed. The algorithm is then applied to the a-~ diagram and the complemented row, D, is removed by step 4. The resulting diagram is
A B - B A
A c to which the algorithm is applied. The conditions of step 9 are the first to be satisfied and the uncomplemented row is removed by step 10. The remaining diagram GI!J GI!J is synthesized by step 8. The result of thissynthesis is
A
B 48
With the addition of the gate for the uncomplemented row and the input to the output gate for the complemented row, the synthesis 1s complete and the NAND realization is
A
A y B
EXAMPLE PROBLEM 3. Design a NAND network which realizes
the switching function, z, shown
mapped below.
CD AB 00 01 11 10
00 l l 0 1 01 0 l 0 1
ll 0 0 l 0
10 0 l 0 1
The a-set is easily determined from the two minimal sum of products expression as
{ ABCD J ACD' ACD J BCD J BCD J ABCD}
There is one product of sums expression from which the ~-set is determined as 49
{Acfi, BCD , ABD , ABC, ACD, BCD}
The a-~ diagram before simplification is
BCD ABD ABC ACD BCD -- ABCD CD CD --AB AB A B - ACD c -c AD A AD D - - :A ciS D D A AC -AC c
BCD c c BD 13 D BD
BCD D D B BC c BC
ABCD A B D c CD CD
The redundant literals are removed according to the
simplification priority. The diagram for z is then
- --- - c c A A A - B - - c - c A - A D D - - - D -D A A c c 1--·- - - c -c B B D D - D --D B - B c c
A B D c D D
The uncomplemented row is removed by step 10 and the resulting diagram is synthesized by step 12 as 50
B c--r--..... c D
D---1...___ A
B
With the addition of the gate for the removed uncornplernented row , the final network is
A 51
The input to gate n marked by an X is redundant and is re moved by input reduction rule 1. This function has been synthesized on page 149 of Maley and Earle (4) using a map factoring technique. Considerably less effort was involved using the technique of this paper. 52
CHlU'TER III
SUMMARY
The general approach to the synthesis of NAND logic
networks presented in this paper differs considerably from
the algebraic and map methods. It has been assumed here
that complemented variables are not available as network
inputs. Akers was the first to suggest synthesis of Boolean functions through the use of an a-p diagram. The author's development is a modification of Akers• work to produce minimal NAND-NOR networks. This diagrammatic approach yields minimal or near minimal networks without the com plexities of trial and error procedures inherent in the algebraic and map methods. The synthesis algorithm of this paper consists of a set of well defined steps leading directly from an arbitrary Boolean expression to the final network. It is applicable to both completely and incom pletely specified Boolean functions. 53
BIBLIOGRAPHY
1. SMITH, R. A., Minimal Three-Variable NOR and NAND Logic Circuits, IEEETEC, Vol. EC-14, No. 1, pp. 79-82, February, 1965.
2. DIETMEYER, D. L. and SCHNEIDER, P. R., A Computer Oriented Factoring Algorithm for NOR Logic Design, IEEETEC, Vol. EC-14, No. 6, pp. 868-874, December, 1965.
3. HELLERMAN, L., A Catalog of Three Variables OR-Invert and AND-Invert Logical Circuits, IEEETEC, Vol. EC-12, No. 3, pp. 198-223, June, 1963.
4. MALEY, G. A. and EARLE, J., The Logical Design of Tran sistor Digital Computers, Prentic Hall, Englewood Cliffs, Jew Jersey, 1963.
5· McCLUSKEY, E. J., Logical D~sign Theory of NOR Gate Net work with No Complemented Inputs, Proc. Fourth Annual Symposium on Switching Circuit Theory and Logical Design, Chicago, Illinois, pp. 137-148, October, 1963.
6. GIMPEL, J. F., The Synthesis of TANT Networks, IEEE Con ference Record on Switching Theory and Logical Design, Ann Arbor, Michigan, pp. 105-125, October, 1965. 7· ELLIS, D. T., A Synthesis of Combinational Logic with NAND or NOR Elements, IEEETEC, Vol. EC-14, No. 5, pp. 701-705, October, 1965. 8. AKERS, s. B., Jr., A Diagrammatic Approach to Multilevel Logic Synthesis, Proc. of the Fifth Annual Symposium on Switching Circuit Theory and Logical Design, Princeton, New Jersey, pp. 165-173, October, 1964. IEEETEC, Vol. EC- 14, No. 2, pp. 174-181, April, 1965. 9. AKERS, s. B., Jr., A Truth Table Method for the Synthesis of Combinational Logic, IEEETEC, Vol. EC- 10, No. 4, pp. 604-615, December, 1961. VITA
The author was born on October 21, 1940, in Berwyn,
Illinois. He received his primary education in Berwyn,
Illinois and graduated from J. Sterling Morton High School in Cicero, Illinois in 1958. He was awarded the Iowa State
Club of Chicago Scholarship and obtained a Bachelor of
Science degree from Iowa State University in Ames, Iowa in May, 1962.
He was enrolled in the Graduate School of the University of Missouri at Rolla in September, 1962 and held a graduate assistantship in Electrical Engineering until June, ~963.
He joined the staff of the Electrical Engineering Department in September, 1963 as a half time instructor and since June, 1964 has held a full time appointment.
Mr. Nelson is a member of Phi Eta Sigma, Kappa Mu
Epsilon, Tau Beta Pi, Eta Kappa Nu, and the Institute of
Electrical and Electronics Engineers.