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Design of a High Reliability Self Diagnosing Computer Using Bit Slice Microprocessors

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Design of a High Reliability Self Diagnosing Computer Using Bit Slice Microprocessors North-Holland 325 Microprocessing and Microprogramming 22 (1 988) 325-331 Design of a High Reliability Self Diagnosing Computer Using Bit Slice Microprocessors S. Sanyal and P.V.S. Rao 2. Design Options Computer Systems & Communications Group, Tata Institute of FundamentalResearch, Bombay-400005, India 2.1 Functional Design This paper describes a processor built to meet the require- ments for a highly reliable and ruggedised digital computer. To achieve the desirable level of reliability and Innovative techniques were used to achieve high performance speed, several design options were considered: without using very high reliability components or redundancy at the circuit level. The processor therefore was designed us- (a) In a standard design using very high reliability ing moderately reliable components (mil B standard) with mi- components (MIL A Standard), the cost factor is croprogrammed control logic and powerful built-in microdi- prohibitive. Also a standard design using MIL A agnostic capabilities. It was successfully used for two major applications: a digital switching system and a data acquisition standard components still presupposes continuous and processing system for a weather radar. functioning of the components. The probability of failure is reduced, but the time required for repair Keywords: Reliability, Microprogramming, Microdiagnostics. does not decrease. 1. Introduction (b) Using moderately reliable components (MIL B Standard) in a design which provides for automatic A need arose for the development of a rugged digit- fault identification permits quick replacement of the al computer to form the nucleus of complex online faulty submodule. A high Mean Time Between systems required for two major applications: a gen- Failures and a low Mean Time to Repair can both eral purpose medium-size digital switching system be achieved. [I] and a data acquisition and processing system for a weather radar. (c) Triple Modular Redundancy (TMR) (where These applications called for high computational processors and checking circuits are triplicated and speed (250 k instructions/second), reliability a majority 2 out of 3 voting logic is used to detect a ('MEAN TIME BETWEEN FAILURE' greater faulty processor) would be extremely costly. It can than 1000 hours), ruggedness, ease of maintenance also turn out to be a self defeating exercise as the ('MEAN TIME TO REPAIR' less than 30 minutes) rate of failure increases due to the additional hard- and easy transportability. The machine which was ware. developed to meet these requirements, though tight- ly constrained in terms of performance, provided a 2.2 Choice of Technology stimulating challenge and ample scope for design innovation. Three options were considered regarding the choice The basic objective of developing a highly reli- of architecture and technology: able computer was achieved, not through the usage of highly reliable components, but through a novel (a) Standard fixed format processor: The functional and innovative microprogrammed scheme. In this blocks for the Data Path and Control Section design, microdiagnostic facilities were provided for shown in Fig. 1 are available in single chips in sever- powerful fault-detection and fault-location capabil- al standard microprocessor families: INTEL 8085, ities. ZILOG Z80 or MOTOROLA 6800. 326 S. Sanyal, P. V.S. Rao / Self Diagnosing Computer DIN BUS I BH,F.ER I SH,FTE. I IO'N REG'BTE"I I I/O BUS (DATA) [ .EG,ST~RS I OREG'STER I ATA IN I I PERIPHERAL I DO~TR~GISTE. I I MEMORYMAIN DEVICES I ARITHMETIC BIT LOGIC UNIT I/O BUS (ADDRESS)T SLICES I ~A~2U_T ......... DOUT BUS DATA PATH,I/OBUS, MEMORY ~ PERIPHERAL DEVICES From I/O BUS ( Dote ) IRt,. BRANCH [NPUTS ~° f s~ ...... i IR DECODE I BRANCH CONDITION MULTIPLEXER ] ROM (1KXg) 3 t9 3 3 / CONTROL t ,_LMOLT.PLEXER BITS 9 t NEXT ADDRESSAD FIELDS CONTROL SECTION Fig. 1. BLOCK DIAGRAM OFTHE 16 BIT COMPUTER The Standard Processor approach has the following Integrated circuit (MSI & SSI) logic modules (Reg- problems: isters, Counters, Gates etc.). This approach prov- ides adequate scope for original design of the pro- i. The Fixed Format Instruction Set and Architec- cessors and for incorporating the desired reliability ture of these microprocessors do not allow the features. It also makes it possible to achieve higher designer any flexibility for implementing his own processing speed by using fast components: Schott- architecture. ky Transistor Transistor Logic (S-TTL), Emitter Coupled Logic (ECL) and so on. ii. The processing speed of these microprocessors (which typically have an 8 MHz clock rate) can- (c) Design based on bit slice microprocessors: Cir- not cope with the processing load generated in a cuits consisting of hundreds of MSI and SSI chips real time control application. can be replaced by a few Bipolar Bit Slice Micro- processor Chips and appropriate support chips. iii. Additional reliability features cannot be built The 16 bit data path in Fig. 1 can be completely de- into such a design because the control section is signed using four 4 bit slices. This approach yields a 'hard wired'. speed improvement by a factor of 10 over fixed for- (b) MSI and SSI implementation: It is possible to mat microprocessors. design processors using Medium and Small Scale Another advantage is modularity. Bit-slice mi- S. SanyaL P.V.S. Rao / Serf Diagnosing Computer 327 croprocessors are normally four-bit wide. Com- were incorporated selectively to provide a direct in- puters of any wordlength can be configured using dication of some types of failures. the required number of slices. Normally, bit slice microprocessors are designed with Schottky and Lowpower Schottky TTL's. 3. Implementation Hence, it is possible to achieve microcycle times down to 100 ns from these chips. They are also use- 3.1 Description ~['the Basic Central Processor Logic' ful for making specialized controllers (e.g. disk con- trollers). Fig. 1 shows a block diagram of the basic processor A comparative study of different bit-slice proces- (datapath and control section). Am 2901 (Ad- sors may be found in Table 1. It is obvious from vanced Micro Devices) bit slices are the main com- Table 1 that Am 2901 is the most suitable choice. ponents of the datapath. Each 4 bit slice contains sixteen four bit two port addressable registers, a 2.3 Diagnostic' Methodology four bit Arithmetic Logic Unit and shifter logic (capable of I bit right or left shift or no shift); a four Self checking of the system is carried out on a time bit expandable Q register provides the facility for shared basis with the actual processing work. double word operations. Whenever the operating system goes to an 'idle' state, waiting for a process to be initiated, the diag- 3.1.1 Arithmetic Logic Unit nostic routine is invoked. This is assigned a low The arithmetic logic unit provides appropriate flags priority so that real time processes of higher prior- for storage of control information resulting from an ity do not suffer due to unavailability of the system. operation: In the diagnostic phase, microdiagnostic routines check the data path and the control logic complete- (a) the sign (N) bit is set if any arithmetic operation ly. These are much faster than conventional diag- generates a 2's complement negative number. nostic routines written in machine language. Another advantage of microdiagnostic routines is (b) the zero (Z) bit is set if the result of any opera- that they can check hardware very effectively at a tion is zero. much finer level. In addition, hardware checkers (c) the carry (C) bit is set if the result produces a car- Table 1. ry. Manufac- Device Logic Bit Speed Power PCB Availabili- (d) the overflow (V) bit is set if the result of any op- turer family slice supply design ty eration exceeds the permitted range [2's comple- width levels of Mil ment numbers can range over + (2"- 1) to -2 n if the required SPEC version wordlength is n bits]. Advanced Am 2901 Low 4 100ns 1 Not diffi- Available 3.1.2 Input/Output Bus power cult microdevi- (AM D Shottky The Input/Output (I/O) bus provides the means for ces hand- TTL the processor to communicate with the peripheral book) devices. Internally, the Din Bus and the DOut Bus 1976 are used for addressing and data transactions. The Signetics 3000 Shottky 2 100ns 1 Notdiffi- Available Din Register, DOut Register and the Address Reg- TTL cult ister (AR) function as the respective buffers. Motorola MC10800 ECL 4 55ns 2 Difficult Not avail- able 3.1.3 Control Section at time of (a) The control memory: This Read Only Memory design (ROM) holds the main microprogram routine for 328 S. Sanyal, P. V.S. Rao / Seff Diagnosing Computer instruction execution, 'exception' handling, console iv. Variable Bus SL~nal Deskew: In the asynchro- switch control and microdiagnostics. Instruction nous I/O bus, it is necessary to allow for some Register Decode (IRD) circuitry decodes the in- delays between control signals and the cor- structions and generates the appropriate starting responding qualifying signals arising from skew microaddresses in each case. along the long bus. It is necessary to deskew these signals suitably. A variable deskew facility (b) The basic design: The design incorporates a was implemented for greater time saving. Since number of special features, some of which are ex- the memory sits in close proximity to the pro- plained here: cessor, the deskew time for memory was fixed at a low value (25 ns). The deskew time for peri- The Pipeline Microdata Register: This register is pheral devices was fixed at 150 ns since these are situated at the output of the ROMs; it clocks situated at a distance on the bus. and holds microbits for one clock cycle. During this time, the contents of the next microaddress V.
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