A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks
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Synthesis and Verification of Digital Circuits Using Functional Simulation and Boolean Satisfiability
Synthesis and Verification of Digital Circuits using Functional Simulation and Boolean Satisfiability by Stephen M. Plaza A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Computer Science and Engineering) in The University of Michigan 2008 Doctoral Committee: Associate Professor Igor L. Markov, Co-Chair Assistant Professor Valeria M. Bertacco, Co-Chair Professor John P. Hayes Professor Karem A. Sakallah Associate Professor Dennis M. Sylvester Stephen M. Plaza 2008 c All Rights Reserved To my family, friends, and country ii ACKNOWLEDGEMENTS I would like to thank my advisers, Professor Igor Markov and Professor Valeria Bertacco, for inspiring me to consider various fields of research and providing feedback on my projects and papers. I also want to thank my defense committee for their comments and in- sights: Professor John Hayes, Professor Karem Sakallah, and Professor Dennis Sylvester. I would like to thank Professor David Kieras for enhancing my knowledge and apprecia- tion for computer programming and providing invaluable advice. Over the years, I have been fortunate to know and work with several wonderful stu- dents. I have collaborated extensively with Kai-hui Chang and Smita Krishnaswamy and have enjoyed numerous research discussions with them and have benefited from their in- sights. I would like to thank Ian Kountanis and Zaher Andraus for our many fun discus- sions on parallel SAT. I also appreciate the time spent collaborating with Kypros Constan- tinides and Jason Blome. Although I have not formally collaborated with Ilya Wagner, I have enjoyed numerous discussions with him during my doctoral studies. I also thank my office mates Jarrod Roy, Jin Hu, and Hector Garcia. -
Logic Optimization and Synthesis: Trends and Directions in Industry
Logic Optimization and Synthesis: Trends and Directions in Industry Luca Amaru´∗, Patrick Vuillod†, Jiong Luo∗, Janet Olson∗ ∗ Synopsys Inc., Design Group, Sunnyvale, California, USA † Synopsys Inc., Design Group, Grenoble, France Abstract—Logic synthesis is a key design step which optimizes of specific logic styles and cell layouts. Embedding as much abstract circuit representations and links them to technology. technology information as possible early in the logic optimiza- With CMOS technology moving into the deep nanometer regime, tion engine is key to make advantageous logic restructuring logic synthesis needs to be aware of physical informations early in the flow. With the rise of enhanced functionality nanodevices, opportunities carry over at the end of the design flow. research on technology needs the help of logic synthesis to capture In this paper, we examine the synergy between logic synthe- advantageous design opportunities. This paper deals with the syn- sis and technology, from an industrial perspective. We present ergy between logic synthesis and technology, from an industrial technology aware synthesis methods incorporating advanced perspective. First, we present new synthesis techniques which physical information at the core optimization engine. Internal embed detailed physical informations at the core optimization engine. Experiments show improved Quality of Results (QoR) and results evidence faster timing closure and better correlation better correlation between RTL synthesis and physical implemen- between RTL synthesis and physical implementation. We elab- tation. Second, we discuss the application of these new synthesis orate on synthesis aware technology development, where logic techniques in the early assessment of emerging nanodevices with synthesis enables a fair system-level assessment on emerging enhanced functionality. -
Challenges and Solutions for Large-Scale Integration of Emerging
CHALLENGES AND SOLUTIONS FOR LARGE-SCALE INTEGRATION OF EMERGING TECHNOLOGIES A Dissertation IN Electrical and Computer Engineering and Physics Presented to the Faculty of the University of Missouri–Kansas City in partial fulfillment of the requirements for the degree DOCTOR OF PHILOSOPHY by Md Arif Iqbal B.Sc., Khulna University of Engineering and Technology, Khulna, Bangladesh, 2010 Kansas City, Missouri 2021 © 2021 MD ARIF IQBAL ALL RIGHTS RESERVED CHALLENGES AND SOLUTIONS FOR LARGE-SCALE INTEGRATION OF EMERGING TECHNOLOGIES Md Arif Iqbal, Candidate for the Doctor of Philosophy Degree University of Missouri–Kansas City, 2021 ABSTRACT The semiconductor revolution so far has been primarily driven by the ability to shrink devices and interconnects proportionally (Moore's law) while achieving incremental benefits. In sub-10nm nodes, device scaling reaches its fundamental limits, and the interconnect bottleneck is dominating power and performance. As the traditional way of CMOS scaling comes to an end, it is essential to find an alternative to continue this progress. However, an alternative technology for general-purpose computing remains elusive; currently pursued research directions face adoption challenges in all aspects from materials, devices to architecture, thermal management, integration, and manufacturing. Crosstalk Computing, a novel emerging computing technique, addresses some of the challenges and proposes a new paradigm for circuit design, scaling, and security. However, like other emerging technologies, Crosstalk Computing also faces challenges like designing large-scale circuits using existing CAD tools, scalability, evaluation and benchmarking of large-scale designs, experimentation through commercial foundry processes to compete/co- exist with CMOS for digital logic implementations. This dissertation addresses these issues by providing a methodology for circuit synthesis customizing the existing EDA tool flow, evaluating and benchmarking against state- of-the-art CMOS for large-scale circuits designed at 7nm from MCNC benchmark suits. -
Majority Logic Synthesis Luca Amarù, Eleonora Testa, Miguel Couceiro, Odysseas Zografos, Giovanni De Micheli, Mathias Soeken
Majority logic synthesis Luca Amarù, Eleonora Testa, Miguel Couceiro, Odysseas Zografos, Giovanni de Micheli, Mathias Soeken To cite this version: Luca Amarù, Eleonora Testa, Miguel Couceiro, Odysseas Zografos, Giovanni de Micheli, et al.. Major- ity logic synthesis. ICCAD 2018 - IEEE/ACM International Conference on Computer-Aided Design, Nov 2018, San Diego, United States. 10.1145/3240765.3267501. hal-01925946 HAL Id: hal-01925946 https://hal.inria.fr/hal-01925946 Submitted on 2 Dec 2018 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Majority logic synthesis (Embedded tutorial) Luca Amarù1 Eleonora Testa2 Miguel Couceiro3 Odysseas Zografos4 Giovanni De Micheli2 Mathias Soeken2 1Synopsys Inc., USA 2 EPFL, Switzerland 3Université de Lorraine, France 4imec, Belgium Abstract—The majority function hxyzi evaluates to true, if at s least two of its Boolean inputs evaluate to true. The majority function has frequently been studied as a central primitive in logic synthesis applications for many decades. Knuth refers to cout the majority function in the last volume of his seminal The Art of Computer Programming as “probably the most impor- tant ternary operation in the entire universe.” Majority logic sythesis has recently regained signficant interest in the design automation community due to nanoemerging technologies which a b cin operate based on the majority function. -
Designing a RISC CPU in Reversible Logic
Designing a RISC CPU in Reversible Logic Robert Wille Mathias Soeken Daniel Große Eleonora Schonborn¨ Rolf Drechsler Institute of Computer Science, University of Bremen, 28359 Bremen, Germany frwille,msoeken,grosse,eleonora,[email protected] Abstract—Driven by its promising applications, reversible logic In this paper, the recent progress in the field of reversible cir- received significant attention. As a result, an impressive progress cuit design is employed in order to design a complex system, has been made in the development of synthesis approaches, i.e. a RISC CPU composed of reversible gates. Starting from implementation of sequential elements, and hardware description languages. In this paper, these recent achievements are employed a textual specification, first the core components of the CPU in order to design a RISC CPU in reversible logic that can are identified. Previously introduced approaches are applied execute software programs written in an assembler language. The next to realize the respective combinational and sequential respective combinational and sequential components are designed elements. More precisely, the combinational components are using state-of-the-art design techniques. designed using the reversible hardware description language SyReC [17], whereas for the realization of the sequential I. INTRODUCTION elements an external controller (as suggested in [16]) is utilized. With increasing miniaturization of integrated circuits, the Plugging the respective components together, a CPU design reduction of power dissipation has become a crucial issue in results which can process software programs written in an today’s hardware design process. While due to high integration assembler language. This is demonstrated in a case study, density and new fabrication processes, energy loss has sig- where the execution of a program determining Fibonacci nificantly been reduced over the last decades, physical limits numbers is simulated. -
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization Shubham Raif,6,y, Walter Lau Neton,10,y, Yukio Miyasakao,1, Xinpei Zhanga,1, Mingfei Yua,1, Qingyang Yia,1, Masahiro Fujitaa,1, Guilherme B. Manskeb,2, Matheus F. Pontesb,2, Leomar S. da Rosa Juniorb,2, Marilton S. de Aguiarb,2, Paulo F. Butzene,2, Po-Chun Chienc,3, Yu-Shan Huangc,3, Hoa-Ren Wangc,3, Jie-Hong R. Jiangc,3, Jiaqi Gud,4, Zheng Zhaod,4, Zixuan Jiangd,4, David Z. Pand,4, Brunno A. de Abreue,5,9, Isac de Souza Camposm,5,9, Augusto Berndtm,5,9, Cristina Meinhardtm,5,9, Jonata T. Carvalhom,5,9, Mateus Grellertm,5,9, Sergio Bampie,5, Aditya Lohanaf,6, Akash Kumarf,6, Wei Zengj,7, Azadeh Davoodij,7, Rasit O. Topalogluk,7, Yuan Zhoul,8, Jordan Dotzell,8, Yichi Zhangl,8, Hanyu Wangl,8, Zhiru Zhangl,8, Valerio Tenacen,10, Pierre-Emmanuel Gaillardonn,10, Alan Mishchenkoo,y, and Satrajit Chatterjeep,y aUniversity of Tokyo, Japan, bUniversidade Federal de Pelotas, Brazil, cNational Taiwan University, Taiwan, dUniversity of Texas at Austin, USA, eUniversidade Federal do Rio Grande do Sul, Brazil, fTechnische Universitaet Dresden, Germany, jUniversity of Wisconsin–Madison, USA, kIBM, USA, lCornell University, USA, mUniversidade Federal de Santa Catarina, Brazil, nUniversity of Utah, USA, oUC Berkeley, USA, pGoogle AI, USA The alphabetic characters in the superscript represent the affiliations while the digits represent the team numbers yEqual contribution. Email: [email protected], [email protected], [email protected], [email protected] Abstract—Logic synthesis is a fundamental step in hard- artificial intelligence. -
Design of a High Reliability Self Diagnosing Computer Using Bit Slice Microprocessors
North-Holland 325 Microprocessing and Microprogramming 22 (1 988) 325-331 Design of a High Reliability Self Diagnosing Computer Using Bit Slice Microprocessors S. Sanyal and P.V.S. Rao 2. Design Options Computer Systems & Communications Group, Tata Institute of FundamentalResearch, Bombay-400005, India 2.1 Functional Design This paper describes a processor built to meet the require- ments for a highly reliable and ruggedised digital computer. To achieve the desirable level of reliability and Innovative techniques were used to achieve high performance speed, several design options were considered: without using very high reliability components or redundancy at the circuit level. The processor therefore was designed us- (a) In a standard design using very high reliability ing moderately reliable components (mil B standard) with mi- components (MIL A Standard), the cost factor is croprogrammed control logic and powerful built-in microdi- prohibitive. Also a standard design using MIL A agnostic capabilities. It was successfully used for two major applications: a digital switching system and a data acquisition standard components still presupposes continuous and processing system for a weather radar. functioning of the components. The probability of failure is reduced, but the time required for repair Keywords: Reliability, Microprogramming, Microdiagnostics. does not decrease. 1. Introduction (b) Using moderately reliable components (MIL B Standard) in a design which provides for automatic A need arose for the development of a rugged digit- fault identification permits quick replacement of the al computer to form the nucleus of complex online faulty submodule. A high Mean Time Between systems required for two major applications: a gen- Failures and a low Mean Time to Repair can both eral purpose medium-size digital switching system be achieved. -
Logical Equivalence Checking of Asynchronous Circuits Using Commercial Tools
Logical Equivalence Checking of Asynchronous Circuits Using Commercial Tools Arash Saifhashemi Hsin-Ho Huang Priyanka Bhalerao Peter A. Beerel∗ Intel Corporation Electrical Engineering Yahoo Corporation Electrical Engineering Santa Clara, CA University of Southern California Sunnyvale, CA University of Southern California Email: [email protected] Los Angeles, CA Email: [email protected] Los Angeles, CA Email: [email protected] Email: [email protected] Abstract—We propose a method for logical equivalence check generally cannot be used to compare CSP with decomposed (LEC) of asynchronous circuits using commercial synchronous versions because the decomposition often introduces pipelining tools. In particular, we verify the equivalence of asynchronous that changes the allowed sequence of events at the external circuits which are modeled at the CSP-level in SystemVerilog as interface. Therefore, some researchers only check critical prop- well as circuits modeled at the micro-architectural level using con- erties on the final decomposed design [15], [16]. ditional communication library primitives. Our approach is based on a novel three-valued logic model that abstracts the detailed Our proposed approach is different from the previous work handshaking protocol and is thus agnostic to different gate-level in the following ways: first, since it is focused on CSP- implementations, making it applicable to a variety of different level designs, it is implementation-agnostic and can be used design styles. Our experimental results with commercial LEC for design flows that target various asynchronous templates. tools on a variety of computational blocks and an asynchronous Secondly, compared to [11], we explicitly support modules microprocessor demonstrate the applicability and limitations of the proposed approach. -
Verilog HDL 1
chapter 1.fm Page 3 Friday, January 24, 2003 1:44 PM Overview of Digital Design with Verilog HDL 1 1.1 Evolution of Computer-Aided Digital Design Digital circuit design has evolved rapidly over the last 25 years. The earliest digital circuits were designed with vacuum tubes and transistors. Integrated circuits were then invented where logic gates were placed on a single chip. The first integrated circuit (IC) chips were SSI (Small Scale Integration) chips where the gate count was very small. As technologies became sophisticated, designers were able to place circuits with hundreds of gates on a chip. These chips were called MSI (Medium Scale Integration) chips. With the advent of LSI (Large Scale Integration), designers could put thousands of gates on a single chip. At this point, design processes started getting very complicated, and designers felt the need to automate these processes. Electronic Design Automation (EDA)1 techniques began to evolve. Chip designers began to use circuit and logic simulation techniques to verify the functionality of building blocks of the order of about 100 transistors. The circuits were still tested on the breadboard, and the layout was done on paper or by hand on a graphic computer terminal. With the advent of VLSI (Very Large Scale Integration) technology, designers could design single chips with more than 100,000 transistors. Because of the complexity of these circuits, it was not possible to verify these circuits on a breadboard. Computer- aided techniques became critical for verification and design of VLSI digital circuits. Computer programs to do automatic placement and routing of circuit layouts also became popular. -
Object-Oriented Development for Reconfigurable Architectures
Object-Oriented Development for Reconfigurable Architectures Von der Fakultät für Mathematik und Informatik der Technischen Universität Bergakademie Freiberg genehmigte DISSERTATION zur Erlangung des akademischen Grades Doktor Ingenieur Dr.-Ing., vorgelegt von Dipl.-Inf. (FH) Dominik Fröhlich geboren am 19. Februar 1974 Gutachter: Prof. Dr.-Ing. habil. Bernd Steinbach (Freiberg) Prof. Dr.-Ing. Thomas Beierlein (Mittweida) PD Dr.-Ing. habil. Michael Ryba (Osnabrück) Tag der Verleihung: 20. Juni 2007 To my parents. ABSTRACT Reconfigurable hardware architectures have been available now for several years. Yet the application devel- opment for such architectures is still a challenging and error-prone task, since the methods, languages, and tools being used for development are inappropriate to handle the complexity of the problem. This hampers the widespread utilization, despite of the numerous advantages offered by this type of architecture in terms of computational power, flexibility, and cost. This thesis introduces a novel approach that tackles the complexity challenge by raising the level of ab- straction to system-level and increasing the degree of automation. The approach is centered around the paradigms of object-orientation, platforms, and modeling. An application and all platforms being used for its design, implementation, and deployment are modeled with objects using UML and an action language. The application model is then transformed into an implementation, whereby the transformation is steered by the platform models. In this thesis solutions for the relevant problems behind this approach are discussed. It is shown how UML can be used for complete and precise modeling of applications and platforms. Application development is done at the system-level using a set of well-defined, orthogonal platform models. -
FAULT DETECTION in LOGICAL CIRCUITS by SAMPRAKASH MAJUMDAR, B.Sc.Engr
FAULT DETECTION IN LOGICAL CIRCUITS by SAMPRAKASH MAJUMDAR, B.Sc.Engr. A THESIS IN ELECTRICAL ENGINEERING Submitted to the Graduate Faculty of Texas Tech University in Partial Fulfillment of the Requirements for the Degree of MASTER OF SCIENCE IN ELECTRICAL ENGINEERING Approved c/ Accepted May, 1975 T3 ACKNOWLEDGMENTS I am deeply indebted to Dr. Jagadish C. Prabhakar for his continuous direction and encouragement, for his valuable hours of discussion, and for his serving as the chairman of my committee. I am also very thankful to Dr. Marion Hagler and Dr. Charles N. Kellogg for their constructive criticism and for serving on my committee. 11 TABLE OF CONTENTS ACKNOWLEDGMENTS ii LIST OF TABLES iv LIST OF FIGURES v Chapter I. INTRODUCTION 1 II. METHODS OF FAULT DETECTION 8 Path Sensitization 8 D-Algorithm 12 Fault Matrix 19 Boolean Difference 20 Partitioning 27 State-Table Analysis 28 III. GRAPH THEORETIC TECHNIQUES OF FAULT DETECTION 31 Graphical Representation 31 Structural Representation 32 Behavioral Description 39 Terminology and Notations 40 IV. CONCLUSIONS 61 REFERENCES 63 111 LIST OF TABLES Table Page I. Summary of Fault Detection Techniques 30 IV LIST OF FIGURES Figure Page 2.1. Example of path sensitization 9 2.2. Example of d-algorithm 14 2.3. D-Algorithm in sequential network 17 2.4. Breaking of sequential circuit 18 2.5. Example of Boolean difference 26 3.1. Serial binary adder 34 3.2. Partitioning of figure 3.1 35 3.2a. Graphical representation of figure 3.2 ... 36 3.2b. Graphical representation of figure 3.2 showing vertex 1 (adder) and vertex 2 (JK flip-flop) 36 3.3. -
Automated Synthesis of Unconventional Computing Systems
University of Central Florida STARS Electronic Theses and Dissertations, 2004-2019 2019 Automated Synthesis of Unconventional Computing Systems Amad Ul Hassen University of Central Florida Part of the Computer Engineering Commons Find similar works at: https://stars.library.ucf.edu/etd University of Central Florida Libraries http://library.ucf.edu This Doctoral Dissertation (Open Access) is brought to you for free and open access by STARS. It has been accepted for inclusion in Electronic Theses and Dissertations, 2004-2019 by an authorized administrator of STARS. For more information, please contact [email protected]. STARS Citation Ul Hassen, Amad, "Automated Synthesis of Unconventional Computing Systems" (2019). Electronic Theses and Dissertations, 2004-2019. 6500. https://stars.library.ucf.edu/etd/6500 AUTOMATED SYNTHESIS OF UNCONVENTIONAL COMPUTING SYSTEMS by AMAD UL HASSEN MSc Computer Science, University of Central Florida, 2016 MSc Electrical Engineering, University of Engineering & Technology Lahore, 2013 BSc Electrical Engineering, University of Engineering & Technology, Lahore, 2008 A Dissertation submitted in partial fulfilment of the requirements for the degree of Doctor of Philosophy in the Department of Electrical and Computer Engineering in the College of Engineering and Computer Science at the University of Central Florida Orlando, Florida Summer Term 2019 Major Professor: Sumit Kumar Jha c 2019 Amad Ul Hassen ii ABSTRACT Despite decades of advancements, modern computing systems which are based on the von Neu- mann architecture still carry its shortcomings. Moore’s law, which had substantially masked the effects of the inherent memory-processor bottleneck of the von Neumann architecture, has slowed down due to transistor dimensions nearing atomic sizes.