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An Optimal Power Supply and Body Bias Voltage for an Ultra Low Power Micro-Controller with Silicon on Thin BOX MOSFET

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An Optimal Power Supply and Body Bias Voltage for an Ultra Low Power Micro-Controller with Silicon on Thin BOX MOSFET An Optimal Power Supply And Body Bias Voltage for an Ultra Low Power Micro-Controller with Silicon on Thin BOX MOSFET Hayate Okuharay, Kuniaki Kitamoriy, Yu Fujitay, Kimiyoshi Usamiz, and Hideharu Amanoy yKeio University, 3-14-1 Hiyoshi, Kohoku-ku, Yokohama, Japan zShibaura Institute of Technology, 3-7-5 Toyosu, Kohtoh-ku, Tokyo, Japan yE-mail: fhayate,[email protected] zE-mail: [email protected] Abstract| Body bias control is an efficient means of Although a CPU with the SOTB was investigated in [2], it balancing the trade-off between leakage power and perfor- was not based on a performance and power model. mance especially for chips with silicon on thin buried oxide In the present work, we propose and examine a method (SOTB), a type of FD-SOI technology. In this work, a to find the optimal combination of supply voltage and back- method for finding the optimal combination of the supply gate bias for a micro-controller with the SOTB technique. voltage and body bias voltage to the core and memory is The main contributions of this paper are: proposed and applied to a real micro-controller chip using • A method is proposed to optimize the supply voltage SOTB CMOS technology. By obtaining several coefficients and back-gate bias for a real 32-bit micro-controller of equations for leakage power, switching power and op- implemented with a 65-nm SOTB CMOS technique in erational frequency from the real chip measurements, the which the core and memory are controlled indepen- optimized voltage setting can be obtained for the target dently. operational frequency. The power consumption lost by the • A theoretical model is proposed and examined through error of optimization is 12.6% at maximum, and it can save the evaluation results of a real chip. The accuracy of at most 73.1% of power from the cases where only the body the optimization ranged from 5.23% to 12.6%. bias voltage is optimized. This method can be applied to • By applying the proposed method, the total power can the latest FD-SOI technologies. be reduced by 73% without degrading performance. Keywords| Body bias control, Low power design, The rest of this paper is organized as follows. Section 2 de- Micro-controller, FD-SOI, SOTB. scribes the SOTB technique with a power and performance model. The model of consumed power and operational fre- I. Introduction quency is shown in Section 3. The target micro-controller is introduced in Section 4 and the parameters of the power Ultra low power micro-controllers that can maintain for and performance model are obtained from the real chip at least 10 years with a simple Li or solar battery are re- measurement. In Section 5, we show optimization exam- quired for the latest wearable computing and sensor nodes. ples and examine the effectiveness of the proposed tech- This performance requirement means that 32-bit micropro- nique. We conclude in Section 6 with a summary and a cessors that can work with a 20 MHz or higher clock are brief mention of future work. needed instead of the conventional tiny processors near the threshold level working with a hundreds of kilo Hertz oper- II. ational clock. To fulfill these requirements, a novel FD-SOI SOTB and back gate bias control technique called silicon on thin buried oxide (SOTB) has A. SOTB CMOSFET been developed [1] and implemented on low power micro- processors [2], accelerators [3], and FPGAs [4]. Silicon on thin buried oxide (SOTB) is a novel FD-SOI An important feature of SOTB is that it can control device developed by Low Power Electronics Association & the trade-off between performance and leakage current by Product (LEAP). Figure 1 shows a cross-sectional view of changing the back-gate bias. By giving reverse bias, the SOTB CMOSFET. Unlike other SOI devices, CMOSFET leakage current can be reduced while the delay is stretched is formed on a 10-nm ultra thin box layer. Since the FD- and forward bias can enhance the performance while in- SOI can suppress short channel effect (SCE), impurity dop- creasing the leakage current. Thus, optimization by chang- ing is not necessary. The variation of threshold level by the ing both the supply voltage and the back-gate bias is key random dopant fluctuation is reduced, which is why SOTB for taking full advantage of the SOTB technique. Finding MOSFET is suitable for operation with low voltage supply. the energy minimum point by controlling both the supply Since a transistor and back gate are separated by the box voltage and the back-gate bias has been widely researched layer, p-n junction leakage current between drain/source [5] [6][7]. However, from the viewpoint of designing practi- and substrate is also removed. Accordingly, compared with cal systems, minimizing the energy using the lower clock, conventional bulk CMOS processes, controllability of the which cannot satisfy the required performance, is useless. back gate is improved. The triple-well structure prevents Kao et al. [8] investigated optimization techniques from leakage current of the back gate bias control. This SOTB the practical viewpoint, but their study targeted only the structure enables to change characteristics by the control- functional units and used a conventional bulk technique. ling the power supply voltage and back gate biasing. Back Gate −7 10 10−7 nMOSFET nMOSFET 28-nm FDSOI at V =1.0V 28-nm FDSOI DD at Zero Bias 10−8 STI 10−8 P-well N-well 65-nm FDSOI 65-nm FDSOI 10−9 at V =0.4V at Zero Bias DD Leakage Current[A] Deep n-well Leakage Current[A] P-sub 10−9 −10 (a) (b) Box layer 0.4 0.6 0.8 1 1.2 10 -0.5 −0.3 −0.1 0.1 V VBN DD[V] [V] Fig. 1. Cross-sectional view of SOTB MOSFET: (a)pMOS (b)nMOS (a) (b) B. Power of LSIs Fig. 2. Leakage current of SOTBMOSFET (a)characteristics of VDD (b)characteristics of V BN In general, The consumption power of LSIs is represented as the reverse bias. Note that, with the reverse bias, delay 2 Pall = IleakVDD + αatfCVDD; (1) time increases. The leakage current also increases exponentially to V . where I is leakage current, α is activity factor, C DD leak at Note that, in the case of V , lower V results in lower is capacitance, and f is an operating frequency. The first DD DD switching power quadratic. term represents static power by the leakage current and the second one is the switching power of transistors. In the bulk C. Maximum operational frequency MOSFET, leakage current consists of (1) sub-threshold leakage current, (2) gate tunneling current, (3) gate in- In MOSFET, the gate delay is represented with the α duced drain leakage (GIDL), and (4) p-n junction leakage power low[9]. current. However, in the FD-SOI structure, GIDL and p-n CVDD td = k α (4) junction leakage current are suppressed in the normal us- (VDD − VTH ) age[1]. So we only need to consider the sub-threshold leak- Here, k is the process parameter, α is a parameter to age current and gate tunneling current. The sub-threshold consider velocity saturation in MOSFET, and V is the leakage current I is represented as TH sub threshold voltage. The maximum operational frequency − −V Vgs+η(Vds VDD )+Kγ Vsb ds f is proportional to the reciprocal of t . v max d Isub = Ioff 10 S (1 − e T ); (2) α (VDD − VTH ) where vT is thermal voltage, S is sub-threshold slope, fmax = F ; (5) VDD Ioff is the sub-threshold leakage current at Vgs = 0 and Vds = VDD, Kγ is a coefficient of the back gate bias, and η where F is a constant number related to frequency. The is a coefficient of the drain to source voltage[9]. threshold voltage (VTH ) varies due to the back gate biasing, The gate tunneling current Igt is and it can be linearly approximated as follows: tox VDD 2 −PB I = WP ( ) e VDD ; (3) gt A VTH = Vt0 − Kγ V BN; (6) tox where tox is thickness of gate oxide and W is gate width. where Vt0 is the threshold voltage with the zero bias[9]. PA and PB are constants determined by transistor pro- This equation, which is for nMOSFET, but can also be cess[9]. Leakage current of the transistor is, thus, an expo- used to represent pMOSFET, shows that the maximum nential function of VDD and back gate bias voltage. Figure operational frequency is also a function of VDD and back 2 shows the leakage from the sub-threshold leakage current gate voltage (V BN and V BP ). In nMOSFET, when V BN and the gate tunneling current in nMOSFET, including is higher than the source voltage, it is called the forward (a) the relationship to VDD and (b) the relationship to the bias that increases the maximum operational frequency. In back gate biasing. Here, V BN(V BP ) shows the back gate pMOSFET, when V BP is lower than the source voltage, it bias voltage given to nMOSFET(pMOSFET). Both figures is also called forward bias. Note that, the leakage current show results of SPICE simulation of ST micro's 28nm FD- increases exponentially with increasing forward bias. SOI and 65nm SOTB. The different process technologies re- From the practical viewpoint, a system like a micro- sulted in different the dominant leakage currents, but even controller must work at the operational frequency that sat- so, the leakage current increases exponentially to VDD and isfies the performance requirement.
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