1 Logic Synthesis for Quantum Computing Mathias Soeken, Martin Roetteler, Nathan Wiebe, and Giovanni De Micheli Abstract—Today’s rapid advances in the physical implementa- 1) Quantum computers process qubits instead of classical tion of quantum computers call for scalable synthesis methods to bits. A qubit can be in superposition and several qubits map practical logic designs to quantum architectures. We present can be entangled. We target purely Boolean functions as a synthesis framework to map logic networks into quantum cir- cuits for quantum computing. The synthesis framework is based input to our synthesis algorithms. At design state, it is on LUT networks (lookup-table networks), which play a key sufficient to assume that all input values are Boolean, role in state-of-the-art conventional logic synthesis. Establishing even though entangled qubits in superposition are even- a connection between LUTs in a LUT network and reversible tually acted upon by the quantum hardware. single-target gates in a reversible network allows us to bridge 2) All operations on qubits besides measurement, called conventional logic synthesis with logic synthesis for quantum computing—despite several fundamental differences. As a result, quantum gates, must be reversible. Gates with multiple our proposed synthesis framework directly benefits from the fanout known from classical circuits are therefore not scientific achievements that were made in logic synthesis during possible. Temporarily computed values must be stored the past decades. on additional helper qubits, called ancillae. An intensive We call our synthesis framework LUT-based Hierarchical use of intermediate results therefore increases the qubit Reversible Logic Synthesis (LHRS). Input to LHRS is a classical logic network, e.g., represented as Verilog description; output requirements of the resulting quantum circuit. Since is a quantum network (realized in terms of Clifford+T gates, qubits are a limited resource, the aim is to find circuits the most frequently used gate library in quantum computing). with a possibly small number of ancillae. Quantum The framework offers to trade-off the number of qubits for the circuits that compute a purely Boolean function are often number of quantum gates. In a first step, an initial network referred to as reversible networks. is derived that only consists of single-target gates and already completely determines the number of qubits in the final quantum 3) The quantum gates that can be implemented by current network. Different methods are then used to map each single- quantum computers can act on a single or at most two target gate into Clifford+T gates, while aiming at optimally using qubits [3]. Something as simple as an AND operation available resources. can therefore not be expressed by a single quantum gate. We demonstrate the effectiveness of our method in automati- A universal fault-tolerant quantum gate library is the cally synthesizing IEEE compliant floating point networks up to double precision. As many quantum algorithms target scientific Clifford+T gate set [3]. In this gate set, the T gate simulation applications, they can make rich use of floating point is sufficiently expensive in most approaches to fault arithmetic components. But due to the lack of quantum circuit tolerant quantum computing such that it is customary descriptions for those components, it can be difficult to find to neglect all other gates when costing a quantum a realistic cost estimation for the algorithms. Our synthesized circuit [6]. Mapping reversible functions into networks benchmarks provide cost estimates that allow quantum algorithm designers to provide the first complete cost estimates for a host of that minimize T gates is therefore a central challenge in quantum algorithms. Thus, the benchmarks and, more generally, quantum computing [7]. the LHRS framework are an essential step towards the goal of 4) When executing a quantum circuit on a quantum com- understanding which quantum algorithms will be practical in the puter, all qubits must eventually hold either a primary first generations of quantum computers. input value, a primary output value, or a constant. A circuit should not expose intermediate results to output I. INTRODUCTION lines as this can potentially destroy wanted interference effects, in particular if the circuit is used as a subroutine arXiv:1706.02721v1 [quant-ph] 8 Jun 2017 ECENT progress in fabrication makes the practical ap- R plication of quantum computers a tangible prospect [2], in a larger quantum computation. Qubits that neverthe- [3], [4], [5]. However, as quantum computers scale up to tackle less expose intermediate results are sometimes referred problems in computational chemistry, machine learning, and to as garbage outputs. cryptoanalysis, design automation will be necessary to fully leverage the power of this emerging computational model. It has recently been shown [8], [9], [10] that hierarchical Quantum circuits differ significantly in comparison to clas- reversible logic synthesis methods based on logic network sical circuits. This needs to be addressed by design automation representations are able to synthesize large arithmetic designs. tools: The underlying idea is to map subnetworks into reversible net- works. Hierarchical refers to the fact that intermediate results A preliminary version of this manuscript has been presented at the DAC computed by the subnetworks must be stored on additional 2017 conference [1]. M. Soeken and G. De Micheli are with the Integrated Systems Laboratory, ancilla qubits. If the subnetworks are small enough, one can EPFL, Lausanne, Switzerland. M. Roetteler and N. Wiebe are with Microsoft locally apply less efficient reversible synthesis methods that Research, Redmond, USA. do not require ancilla qubits and are based on Boolean satisfi- This research was supported by H2020-ERC-2014-ADG 669354 Cyber- Care, the Swiss National Science Foundation (200021-169084 MAJesty), and ability [11], truth tables [12], or decision diagrams [13]. How- the ICT COST Action IC1405. ever, state-of-the-art hierarchical synthesis methods mainly 2 suffer from two disadvantages. First, they do not explicitly y1 y2 y3 uncompute the temporary values from the subnetworks and 11 12 13 leave garbage outputs. In order to use the network in a quantum computer, one can apply a technique called “Bennett 7 8 9 10 trick” [14], which requires to double the number of gates and add one further ancilla for each primary output. Second, 1 2 3 4 5 6 current algorithms do not offer satisfying solutions to trade the number of qubits for the number of T gates. In contrast, many x1 x5 x4 x6 x7 x9 x8 x10 x11 x2 x3 algorithms optimize towards the direction of one extreme [10], Fig. 1. A 4-feasible network with 11 inputs, 3 outputs, and 13 gates. i.e., the number of qubits is very small for the cost of a very high number of T gates or vice versa. This paper presents a hierarchical synthesis framework separating it into two steps: synthesizing the mapping, de- based on k-feasible Boolean logic networks, which find use scribed in Sect. IV and mapping single-target gates, described in conventional logic synthesis. These are logic networks in in Sect. V. Section VI discusses the results of the experimental which every gate has at most k inputs. They are often referred evaluation and Sect. VII concludes. to as k-LUT (lookup table) networks. We show that there is a one-to-one correspondence between a k-input LUT in a logic II. PRELIMINARIES network and a reversible single-target gate with k control lines A. Some Notation in a reversible network. A single-target gate has a k-input A digraph G = (V; A) is called simple, if A ⊆ V × V , control function and a single target line that is inverted if i.e., there can be at most one arc between two vertices for and only if the control function evaluates to 1. The initial each direction. An acyclic digraph is called a dag. We refer reversible network with single-target gates can be derived − + to d (v) = #fw j (w; v) 2 Ag and d (v) = #fw j (v; w) 2 quickly and provides a skeleton for subsequent synthesis Ag as in-degree and out-degree of v, respectively. that already fixes the number of qubits in the final quantum network. As a second step, each single-target gate is mapped B. Boolean Logic Networks into a Clifford+T network. We propose different methods for the mapping. A direct method makes use of the exclusive- A Boolean logic network is a simple dag whose vertices sum-of-product (ESOP) representation of the control function are primary inputs, primary outputs, and gates and whose arcs that can be directly translated into multiple-controlled Toffoli connect gates to inputs, outputs, and other gates. Formally, a gates [15]. Multiple-controlled Toffoli gates are a specializa- Boolean logic network N = (V; A; F ) consists of a simple tion of single-target gates for which automated translations dag (V; A) and a function mapping F . It has vertices V = into Clifford+T networks exist. Another method tries to remap X [ Y [ G for primary inputs X, primary outputs Y , and − + a single-target gate into a LUT network with fewer number gates G. We have d (x) = 0 for all x 2 X and d (y) = 0 of inputs in the LUTs, by making use of temporarily unused for all y 2 Y . Arcs A ⊆ (X [ G × G [ Y ) connect primary qubits in the overall quantum network. We show that near- inputs and gates to other gates and primary outputs. Each gate Bd−(g) B optimal Clifford+T networks can be precomputed and stored g 2 G realizes a Boolean function F (g): ! , i.e., in a database if such LUT networks require sufficiently few the number of inputs in F (g) coincides with the number of gates.