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Synthesis and Verification of Digital Circuits Using Functional Simulation and Boolean Satisfiability

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Synthesis and Verification of Digital Circuits Using Functional Simulation and Boolean Satisfiability Synthesis and Verification of Digital Circuits using Functional Simulation and Boolean Satisfiability by Stephen M. Plaza A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Computer Science and Engineering) in The University of Michigan 2008 Doctoral Committee: Associate Professor Igor L. Markov, Co-Chair Assistant Professor Valeria M. Bertacco, Co-Chair Professor John P. Hayes Professor Karem A. Sakallah Associate Professor Dennis M. Sylvester Stephen M. Plaza 2008 c All Rights Reserved To my family, friends, and country ii ACKNOWLEDGEMENTS I would like to thank my advisers, Professor Igor Markov and Professor Valeria Bertacco, for inspiring me to consider various fields of research and providing feedback on my projects and papers. I also want to thank my defense committee for their comments and in- sights: Professor John Hayes, Professor Karem Sakallah, and Professor Dennis Sylvester. I would like to thank Professor David Kieras for enhancing my knowledge and apprecia- tion for computer programming and providing invaluable advice. Over the years, I have been fortunate to know and work with several wonderful stu- dents. I have collaborated extensively with Kai-hui Chang and Smita Krishnaswamy and have enjoyed numerous research discussions with them and have benefited from their in- sights. I would like to thank Ian Kountanis and Zaher Andraus for our many fun discus- sions on parallel SAT. I also appreciate the time spent collaborating with Kypros Constan- tinides and Jason Blome. Although I have not formally collaborated with Ilya Wagner, I have enjoyed numerous discussions with him during my doctoral studies. I also thank my office mates Jarrod Roy, Jin Hu, and Hector Garcia. Without my family and friends I would never have come this far. I would like to thank Geoff Blake and Smita Krishnaswamy, who have been both good friends and colleagues and who have talked to me often when the stress at work was overwhelming. I also want to thank Geoff for his patience being my roommate for so many years. I am blessed to iii also have several good friends outside of the department who have provided me a lot of support: Steve Kibit (Steve2 representin’), Rob Denis, and Jen Pileri. Most of all, I would like to thank my family who has been an emotional crutch for me. My mom, dad, and brother Mark have all been supportive of my decision to go for a PhD and have continuously encouraged me to strive for excellence. iv PREFACE The semiconductor industry has long relied on the steady trend of transistor scaling, that is, the shrinking of the dimensions of silicon transistor devices, as a way to improve the cost and performance of electronic devices. However, several design challenges have emerged as transistors have become smaller. For instance, wires are not scaling as fast as transistors, and delay associated with wires is becoming more significant. Moreover, in the design flow for integrated circuits, accurate modeling of wire-related delay is available only toward the end of the design process, when the physical placement of logic units is known. Consequently, one can only know whether timing performance objectives are satisfied, i.e., if timing closure is achieved, after several design optimizations. Unless timing closure is achieved, time-consuming design-flow iterations are required. Given the challenges arising from increasingly complex designs, failing to quickly achieve timing closure threatens the ability of designers to produce high-performance chips that can match continually growing consumer demands. In this dissertation, we introduce powerful constraint-guided synthesis optimizations that take into account upcoming timing closure challenges and eliminate expensive de- sign iterations. In particular, we use logic simulation to approximate the behavior of in- creasingly complex designs leveraging a recently proposed concept, called bit signatures, which allows us to represent a large fraction of a complex circuit’s behavior in a com- v pact data structure. By manipulating these signatures, we can efficiently discover a greater set of valid logic transformations than was previously possible and, as a result, enhance timing optimization. Based on the abstractions enabled through signatures, we propose a comprehensive suite of novel techniques: (1) a fast computation of circuit don’t-cares that increases restructuring opportunities, (2) a verification methodology to prove the cor- rectness of speculative optimizations that efficiently utilizes the computational power of modern multi-core systems, and (3) a physical synthesis strategy using signatures that re-implements sections of a critical path while minimizing perturbations to the existing placement. Our results indicate that logic simulation is effective in approximating the be- havior of complex designs and enables a broader family of optimizations than previous synthesis approaches. vi TABLE OF CONTENTS DEDICATION ................................... ii ACKNOWLEDGEMENTS ............................ iii PREFACE ...................................... v LIST OF FIGURES ................................ xi LIST OF TABLES ................................. xvi LIST OF ABBREVIATIONS ...........................xviii PART I Introduction and Background ......................... 1 Chapter I. Introduction: Overcoming Challenges in Nanometer Design .. 1 1.1 TrendsintheElectronicsandEDAIndustries . ... 1 1.2 Challenges in High-Performance Integrated Circuit Design ...... 3 1.3 Bridging the Gap between Logic and Physical Optimizations..... 7 1.4 Using Simulation-based Abstractions for Circuit Optimizations . 8 1.5 Components of Our Simulation-based Framework ........... 10 1.6 OrganizationoftheDissertation . 11 Chapter II. Synergies between Synthesis, Verification, and Functional Sim- ulation .................................. 14 2.1 ScalableVerification .. .. .. .. .. .. .. 15 2.1.1 Satisfiability........................... 16 2.1.2 PreviousParallelSATApproaches . 20 2.2 ScalableLogicSynthesis . 23 2.2.1 Don’tCareAnalysis . .. .. .. .. .. 23 vii 2.2.2 LogicRewriting......................... 25 2.2.3 Physically-awareSynthesis . 26 2.3 LogicSimulationandBitSignatures . 27 2.4 Summary ................................ 28 Chapter III. Challenges to Achieving Design Closure ............ 29 3.1 PhysicalSynthesis............................ 31 3.2 Advances in Integrated Circuit Design ................. 35 3.3 LimitationsofCurrentIndustrySolutions . .... 38 3.4 ContributionsoftheDissertation . .. 39 II Improving the Quality of Functional Simulation ............... 41 Chapter IV. High-coverage Functional Simulation .............. 42 4.1 Improving Verification Coverage through Automated Constrained-Random Simulation................................ 44 4.2 FindingInactivePartsofaCircuit . 46 4.2.1 ToggleActivityofaSignal . 46 4.2.2 ToggleActivityofMultipleBits . 48 4.3 TargetedRe-simulation . 52 4.3.1 RandomSimulationwithSAT . 52 4.3.2 Partition-TargetedSimulation. 56 4.4 EmpiricalValidation .. .. .. .. .. .. .. 59 4.5 ConcludingRemarks .......................... 63 Chapter V. Enhancing Simulation-based Abstractions with Don’t Cares . 64 5.1 EncodingDon’tCaresinSignatures . 65 5.2 GlobalODCAnalysis.......................... 67 5.2.1 ApproximateODCSimulator. 67 5.2.2 FalsePositivesandFalseNegatives. 69 5.2.3 AnalysisandApproximationofODCs . 70 5.2.4 PerformanceofApproximateSimulator . 73 5.3 ConcludingRemarks .......................... 75 III Improving the Efficiency of Formal Equivalence Checking ........ 76 Chapter VI. Incremental Verification with Don’t Cares ........... 77 6.1 VerifyingSignatureAbstractions . .. 78 viii 6.2 Incremental Equivalence Checking up to Don’t Cares . ..... 81 6.2.1 Moving-dominatorEquivalenceChecker . 81 6.2.2 VerificationAlgorithm . 82 6.2.3 CalculatingDominators. 84 6.3 ConcludingRemarks .......................... 85 Chapter VII. Multi-threaded SAT Solving .................. 87 7.1 Parallel-processingMethodologiesinEDA . .... 87 7.2 RuntimeVariabilityinSATSolving . 91 7.3 SchedulingSATInstancesofVaryingDifficulty . .... 93 7.4 CurrentParallelSATSolvers . 96 7.5 SolvingIndividualHardInstancesinParallel . ...... 97 7.5.1 SearchSpacePartitioning. 98 7.5.2 LightweightParallelSAT . 100 7.6 EmpiricalValidation . 103 7.6.1 EffectiveSchedulingofSATInstances . 103 7.6.2 SolvingIndividualHardProblems . 105 7.6.3 PartitioningStrategies. 108 7.6.4 ParallelLearningStrategies. 109 7.7 ConcludingRemarks .. .. .. .. .. .. .. 110 IV Improving Logic and Physical Synthesis .................. 111 Chapter VIII. Signature-based Manipulations ................ 112 8.1 Logic Transformations through Signature Manipulations ....... 112 8.2 ODC-enhancedNodeMerging . 113 8.2.1 IdentifyingODC-basedNodeMergers . 115 8.2.2 EmpiricalValidation . 117 8.3 DeterminingLogicFeasibilitywithSignatures . ...... 125 8.4 ConcludingRemarks .. .. .. .. .. .. .. 134 Chapter IX. Path-based Physical Resynthesis using Functional Simulation 136 9.1 LogicRestructuringforTimingApplications . ..... 138 9.2 IdentifyingNon-monotonePaths . 139 9.2.1 PathMonotonicity . 139 9.2.2 CalculatingNon-monotoneFactors. 141 9.3 Physically-awareLogicRestructuring . 145 9.3.1 SubcircuitExtraction . 145 9.3.2 Physically-guidedTopologyConstruction . 146 ix 9.4 Enhancing Resynthesis through Global Signature Matching...... 149 9.5 EmpiricalValidation . 150 9.5.1 PrevalenceofNon-monotonicInterconnect . 151 9.5.2 Physically-awareRestructuring . 152 9.5.3 Comparison with Redundancy Addition and Removal .
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