DOCSLIB.ORG

Synthesis and Optimization of Synchronous Logic Circuits

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Synthesis and Optimization of Synchronous Logic Circuits SYNTHESIS AND OPTIMIZATION OF SYNCHRONOUS LOGIC CIRCUITS disserttion sumi ttedtothe deprtmentofeletrilengi neering ndtheommitteeongrdutestudies ofstnforduniversi ty in prtilfulfillmentoftherequirements forthedegreeof dotorofphilosophy By Maurizio Damiani May, 1994 I certify that I have read this thesis and that in my opinion it is fully adequate, in scope and in quality, as a dissertation for the degree of Doctor of Philosophy. Giovanni De Micheli (Principal Adviser) I certify that I have read this thesis and that in my opinion it is fully adequate, in scope and in quality, as a dissertation for the degree of Doctor of Philosophy. David L. Dill I certify that I have read this thesis and that in my opinion it is fully adequate, in scope and in quality, as a dissertation for the degree of Doctor of Philosophy. Teresa Meng Approved for the University Committee on Graduate Stud- ies: Dean of Graduate Studies ii Abstract The design automation of complex digital circuits offers important benefits. It allows the designer to reduce design time and errors, to explore more thoroughly the design space, and to cope effectively with an ever-increasing project complexity. This dissertation presents new algorithms for the logic optimization of combinational and synchronous digital circuits. These algorithms rely on a common paradigm. Namely, global optimization is achieved by the iterative local optimization of small subcircuits. The dissertation first explores the combinational case. Chapter 2 presents algorithms for the optimization of subnetworks consisting of a single-output subcircuit. The design space for this subcircuit is described implicitly by a Boolean function, a so-called don’t care function. Efficient methods for extracting this function are presented. Chapter 3 is devoted to a novel method for the optimization of multiple-output sub- circuits. There, we introduce the notion of compatible gates. Compatible gates represent subsets of gates whose optimization is particularly simple. The other three chapters are devoted to the optimization of synchronous circuits. Fol- lowing the lines of the combinational case, we attempt the optimization of the gate-level (rather than the state diagram -level) representation. In Chapter 4 we focus on extending combinational techniques to the sequential case. In particular, we present algorithms for finding a synchronous don’t care function that can be used in the optimization process. Unlike the combinational case, however, this approach is exact only for pipeline-like circuits. Exact approaches for general, acyclic circuits are presented in Chapter 5. There, we introduce the notion of synchronous recurrence equation. Eventually, Chapter 6 presents methods for handling feedback interconnection. iii Acknowledgements This thesis would not have been possible without the perseverance and guidance of my thesis advisor, Professor Giovanni De Micheli. His continuous support, encouragement, supervision and and constructive criticism made him a reliable reference in the most critical moments of my research. I wish to thank Professor D. Dill for his key suggestions in the many discussions on my work, and the other members of my reading and oral committees, Proff. T. Meng and C. Quate, for their time and patience. I also need to thank my group mates, Polly Siegel, David Ku, Dave Filo, Rajesh Gupta, Frederic Mailhot, Thomas Truong, for making my stay at Stanford especially enjoyable. Special thanks go to Jerry Yang for sharing late night efforts in code and paper writing. He showed plenty of tolerance and self-control towards an impatient writer. I must also acknowledge the dear friends outside my research group. Among them John and Noriko Wallace, Tony and Lydia Pugliese. But I am most indebted to my parents for their love, caring, and understanding, and to my wife Elena, for sharing this experience with me, and helping me in making it through the difficult times. iv Contents Abstract iii Acknowledgements iv 1 Introduction 1 1.1 VLSI and logic synthesis XXXXXXXXXXXXXXXXXXXXXXXXX 1 1.2 Previous work and contributions of this thesis. XXXXXXXXXXXXXX 5 1.2.1 Combinational logic optimization. XXXXXXXXXXXXXXXX 5 1.2.2 Synchronous logic optimization. XXXXXXXXXXXXXXXXXX 10 2 Combinational networks 17 2.1 Introduction XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 17 2.2 Terminology XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 18 2.2.1 Boolean functions and their representations XXXXXXXXXXXX 18 2.2.2 Combinational circuits and logic networks. XXXXXXXXXXXX 19 2.2.3 Specifications for combinational networks. XXXXXXXXXXXX 21 2.2.4 Optimization of combinational multiple-level circuits XXXXXXX 21 2.3 Perturbation analysis of combinational networks. XXXXXXXXXXXXX 23 2.3.1 Single-vertex optimization and observability don’t cares . XXXX 26 2.4 Multi-vertex optimization and compatible don’t cares XXXXXXXXXX 41 2.5 Approximating observability don’t cares XXXXXXXXXXXXXXXXX 53 2.5.1 Experimental results. XXXXXXXXXXXXXXXXXXXXXXX 59 2.6 Summary XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 61 v 3 Multi-vertex optimization with compatible gates 63 3.1 Related Previous Work XXXXXXXXXXXXXXXXXXXXXXXXXXX 65 3.1.1 Two-level Synthesis XXXXXXXXXXXXXXXXXXXXXXXX 65 3.1.2 Boolean Relations-based Multiple-level Optimization XXXXXXX 66 3.2 Compatible Gates XXXXXXXXXXXXXXXXXXXXXXXXXXXXX 69 3.3 Optimizing Compatible Gates XXXXXXXXXXXXXXXXXXXXXXX 70 3.3.1 Implicant Extraction XXXXXXXXXXXXXXXXXXXXXXXX 70 3.3.2 Covering Step XXXXXXXXXXXXXXXXXXXXXXXXXXX 71 3.4 Finding Compatible Gates XXXXXXXXXXXXXXXXXXXXXXXXX 75 3.5 Unate Optimization XXXXXXXXXXXXXXXXXXXXXXXXXXXX 81 3.5.1 Optimizing Unate Subsets XXXXXXXXXXXXXXXXXXXXX 81 3.5.2 Implicant Extraction XXXXXXXXXXXXXXXXXXXXXXXX 81 3.5.3 Covering Step XXXXXXXXXXXXXXXXXXXXXXXXXXX 84 3.6 Implementation and Results XXXXXXXXXXXXXXXXXXXXXXXX 87 3.7 Summary XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 89 4 Acyclic synchronous networks 91 4.1 Terminology XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 92 4.1.1 Synchronous logic networks. XXXXXXXXXXXXXXXXXXX 92 4.1.2 Sequences and sequence functions. XXXXXXXXXXXXXXXX 93 4.1.3 Pattern expressions and functions. XXXXXXXXXXXXXXXXX 94 4.1.4 Functional modeling of synchronous circuits. XXXXXXXXXXX 98 4.2 Sequential don’t cares XXXXXXXXXXXXXXXXXXXXXXXXXXX 99 4.2.1 Retiming-invariant don’t care conditions XXXXXXXXXXXXX 100 4.2.2 Controllability and observability don’t cares XXXXXXXXXXX 101 4.3 Local optimization of acyclic networks XXXXXXXXXXXXXXXXXX 105 4.3.1 Internal observability don’t care conditions. XXXXXXXXXXXX 106 4.4 Computation of observability don’t cares in acyclic networks XXXXXX 112 4.5 Experimental results. XXXXXXXXXXXXXXXXXXXXXXXXXXXX 114 4.6 Summary XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 115 vi 5 Recurrence Equations 116 5.1 Introduction XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 116 5.2 Synchronous Recurrence Equations XXXXXXXXXXXXXXXXXXXX 119 5.2.1 Optimization of synchronous circuits by recurrence equations XX 119 5.3 Finding acyclic solutions. XXXXXXXXXXXXXXXXXXXXXXXXX 120 5.3.1 Representing feasible solutions XXXXXXXXXXXXXXXXXX 120 5.4 Minimum cost solutions. XXXXXXXXXXXXXXXXXXXXXXXXXX 125 5.4.1 Extraction of primes XXXXXXXXXXXXXXXXXXXXXXXX 126 5.4.2 Covering Step. XXXXXXXXXXXXXXXXXXXXXXXXXXX 130 5.5 Recurrence equations for sequential optimization. XXXXXXXXXXXXX 132 5.5.1 Image of a SRE. XXXXXXXXXXXXXXXXXXXXXXXXXX 133 5.6 Implementation and experimental results. XXXXXXXXXXXXXXXXX 134 5.7 Summary. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 135 6 Cyclic synchronous networks 137 6.1 Modeling of cyclic networks. XXXXXXXXXXXXXXXXXXXXXXX 138 6.1.1 The reset assumption. XXXXXXXXXXXXXXXXXXXXXXX 139 6.2 Feedback and external controllability don’t cares XXXXXXXXXXXXX 140 6.2.1 Don’t cares and state-space traversals XXXXXXXXXXXXXXX 144 6.3 Perturbation analysis of cyclic networks. XXXXXXXXXXXXXXXXX 145 6.3.1 An iterative procedure for external observability don’t cares . XX 148 6.4 Experimental results. XXXXXXXXXXXXXXXXXXXXXXXXXXXX 151 6.5 Summary XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 152 7 Conclusions 153 Bibliography 155 vii Chapter 1 Introduction Logic synthesis is the process of transforming a register-transfer level description of a design into an optimal logic-level representation. Traditionally, it has been divided into combinational and sequential synthesis. This chapter first reviews the VLSI design pro- cess, describing the role played by logic synthesis, its status, and previous contributions in the field. It then provides an outline of this dissertation, highlighting the contributions of this work. 1.1 VLSI and logic synthesis Very Large Scale Integration (VLSI) has emerged as a central technology for the real- ization of complex digital systems. The benefits in terms of performance, reliability, and cost reduction of integrating large systems on a single chip have pushed designs from the tens of thousands of transistors into the millions in just over a decade. Computer aids play an important role in coping with the complexity of such designs, by partitioning them into a sequence of well-defined steps. Quality and time-to market of the final product are also improved by automating the most tedious, lengthy and error-prone phases of the project. The design process typically begins with a functional description of the desired func- tionality by means of a high-level description language. Several languages have been developed to this purpose (VHDL, VerilogHDL, HardwareC) [1]. 1 CHAPTER 1. INTRODUCTION 2 High-level synthesis is the first design step for which CAD tools have been developed. It consists of mapping a functional description
Load more

Recommended publications
  • Optimization of Combinational Logic Circuits Based on Compatible Gates
    COMPUTER SYSTEMS LABORATORY STANFORD UNIVERSITY STANFORD, CA 94305455 Optimization of Combinational Logic Circuits Based on Compatible Gates Maurizio Damiani Jerry Chih-Yuan Yang Giovanni De Micheli Technical Report: CSL-TR-93-584 September 1993 This research is sponsored by NSF and DEC under a PYI award and by ARPA and NSF under contract MIP 9115432. Optimization of Combinational Logic Circuits Based on Compatible Gates Maurizio Damiani * Jerry Chih- Yuan Yang Giovanni De Micheli Technical Report: CSL-TR-93-584 September, 1993 Computer Systems Laboratory Departments of Electrical Engineering and Computer Science Stanford University, Stanford CA 94305-4055 Abstract This paper presents a set of new techniques for the optimization of multiple-level combinational Boolean networks. We describe first a technique based upon the selection of appropriate multiple- output subnetworks (consisting of so-called compatible gates) whose local functions can be op- timized simultaneously. We then generalize the method to larger and more arbitrary subsets of gates. Because simultaneous optimization of local functions can take place, our methods are more powerful and general than Boolean optimization methods using don’t cares , where only single-gate optimization can be performed. In addition, our methods represent a more efficient alternative to optimization procedures based on Boolean relations because the problem can be modeled by a unate covering problem instead of the more difficult binate covering problem. The method is implemented in program ACHILLES and compares favorably to SIS. Key Words and Phrases: Combinational logic synthesis, don’t care methods. *Now with the Dipartimento di Elettronica ed Informatica, UniversitB di Padova, Via Gradenigo 6/A, Padova, Italy.
    [Show full text]
  • Synthesis and Verification of Digital Circuits Using Functional Simulation and Boolean Satisfiability
    Synthesis and Verification of Digital Circuits using Functional Simulation and Boolean Satisfiability by Stephen M. Plaza A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Computer Science and Engineering) in The University of Michigan 2008 Doctoral Committee: Associate Professor Igor L. Markov, Co-Chair Assistant Professor Valeria M. Bertacco, Co-Chair Professor John P. Hayes Professor Karem A. Sakallah Associate Professor Dennis M. Sylvester Stephen M. Plaza 2008 c All Rights Reserved To my family, friends, and country ii ACKNOWLEDGEMENTS I would like to thank my advisers, Professor Igor Markov and Professor Valeria Bertacco, for inspiring me to consider various fields of research and providing feedback on my projects and papers. I also want to thank my defense committee for their comments and in- sights: Professor John Hayes, Professor Karem Sakallah, and Professor Dennis Sylvester. I would like to thank Professor David Kieras for enhancing my knowledge and apprecia- tion for computer programming and providing invaluable advice. Over the years, I have been fortunate to know and work with several wonderful stu- dents. I have collaborated extensively with Kai-hui Chang and Smita Krishnaswamy and have enjoyed numerous research discussions with them and have benefited from their in- sights. I would like to thank Ian Kountanis and Zaher Andraus for our many fun discus- sions on parallel SAT. I also appreciate the time spent collaborating with Kypros Constan- tinides and Jason Blome. Although I have not formally collaborated with Ilya Wagner, I have enjoyed numerous discussions with him during my doctoral studies. I also thank my office mates Jarrod Roy, Jin Hu, and Hector Garcia.
    [Show full text]
  • A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks
    A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks Eleonora Testa∗, Mathias Soekeny, Heinz Riener∗, Luca Amaruz and Giovanni De Micheli∗ ∗Integrated Systems Laboratory, EPFL, Lausanne, Switzerland yMicrosoft, Switzerland zSynopsys Inc., Design Group, Sunnyvale, California, USA Abstract—Logic synthesis is a fundamental step in the real- correlates to the resistance of the function against algebraic ization of modern integrated circuits. It has traditionally been attacks [10], while the multiplicative complexity of a logic employed for the optimization of CMOS-based designs, as well network implementing that function only provides an upper as for emerging technologies and quantum computing. Recently, bound. Consequently, minimizing the multiplicative complexity it found application in minimizing the number of AND gates in of a network is important to assess the real multiplicative cryptography benchmarks represented as xor-and graphs (XAGs). complexity of the function, and therefore its vulnerability. The number of AND gates in an XAG, which is called the logic net- work’s multiplicative complexity, plays a critical role in various Second, the number of AND gates plays an important role cryptography and security protocols such as fully homomorphic in high-level cryptography protocols such as zero-knowledge encryption (FHE) and secure multi-party computation (MPC). protocols, fully homomorphic encryption (FHE), and secure Further, the number of AND gates is also important to assess multi-party computation (MPC) [11], [12], [6]. For example, the the degree of vulnerability of a Boolean function, and influences size of the signature in post-quantum zero-knowledge signatures the cost of techniques to protect against side-channel attacks.
    [Show full text]
  • Logic Optimization and Synthesis: Trends and Directions in Industry
    Logic Optimization and Synthesis: Trends and Directions in Industry Luca Amaru´∗, Patrick Vuillod†, Jiong Luo∗, Janet Olson∗ ∗ Synopsys Inc., Design Group, Sunnyvale, California, USA † Synopsys Inc., Design Group, Grenoble, France Abstract—Logic synthesis is a key design step which optimizes of specific logic styles and cell layouts. Embedding as much abstract circuit representations and links them to technology. technology information as possible early in the logic optimiza- With CMOS technology moving into the deep nanometer regime, tion engine is key to make advantageous logic restructuring logic synthesis needs to be aware of physical informations early in the flow. With the rise of enhanced functionality nanodevices, opportunities carry over at the end of the design flow. research on technology needs the help of logic synthesis to capture In this paper, we examine the synergy between logic synthe- advantageous design opportunities. This paper deals with the syn- sis and technology, from an industrial perspective. We present ergy between logic synthesis and technology, from an industrial technology aware synthesis methods incorporating advanced perspective. First, we present new synthesis techniques which physical information at the core optimization engine. Internal embed detailed physical informations at the core optimization engine. Experiments show improved Quality of Results (QoR) and results evidence faster timing closure and better correlation better correlation between RTL synthesis and physical implemen- between RTL synthesis and physical implementation. We elab- tation. Second, we discuss the application of these new synthesis orate on synthesis aware technology development, where logic techniques in the early assessment of emerging nanodevices with synthesis enables a fair system-level assessment on emerging enhanced functionality.
    [Show full text]
  • Designing a RISC CPU in Reversible Logic
    Designing a RISC CPU in Reversible Logic Robert Wille Mathias Soeken Daniel Große Eleonora Schonborn¨ Rolf Drechsler Institute of Computer Science, University of Bremen, 28359 Bremen, Germany frwille,msoeken,grosse,eleonora,[email protected] Abstract—Driven by its promising applications, reversible logic In this paper, the recent progress in the field of reversible cir- received significant attention. As a result, an impressive progress cuit design is employed in order to design a complex system, has been made in the development of synthesis approaches, i.e. a RISC CPU composed of reversible gates. Starting from implementation of sequential elements, and hardware description languages. In this paper, these recent achievements are employed a textual specification, first the core components of the CPU in order to design a RISC CPU in reversible logic that can are identified. Previously introduced approaches are applied execute software programs written in an assembler language. The next to realize the respective combinational and sequential respective combinational and sequential components are designed elements. More precisely, the combinational components are using state-of-the-art design techniques. designed using the reversible hardware description language SyReC [17], whereas for the realization of the sequential I. INTRODUCTION elements an external controller (as suggested in [16]) is utilized. With increasing miniaturization of integrated circuits, the Plugging the respective components together, a CPU design reduction of power dissipation has become a crucial issue in results which can process software programs written in an today’s hardware design process. While due to high integration assembler language. This is demonstrated in a case study, density and new fabrication processes, energy loss has sig- where the execution of a program determining Fibonacci nificantly been reduced over the last decades, physical limits numbers is simulated.
    [Show full text]
  • Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization
    Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization Shubham Raif,6,y, Walter Lau Neton,10,y, Yukio Miyasakao,1, Xinpei Zhanga,1, Mingfei Yua,1, Qingyang Yia,1, Masahiro Fujitaa,1, Guilherme B. Manskeb,2, Matheus F. Pontesb,2, Leomar S. da Rosa Juniorb,2, Marilton S. de Aguiarb,2, Paulo F. Butzene,2, Po-Chun Chienc,3, Yu-Shan Huangc,3, Hoa-Ren Wangc,3, Jie-Hong R. Jiangc,3, Jiaqi Gud,4, Zheng Zhaod,4, Zixuan Jiangd,4, David Z. Pand,4, Brunno A. de Abreue,5,9, Isac de Souza Camposm,5,9, Augusto Berndtm,5,9, Cristina Meinhardtm,5,9, Jonata T. Carvalhom,5,9, Mateus Grellertm,5,9, Sergio Bampie,5, Aditya Lohanaf,6, Akash Kumarf,6, Wei Zengj,7, Azadeh Davoodij,7, Rasit O. Topalogluk,7, Yuan Zhoul,8, Jordan Dotzell,8, Yichi Zhangl,8, Hanyu Wangl,8, Zhiru Zhangl,8, Valerio Tenacen,10, Pierre-Emmanuel Gaillardonn,10, Alan Mishchenkoo,y, and Satrajit Chatterjeep,y aUniversity of Tokyo, Japan, bUniversidade Federal de Pelotas, Brazil, cNational Taiwan University, Taiwan, dUniversity of Texas at Austin, USA, eUniversidade Federal do Rio Grande do Sul, Brazil, fTechnische Universitaet Dresden, Germany, jUniversity of Wisconsin–Madison, USA, kIBM, USA, lCornell University, USA, mUniversidade Federal de Santa Catarina, Brazil, nUniversity of Utah, USA, oUC Berkeley, USA, pGoogle AI, USA The alphabetic characters in the superscript represent the affiliations while the digits represent the team numbers yEqual contribution. Email: [email protected], [email protected], [email protected], [email protected] Abstract—Logic synthesis is a fundamental step in hard- artificial intelligence.
    [Show full text]
  • Basic Boolean Algebra and Logic Optimization
    Fundamental Algorithms for System Modeling, Analysis, and Optimization Edward A. Lee, Jaijeet Roychowdhury, Sanjit A. Seshia UC Berkeley EECS 144/244 Fall 2011 Copyright © 2010-11, E. A. Lee, J. Roychowdhury, S. A. Seshia, All rights reserved Lec 3: Boolean Algebra and Logic Optimization - 1 Thanks to S. Devadas, K. Keutzer, S. Malik, R. Rutenbar for several slides RTL Synthesis Flow FSM, HDL Verilog, HDL Simulation/ VHDL Verification RTL Synthesis a 0 d q Boolean circuit/network 1 netlist b Library/ s clk module logic generators optimization a 0 d q Boolean circuit/network netlist b 1 s clk physical design Graph / Rectangles layout K. Keutzer EECS 144/244, UC Berkeley: 2 Reduce Sequential Ckt Optimization to Combinational Optimization B Flip-flops inputs Combinational outputs Logic Optimize the size/delay/etc. of the combinational circuit (viewed as a Boolean network) EECS 144/244, UC Berkeley: 3 Logic Optimization 2-level Logic opt netlist tech multilevel independent Logic opt logic Library optimization tech dependent Generic Library netlist Real Library EECS 144/244, UC Berkeley: 4 Outline of Topics Basics of Boolean algebra Two-level logic optimization Multi-level logic optimization Boolean function representation: BDDs EECS 144/244, UC Berkeley: 5 Definitions – 1: What is a Boolean function? EECS 144/244, UC Berkeley: 6 Definitions – 1: What is a Boolean function? Let B = {0, 1} and Y = {0, 1} Input variables: X1, X2 …Xn Output variables: Y1, Y2 …Ym A logic function ff (or ‘Boolean’ function, switching function) in n inputs and m
    [Show full text]
  • The Basics of Logic Design
    C APPENDIX The Basics of Logic Design C.1 Introduction C-3 I always loved that C.2 Gates, Truth Tables, and Logic word, Boolean. Equations C-4 C.3 Combinational Logic C-9 Claude Shannon C.4 Using a Hardware Description IEEE Spectrum, April 1992 Language (Shannon’s master’s thesis showed that C-20 the algebra invented by George Boole in C.5 Constructing a Basic Arithmetic Logic the 1800s could represent the workings of Unit C-26 electrical switches.) C.6 Faster Addition: Carry Lookahead C-38 C.7 Clocks C-48 AAppendixC-9780123747501.inddppendixC-9780123747501.indd 2 226/07/116/07/11 66:28:28 PPMM C.8 Memory Elements: Flip-Flops, Latches, and Registers C-50 C.9 Memory Elements: SRAMs and DRAMs C-58 C.10 Finite-State Machines C-67 C.11 Timing Methodologies C-72 C.12 Field Programmable Devices C-78 C.13 Concluding Remarks C-79 C.14 Exercises C-80 C.1 Introduction This appendix provides a brief discussion of the basics of logic design. It does not replace a course in logic design, nor will it enable you to design signifi cant working logic systems. If you have little or no exposure to logic design, however, this appendix will provide suffi cient background to understand all the material in this book. In addition, if you are looking to understand some of the motivation behind how computers are implemented, this material will serve as a useful intro- duction. If your curiosity is aroused but not sated by this appendix, the references at the end provide several additional sources of information.
    [Show full text]
  • Gate Logic Logic Optimization Overview
    Lecture 5: Gate Logic Logic Optimization MAH, AEN EE271 Lecture 5 1 Overview Reading McCluskey, Logic Design Principles- or any text in boolean algebra Introduction We could design at the level of irsim - Think about transistors as switches - Build collections of switches that do useful stuff - Don’t much care whether the collection of transistors is a gate, switch logic, or some combination. It is a collection of switches. But this is pretty complicated - Switches are bidirectional, charge-sharing, - Need to worry about series resistance… MAH, AEN EE271 Lecture 5 2 Logic Gates Constrain the problem to simplify it. • Constrain how one can connect transistors - Create a collection of transistors where the Output is always driven by a switch-network to a supply (not an input) And the inputs to this unit only connect the gate of the transistors • Model this collection of transistors by a simpler abstraction Units are unidirectional Function is modelled by boolean operations Capacitance only affects speed and not functionality Delay through network is sum of delays of elements This abstract model is one we have used already. • It is a logic gate MAH, AEN EE271 Lecture 5 3 Logic Gates Come in various forms and sizes In CMOS, all of the primitive gates1 have one inversion from each input to the output. There are many versions of primitive gates. Different libraries have different collections. In general, most libraries have all 3 input gates (NAND, NOR, AOI, and OAI gates) and some 4 input gates. Most libraries are much richer, and have a large number of gates.
    [Show full text]
  • Logical Equivalence Checking of Asynchronous Circuits Using Commercial Tools
    Logical Equivalence Checking of Asynchronous Circuits Using Commercial Tools Arash Saifhashemi Hsin-Ho Huang Priyanka Bhalerao Peter A. Beerel∗ Intel Corporation Electrical Engineering Yahoo Corporation Electrical Engineering Santa Clara, CA University of Southern California Sunnyvale, CA University of Southern California Email: [email protected] Los Angeles, CA Email: [email protected] Los Angeles, CA Email: [email protected] Email: [email protected] Abstract—We propose a method for logical equivalence check generally cannot be used to compare CSP with decomposed (LEC) of asynchronous circuits using commercial synchronous versions because the decomposition often introduces pipelining tools. In particular, we verify the equivalence of asynchronous that changes the allowed sequence of events at the external circuits which are modeled at the CSP-level in SystemVerilog as interface. Therefore, some researchers only check critical prop- well as circuits modeled at the micro-architectural level using con- erties on the final decomposed design [15], [16]. ditional communication library primitives. Our approach is based on a novel three-valued logic model that abstracts the detailed Our proposed approach is different from the previous work handshaking protocol and is thus agnostic to different gate-level in the following ways: first, since it is focused on CSP- implementations, making it applicable to a variety of different level designs, it is implementation-agnostic and can be used design styles. Our experimental results with commercial LEC for design flows that target various asynchronous templates. tools on a variety of computational blocks and an asynchronous Secondly, compared to [11], we explicitly support modules microprocessor demonstrate the applicability and limitations of the proposed approach.
    [Show full text]
  • Verilog HDL 1
    chapter 1.fm Page 3 Friday, January 24, 2003 1:44 PM Overview of Digital Design with Verilog HDL 1 1.1 Evolution of Computer-Aided Digital Design Digital circuit design has evolved rapidly over the last 25 years. The earliest digital circuits were designed with vacuum tubes and transistors. Integrated circuits were then invented where logic gates were placed on a single chip. The first integrated circuit (IC) chips were SSI (Small Scale Integration) chips where the gate count was very small. As technologies became sophisticated, designers were able to place circuits with hundreds of gates on a chip. These chips were called MSI (Medium Scale Integration) chips. With the advent of LSI (Large Scale Integration), designers could put thousands of gates on a single chip. At this point, design processes started getting very complicated, and designers felt the need to automate these processes. Electronic Design Automation (EDA)1 techniques began to evolve. Chip designers began to use circuit and logic simulation techniques to verify the functionality of building blocks of the order of about 100 transistors. The circuits were still tested on the breadboard, and the layout was done on paper or by hand on a graphic computer terminal. With the advent of VLSI (Very Large Scale Integration) technology, designers could design single chips with more than 100,000 transistors. Because of the complexity of these circuits, it was not possible to verify these circuits on a breadboard. Computer- aided techniques became critical for verification and design of VLSI digital circuits. Computer programs to do automatic placement and routing of circuit layouts also became popular.
    [Show full text]
  • Deep Learning for Logic Optimization Algorithms
    Deep Learning for Logic Optimization Algorithms Winston Haaswijky∗, Edo Collinsz∗, Benoit Seguinx∗, Mathias Soekeny, Fred´ eric´ Kaplanx, Sabine Susstrunk¨ z, Giovanni De Micheliy yIntegrated Systems Laboratory, EPFL, Lausanne, VD, Switzerland zImage and Visual Representation Lab, EPFL, Lausanne, VD, Switzerland xDigital Humanities Laboratory, EPFL, Lausanne, VD, Switzerland ∗These authors contributed equally to this work Abstract—The slowing down of Moore’s law and the emergence to the state-of-the-art. Finally, our algorithm is a generic of new technologies puts an increasing pressure on the field optimization method. We show that it is capable of performing of EDA. There is a constant need to improve optimization depth optimization, obtaining 92.6% of potential improvement algorithms. However, finding and implementing such algorithms is a difficult task, especially with the novel logic primitives and in depth optimization of 3-input functions. Further, the MCNC potentially unconventional requirements of emerging technolo- case study shows that we unlock significant depth improvements gies. In this paper, we cast logic optimization as a deterministic over the academic state-of-the-art, ranging from 12.5% to Markov decision process (MDP). We then take advantage of 47.4%. recent advances in deep reinforcement learning to build a system that learns how to navigate this process. Our design has a II. BACKGROUND number of desirable properties. It is autonomous because it learns automatically and does not require human intervention. A. Deep Learning It generalizes to large functions after training on small examples. With ever growing data sets and increasing computational Additionally, it intrinsically supports both single- and multi- output functions, without the need to handle special cases.
    [Show full text]