SYNTHESIS AND OPTIMIZATION OF SYNCHRONOUS LOGIC CIRCUITS disserttion sumi ttedtothe deprtmentofeletrilengi neering ndtheommitteeongrdutestudies ofstnforduniversi ty in prtilfulfillmentoftherequirements forthedegreeof dotorofphilosophy By Maurizio Damiani May, 1994 I certify that I have read this thesis and that in my opinion it is fully adequate, in scope and in quality, as a dissertation for the degree of Doctor of Philosophy. Giovanni De Micheli (Principal Adviser) I certify that I have read this thesis and that in my opinion it is fully adequate, in scope and in quality, as a dissertation for the degree of Doctor of Philosophy. David L. Dill I certify that I have read this thesis and that in my opinion it is fully adequate, in scope and in quality, as a dissertation for the degree of Doctor of Philosophy. Teresa Meng Approved for the University Committee on Graduate Stud- ies: Dean of Graduate Studies ii Abstract The design automation of complex digital circuits offers important benefits. It allows the designer to reduce design time and errors, to explore more thoroughly the design space, and to cope effectively with an ever-increasing project complexity. This dissertation presents new algorithms for the logic optimization of combinational and synchronous digital circuits. These algorithms rely on a common paradigm. Namely, global optimization is achieved by the iterative local optimization of small subcircuits. The dissertation first explores the combinational case. Chapter 2 presents algorithms for the optimization of subnetworks consisting of a single-output subcircuit. The design space for this subcircuit is described implicitly by a Boolean function, a so-called don’t care function. Efficient methods for extracting this function are presented. Chapter 3 is devoted to a novel method for the optimization of multiple-output sub- circuits. There, we introduce the notion of compatible gates. Compatible gates represent subsets of gates whose optimization is particularly simple. The other three chapters are devoted to the optimization of synchronous circuits. Fol- lowing the lines of the combinational case, we attempt the optimization of the gate-level (rather than the state diagram -level) representation. In Chapter 4 we focus on extending combinational techniques to the sequential case. In particular, we present algorithms for finding a synchronous don’t care function that can be used in the optimization process. Unlike the combinational case, however, this approach is exact only for pipeline-like circuits. Exact approaches for general, acyclic circuits are presented in Chapter 5. There, we introduce the notion of synchronous recurrence equation. Eventually, Chapter 6 presents methods for handling feedback interconnection. iii Acknowledgements This thesis would not have been possible without the perseverance and guidance of my thesis advisor, Professor Giovanni De Micheli. His continuous support, encouragement, supervision and and constructive criticism made him a reliable reference in the most critical moments of my research. I wish to thank Professor D. Dill for his key suggestions in the many discussions on my work, and the other members of my reading and oral committees, Proff. T. Meng and C. Quate, for their time and patience. I also need to thank my group mates, Polly Siegel, David Ku, Dave Filo, Rajesh Gupta, Frederic Mailhot, Thomas Truong, for making my stay at Stanford especially enjoyable. Special thanks go to Jerry Yang for sharing late night efforts in code and paper writing. He showed plenty of tolerance and self-control towards an impatient writer. I must also acknowledge the dear friends outside my research group. Among them John and Noriko Wallace, Tony and Lydia Pugliese. But I am most indebted to my parents for their love, caring, and understanding, and to my wife Elena, for sharing this experience with me, and helping me in making it through the difficult times. iv Contents Abstract iii Acknowledgements iv 1 Introduction 1 1.1 VLSI and logic synthesis XXXXXXXXXXXXXXXXXXXXXXXXX 1 1.2 Previous work and contributions of this thesis. XXXXXXXXXXXXXX 5 1.2.1 Combinational logic optimization. XXXXXXXXXXXXXXXX 5 1.2.2 Synchronous logic optimization. XXXXXXXXXXXXXXXXXX 10 2 Combinational networks 17 2.1 Introduction XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 17 2.2 Terminology XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 18 2.2.1 Boolean functions and their representations XXXXXXXXXXXX 18 2.2.2 Combinational circuits and logic networks. XXXXXXXXXXXX 19 2.2.3 Specifications for combinational networks. XXXXXXXXXXXX 21 2.2.4 Optimization of combinational multiple-level circuits XXXXXXX 21 2.3 Perturbation analysis of combinational networks. XXXXXXXXXXXXX 23 2.3.1 Single-vertex optimization and observability don’t cares . XXXX 26 2.4 Multi-vertex optimization and compatible don’t cares XXXXXXXXXX 41 2.5 Approximating observability don’t cares XXXXXXXXXXXXXXXXX 53 2.5.1 Experimental results. XXXXXXXXXXXXXXXXXXXXXXX 59 2.6 Summary XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 61 v 3 Multi-vertex optimization with compatible gates 63 3.1 Related Previous Work XXXXXXXXXXXXXXXXXXXXXXXXXXX 65 3.1.1 Two-level Synthesis XXXXXXXXXXXXXXXXXXXXXXXX 65 3.1.2 Boolean Relations-based Multiple-level Optimization XXXXXXX 66 3.2 Compatible Gates XXXXXXXXXXXXXXXXXXXXXXXXXXXXX 69 3.3 Optimizing Compatible Gates XXXXXXXXXXXXXXXXXXXXXXX 70 3.3.1 Implicant Extraction XXXXXXXXXXXXXXXXXXXXXXXX 70 3.3.2 Covering Step XXXXXXXXXXXXXXXXXXXXXXXXXXX 71 3.4 Finding Compatible Gates XXXXXXXXXXXXXXXXXXXXXXXXX 75 3.5 Unate Optimization XXXXXXXXXXXXXXXXXXXXXXXXXXXX 81 3.5.1 Optimizing Unate Subsets XXXXXXXXXXXXXXXXXXXXX 81 3.5.2 Implicant Extraction XXXXXXXXXXXXXXXXXXXXXXXX 81 3.5.3 Covering Step XXXXXXXXXXXXXXXXXXXXXXXXXXX 84 3.6 Implementation and Results XXXXXXXXXXXXXXXXXXXXXXXX 87 3.7 Summary XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 89 4 Acyclic synchronous networks 91 4.1 Terminology XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 92 4.1.1 Synchronous logic networks. XXXXXXXXXXXXXXXXXXX 92 4.1.2 Sequences and sequence functions. XXXXXXXXXXXXXXXX 93 4.1.3 Pattern expressions and functions. XXXXXXXXXXXXXXXXX 94 4.1.4 Functional modeling of synchronous circuits. XXXXXXXXXXX 98 4.2 Sequential don’t cares XXXXXXXXXXXXXXXXXXXXXXXXXXX 99 4.2.1 Retiming-invariant don’t care conditions XXXXXXXXXXXXX 100 4.2.2 Controllability and observability don’t cares XXXXXXXXXXX 101 4.3 Local optimization of acyclic networks XXXXXXXXXXXXXXXXXX 105 4.3.1 Internal observability don’t care conditions. XXXXXXXXXXXX 106 4.4 Computation of observability don’t cares in acyclic networks XXXXXX 112 4.5 Experimental results. XXXXXXXXXXXXXXXXXXXXXXXXXXXX 114 4.6 Summary XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 115 vi 5 Recurrence Equations 116 5.1 Introduction XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 116 5.2 Synchronous Recurrence Equations XXXXXXXXXXXXXXXXXXXX 119 5.2.1 Optimization of synchronous circuits by recurrence equations XX 119 5.3 Finding acyclic solutions. XXXXXXXXXXXXXXXXXXXXXXXXX 120 5.3.1 Representing feasible solutions XXXXXXXXXXXXXXXXXX 120 5.4 Minimum cost solutions. XXXXXXXXXXXXXXXXXXXXXXXXXX 125 5.4.1 Extraction of primes XXXXXXXXXXXXXXXXXXXXXXXX 126 5.4.2 Covering Step. XXXXXXXXXXXXXXXXXXXXXXXXXXX 130 5.5 Recurrence equations for sequential optimization. XXXXXXXXXXXXX 132 5.5.1 Image of a SRE. XXXXXXXXXXXXXXXXXXXXXXXXXX 133 5.6 Implementation and experimental results. XXXXXXXXXXXXXXXXX 134 5.7 Summary. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 135 6 Cyclic synchronous networks 137 6.1 Modeling of cyclic networks. XXXXXXXXXXXXXXXXXXXXXXX 138 6.1.1 The reset assumption. XXXXXXXXXXXXXXXXXXXXXXX 139 6.2 Feedback and external controllability don’t cares XXXXXXXXXXXXX 140 6.2.1 Don’t cares and state-space traversals XXXXXXXXXXXXXXX 144 6.3 Perturbation analysis of cyclic networks. XXXXXXXXXXXXXXXXX 145 6.3.1 An iterative procedure for external observability don’t cares . XX 148 6.4 Experimental results. XXXXXXXXXXXXXXXXXXXXXXXXXXXX 151 6.5 Summary XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 152 7 Conclusions 153 Bibliography 155 vii Chapter 1 Introduction Logic synthesis is the process of transforming a register-transfer level description of a design into an optimal logic-level representation. Traditionally, it has been divided into combinational and sequential synthesis. This chapter first reviews the VLSI design pro- cess, describing the role played by logic synthesis, its status, and previous contributions in the field. It then provides an outline of this dissertation, highlighting the contributions of this work. 1.1 VLSI and logic synthesis Very Large Scale Integration (VLSI) has emerged as a central technology for the real- ization of complex digital systems. The benefits in terms of performance, reliability, and cost reduction of integrating large systems on a single chip have pushed designs from the tens of thousands of transistors into the millions in just over a decade. Computer aids play an important role in coping with the complexity of such designs, by partitioning them into a sequence of well-defined steps. Quality and time-to market of the final product are also improved by automating the most tedious, lengthy and error-prone phases of the project. The design process typically begins with a functional description of the desired func- tionality by means of a high-level description language. Several languages have been developed to this purpose (VHDL, VerilogHDL, HardwareC) [1]. 1 CHAPTER 1. INTRODUCTION 2 High-level synthesis is the first design step for which CAD tools have been developed. It consists of mapping a functional description